JPS59132145A - Forming method of electrode of semiconductor device - Google Patents
Forming method of electrode of semiconductor deviceInfo
- Publication number
- JPS59132145A JPS59132145A JP58007028A JP702883A JPS59132145A JP S59132145 A JPS59132145 A JP S59132145A JP 58007028 A JP58007028 A JP 58007028A JP 702883 A JP702883 A JP 702883A JP S59132145 A JPS59132145 A JP S59132145A
- Authority
- JP
- Japan
- Prior art keywords
- silver
- metal layer
- layer
- electrode
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の電極形成方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming electrodes of a semiconductor device.
半導体装置にあって、特にガラス封止接合によりて組み
立てられるもの1例えば小信号ダイオードでは、チップ
の機能領域上の電極が、バンプを形成しなければならな
い。すなわち、チップの表面側において、数ミクロンな
いし数十ミクロンの厚さに形成する半球状に盛シ上った
金属層が、機能領域と電気的、かつ機械的に接合されて
いる必要がある。BACKGROUND OF THE INVENTION In semiconductor devices, especially those assembled by glass-sealing bonding, such as small signal diodes, the electrodes on the functional areas of the chip must form bumps. That is, on the front side of the chip, a hemispherically raised metal layer formed to a thickness of several microns to several tens of microns needs to be electrically and mechanically connected to the functional area.
このような要求を満足させるために、従来装置の電極構
造は、第1図に示されているように、機能領域としての
ベース領域(2)を拡散形成したシリコンウェハ(1)
上に、絶縁膜としてのシリコン酸化膜(3)を形成し、
かつコンタクトホールを開口した状態としておき、一般
的にはコンタクトホール上に、アルミニウムによる電極
形成後に、銀をメッキによシバンブ形成させることが行
なわれ、また高信頼性の半導体デぶイスでは、バリアメ
タルとしてのチタン・タングステン層(4)、ついで金
層(5)を順次に蒸着、あるいはスパッタリングによ多
形成したのち、選択メッキ法などで金バンプ(6)を形
成するようにしている。In order to satisfy these requirements, the electrode structure of the conventional device is based on a silicon wafer (1) on which a base region (2) as a functional region is diffused, as shown in FIG.
A silicon oxide film (3) is formed on top as an insulating film,
In addition, the contact hole is left open, and after forming an electrode with aluminum, silver is generally plated on the contact hole.Also, in highly reliable semiconductor devices, barrier After a titanium/tungsten layer (4) as a metal and then a gold layer (5) are sequentially formed by vapor deposition or sputtering, gold bumps (6) are formed by selective plating or the like.
しかし乍らこのような従来の電極形成手段によると、寸
ず前者のアルミニウムー銀系の場合には、アルミニウム
ー銀量の接着強度が安定しない不都合があった。これは
酸化され易いアルミニウムの上に銀メッキを施すために
、その表面状態が不安定でアルミニウムー銀量の接着強
度が弱くなシ易使用するためにチップ自体の単価が高く
なる欠点をもつものであった。However, with such conventional electrode forming means, in the case of the former aluminum-silver system, there was a problem that the adhesive strength of the aluminum-silver amount was not stable. This is because silver plating is applied on aluminum, which is easily oxidized, so the surface condition is unstable and the adhesive strength between aluminum and silver is weak.Since it is easy to use, the unit cost of the chip itself is high. Met.
この発明は従来方法のこのような欠点に鑑み、銀バンプ
を用いて機械的強度が高くかつ低価格のチップを得るた
めの電極形成方法を提供しようとするものである。In view of these shortcomings of the conventional methods, the present invention seeks to provide a method for forming electrodes using silver bumps to obtain chips with high mechanical strength and low cost.
以下、この発明に係わる電極形成方法の一実施例につき
、第2図ないし第6図を参照して詳細に説明する。Hereinafter, one embodiment of the electrode forming method according to the present invention will be described in detail with reference to FIGS. 2 to 6.
この実施例方法では、まず機能領域としてのベース領域
αりを拡散形成したシリコンウェハ←0上に、絶縁膜と
してのシリコン酸化膜03を形成し、かつこの酸化膜α
jにコンタクトホールを開口させた上で、バリアメタル
層として例えばチタン・タングステン合金層a4)、り
いで金層a四を順次に蒸着、あるいはスパッタリングに
よシ被着形成する。こ\で金層(1ツの膜厚はせいぜい
数百ないし数千人程度の極く薄いものであってよい(第
2図)。次に写真製版法を利用して金層(151上の電
極を必要としない領域にのみバター二/グしたフォトレ
ジストQ6)を被着させ(第3図)、かつこのフォトレ
ジストαQをマスクにして銀メッキを施し、必要な量の
銀バンブαDを被着形成する(第4図)。さらにその後
、フォトレジストαeを除去しく第5図)、かつ銀バン
プ卸をマスクにして不要な金層(151,およびチタン
・タングステン合金層α4を順次にエツチング除去して
、所期の電極構造を得るのである(第6図)。In this embodiment method, first, a silicon oxide film 03 as an insulating film is formed on a silicon wafer ←0 on which a base region α as a functional region has been diffused, and this oxide film α
After opening a contact hole in j, a barrier metal layer such as a titanium-tungsten alloy layer a4) and a gold layer a4 are sequentially deposited by vapor deposition or sputtering. The gold layer (the thickness of one layer may be extremely thin, at most several hundred to several thousand layers (Fig. 2)). Next, the gold layer (151) is formed using photolithography. A butter-nickeled photoresist Q6) is deposited only on areas that do not require electrodes (Fig. 3), and silver plating is applied using this photoresist αQ as a mask to cover the required amount of silver bumps αD. After that, the photoresist αe is removed (Fig. 5), and the unnecessary gold layer (151) and titanium-tungsten alloy layer α4 are sequentially etched away using the silver bump layer as a mask. In this way, the desired electrode structure is obtained (Fig. 6).
しかしてこの電極形成において、機能領域であるペース
領域a乃に直接接合されるチタン・タングステン合金層
(14)は、上層金属とシリコンとの相互拡散の防止、
および付着強度の改善を目的として存在し、数百ないし
数千人程度の厚さであればよい。また金層a句は、次の
銀メツキ実施の際の下地金属となシ、かつメタライゼー
ション工程後の保管雰囲気に対する酸化を阻止して、銀
の付着強度を弱めることのないようにするためで、その
要求に耐え得る最低の厚さであればよく、さらにバンブ
本体の銀であるが、これは金の代替えとしての信頼性を
充分に満足する実験結果より採用した。However, in forming the lever electrode, the titanium-tungsten alloy layer (14) directly bonded to the functional area, ie, the space area a, prevents interdiffusion between the upper layer metal and silicon.
It exists for the purpose of improving adhesion strength, and may have a thickness of several hundred to several thousand layers. In addition, the gold layer A is used to prevent oxidation in the storage atmosphere after the metallization process and to prevent weakening of the adhesion strength of silver. The thickness of the bump body should be the minimum thickness that can withstand the requirements, and silver for the bump body was selected based on experimental results that showed it to be reliable as a replacement for gold.
なお前記実施例は、小信号ダイオードに適用する場合に
ついて述べたが、その他のバンブを用いる半導体装置2
例えば7エイスボンデイングを用いるトランジスタとか
ICなどにも適用できることは勿論であシ、またバリア
メタルとしてチタン・タングステン合金を例にしたが、
その他の同様の特性をもつ金属2例えばタングステン、
モリブデンなどをオリ用してもよい。Note that although the above embodiment has been described for the case where it is applied to a small signal diode, the semiconductor device 2 using other bumps may also be used.
For example, it is of course applicable to transistors and ICs that use 7-eighth bonding, and titanium-tungsten alloy is used as an example as a barrier metal.
Other metals with similar properties2 such as tungsten,
Molybdenum or the like may also be used.
以上詳述したようにこの発明方法によれば、バンブ材料
に銀を用いることによ多材料の単価を抑え、しかも公知
手段によυ接着強度が強くて信頼性の高い電極構造を容
易に得られる特徴がある。As detailed above, according to the method of the present invention, the unit cost of multiple materials can be reduced by using silver as the bump material, and an electrode structure with strong υ adhesive strength and high reliability can be easily obtained by known means. There are characteristics that can be used.
第1図は従来の形成方法による電極構造を示すチップ断
面図、第2図ないし第6図はこの発明の一実施例形成方
法による電極構造を工程順に示すそれぞれ断面図でおる
。
αυ・・・・シリコン酸化膜・、αり・・・・ベース領
域(機能領域)、(131・・・・シリコン酸化膜、■
・・・・チタン・タングステン合金層(〕くリアメタル
層)、α5−−−−金層、ae・・・・フォトレジスト
、αη・・・・銀ノ(ンプ。FIG. 1 is a chip cross-sectional view showing an electrode structure formed by a conventional forming method, and FIGS. 2 through 6 are cross-sectional views showing the electrode structure formed by an embodiment of the present invention in the order of steps. αυ...Silicon oxide film, αri...Base region (functional area), (131...Silicon oxide film, ■
...Titanium-tungsten alloy layer (rear metal layer), α5---gold layer, ae...photoresist, αη...silver metal layer.
Claims (1)
ングステン、タングステン、モリブデンなどのバリアメ
タル層、ついで金層を順次に被着形成させる工程と、こ
の金層上の電極を必要としない領域にのみフォトレジス
トを被着し、このフォトレジストをマスクにして金層上
に銀バンプを被着形成させる工程と、この銀バンプをマ
スクにして金層、ついでバリアメタル層を順次にエツチ
ング除去する工程とを含むことを特徴とする半導体装置
の電極形成方法。The process involves sequentially depositing a barrier metal layer such as titanium, tungsten, tungsten, or molybdenum, and then a gold layer on the functional area in which the contact hole has been opened. A process of depositing a resist and using this photoresist as a mask to deposit and form silver bumps on the gold layer, and a process of sequentially etching away the gold layer and then the barrier metal layer using the silver bumps as a mask. A method for forming an electrode of a semiconductor device, the method comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58007028A JPS59132145A (en) | 1983-01-17 | 1983-01-17 | Forming method of electrode of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58007028A JPS59132145A (en) | 1983-01-17 | 1983-01-17 | Forming method of electrode of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59132145A true JPS59132145A (en) | 1984-07-30 |
Family
ID=11654579
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58007028A Pending JPS59132145A (en) | 1983-01-17 | 1983-01-17 | Forming method of electrode of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59132145A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01132139A (en) * | 1987-11-18 | 1989-05-24 | Casio Comput Co Ltd | Bump electrode structure of semiconductor device and manufacture thereof |
-
1983
- 1983-01-17 JP JP58007028A patent/JPS59132145A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01132139A (en) * | 1987-11-18 | 1989-05-24 | Casio Comput Co Ltd | Bump electrode structure of semiconductor device and manufacture thereof |
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