JPS59123493A - Pulse generator circuit for driving motor - Google Patents

Abstract

PURPOSE:To obtain an accurate optimum drive pulse for a motor by setting the desired control characteristics by a digital value. CONSTITUTION:An input circuit 20 sets an initial pulse period (alpha), an input circuit 21 sets the amount (beta) of variation to the period (alpha), and a setter 24 sets the total pulse number M for driving the motor. The pulse period is reduced until becoming the pulse number A after the completion of the through-up operation set by a pulse setter 22, and when exceeding the pulse number C started from the through-down operation set by a pulse setter 23, a pulse generator 25 is controlled so as to sequentially apply a pulse in a direction for gradually increasing the period.

Description

[Detailed description of the invention] (a) Technical field of the invention The present invention relates to a pulse generation circuit for driving a motor.

(b) Background of the Technology The present invention presents a means for a pulse generation circuit that improves an analog motor drive circuit to a digital one. In particular, the present invention proposes a driving method for a pulse controller that allows easy rotational speed control and prevents step-out at high speeds.

(C) Problems with conventional technology Configuration of conventional analog pulse generation circuit and 1
The speed control characteristics that are the object of the present invention are shown in Figures 1 and 2.
The problem will be explained with reference to FIG.

FIG. 1 is a block diagram of a conventional motor drive pulse generation circuit.

In the figure, 1 is a controller that does not control the motor, 2 and 3
are an analog voltage integrator and a voltage controlled oscillator (VCO) that provide the desired control characteristics; 4 is an AND gate element; and 7 are signal lines for transmitting instructions for through amplifier or through town control, respectively.

FIG. 2 shows two examples of speed characteristics of the target motor control.

The horizontal axis in the figure represents the time after motor activation, and the vertical axis represents the frequency P of the drive pulse. The period of the frequency P changes every moment as 5 hours pass, except for the constant speed period 9.

The above-mentioned through amplifier control is the period after startup until constant speed control is achieved8. The through-crank control is a period 1o from the constant speed period 9 to the end of motor control.

However, the analog motor control circuit described above has the following problems. That is, since the integrator 2 performs motor control based on the voltage generated by the capacitor accumulated charge, the two-hour followability is not good if the control command changes frequently. Furthermore, due to the charging and discharging characteristics of the capacitor, there is a problem in the linearity of speed control during through-up or through-down. Furthermore,
Since the controller counts the output pulses 5 to perform speed control (through-down control, etc.), analog circuits have problems such as the need for loop return control, which is troublesome to adjust.

(d) Object of the Invention The present invention is directed to embodying a digital pulse generation circuit in view of the above-mentioned problems.

(e) Structure of the Invention The above object is to set an initial pulse period α for one rotational speed control, a change amount β of the period α, and a total number M of pulses for driving the motor, and to In the pulse output circuit of the motor drive, set the number of pulses A at the end point of through-up control and the number C of pulses at the start point of through-down control.

The pulse period decreases to α-β, α-2β, -1-7α-nβ until the motor drive pulse period reaches 8.

When the number of motor output pulses exceeds the number of pulses of C, the -period becomes α-nβ, α-(n-1)β-nee---
This is achieved by providing a motor-driven pulse generation circuit that controls the motor speed at a predetermined speed by applying pulses that increase sequentially as 1α-β.

(f) Embodiments of the Invention The present invention will be described in detail below with reference to FIGS. 3 to 6, which show an embodiment of the digital pulse generation circuit according to the present invention.

FIG. 3 is a circuit diagram showing the main part of the generating pulse source circuit. 4 and 5 are flowcharts of circuit operation, and FIG. 6 is a complete circuit diagram of a pulse generation circuit for driving a motor.

In addition, FIG. 3 shows the 6th motor speed control characteristics
FIG. 2 is a partial circuit diagram of the embodiment circuit; FIG.

In Fig. 3, L is the adder output determined by the initial pulse period α and the amount of change in pulse period β, which are preset from the outside. This is the output of

In the circuit shown in FIG. 3, the output f of the oscillator 11 is counted by the counter I, and when the adder output I and the count match, the comparator 2 operates and outputs an output power pulse P.

FIG. 4 is a time chart of FIG. 3. However, the figure exemplifies the case where the adder output is 7 or 18.

Pulse waveforms 12, 13, 14, 15 and 16 in FIG. This is the signal pulse that resets the moon.

In FIG. 3, the output pulse (2) of the pulse source circuit is generated by the crystal oscillator 11 into a highly stable L/f wave pulse. Here, if I5 is kept constant and deviates from it, it becomes a cycle pulse with a constant period.

However, the period of the pulse P is determined by the setting of the β value and the selection circuit for its addition sign (see the circuit section of selector I in FIG. 6).
The through-a-
A knob control pulse or a through-down control pulse is obtained (see speed control characteristics in FIG. 2).

The operation time chart in FIG. 5 shows the above-mentioned pulse P following the scoot signal 26 for driving the 7 motors.

Through-up control period 8. The waveforms of control pulses that change over time are illustrated in each of the constant speed control period 9 and the subsequent through-down control period 10.

Next, with reference to FIG. 5, the operation of the circuit of the embodiment shown in FIG. 6, which controls the motor speed, will be explained.

FIG. 6 is a complete circuit diagram of a pulse generation circuit having the motor control characteristics shown in FIG. 2.

The control input circuit section of the 2 preset settings in the figure is as follows.

That is, 20 is the input circuit for the initial pulse period α, 2]
22 is a circuit for setting the number of pulses A at the end of through-up, 23 is a circuit for setting the number C of pulses at the start of through-down, and 24 includes the number of pulses and the number C of pulses. Total cumulative pulse number M of motor control
This is the setting circuit.

The α input circuit 20 and the β input circuit 21 are connected to the illustrated adder via the selector I and the selector ■, respectively, and the output (L) of the adder is connected to the basic Norse generation source circuit 25 in FIG. be done.

The total number of pulses M setting circuit 24, all patterns of number 2 motor control, input circuits that determine control patterns such as those shown in (a) or (b) of Fig. 2, and pulse number C setting for ending control of the serial knob. The circuit 22 is the cumulative pulse input circuit from motor start to constant speed drive, and the slew turn control start pulse number C setting circuit 23 is the cumulative pulse input circuit from the end point of constant speed control to motor stop. It is. However, C is precisely the number of remaining pulses obtained by subtracting the cumulative normality up to the end point of constant speed control from the total number of pulses M.

The operation of the circuit of FIG. 6 is as follows: First, the start pulse 26 (see FIG. 5) causes the ll-F circuit 27 to be activated (71-), and its output signal causes the selector (2) to select the α side input.

At the same time, α is input to the adder from the side input (corresponding to the morph start pulse). Selector I first selects −β and ζ
Therefore, the input on the α side of the adder becomes one β, and the output of the adder becomes α−β.

On the other hand, the counter III of which M is preset is reset by the second pulse 26, so that the counter I11
A signal of all DOs and NODOs is input to the signal line of the output Q of the gate element G1 (see the Q signal in FIG. 5).

In the element G1, the gate is opened by the signal Q, and the pulse P explained in FIG. 3 becomes a morph drive pulse (CP). Furthermore, the counter II is also reset by the start pulse 26.

The drive pulse CP is also input to the counter 2 (up counter of the pulseless accumulative bond) and the counter 2 (down counter), and serves as a rasochi pulse that is input to the launch circuit via the gate element G2.

The CP pulse passes through the delay circuit 28, resets the FF circuit 27, and selector n selects L'. That is, from the second pulse, the period is not the preset α but L.
', and from then on, every CP pulse output is α-β, α-2β,
α-3β and its period decrease. This continues until the cumulative number of pulses B on the counter 2 matches the number of pulses at the end of through-up.

The calibrator (2) compares A and B as described above, and when the logic output of A>B becomes O, the gate element-G3. G2 game 1-
After closing, the CP pulse period becomes constant.

Furthermore, if the number of output pulses of the down counter 11 is equal to the number of continuous output pulses of a certain period or the number of remaining pulses to start through-down control is C or less than C (C>D), the comparator ■
The logic output of becomes 1, which opens the gate element G2 of the latch circuit again, and at the same time, the selector (2) is switched to the β side.

From now on, the period of the morph drive output pulse CP is α−nβ,
When the counter ■ increases as α-(n-1)β and α-(n-2)β and reaches 0, a signal with a count value of zero is sent to the gate element G1 via the output line Q. Then close the box.

Thus, a single cycle operation of motor control is completed.

11. The single cycle operation of the motor control described above is shown in Figure 2 (
b) This explains the characteristics of the total number of pulses M set above.
is the case when M>A+C. Also, the triangular characteristic without the constant speed control part in the same figure (b) is as follows.

This is the case when M<A+C.

(g) Nine Results of the Invention According to the motor drive pulse generation circuit of the present invention, which has been explained in detail in the circuit of the embodiment, the three elements of the target control characteristics are digital values, compared to conventional analog circuits. There is an advantage that highly accurate drive pulses that are set and are optimal for the motor are supplied. Furthermore, the load on the controller is reduced and reliability is high. From this point of view, the present invention has great practical value.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of a conventional analog pulse generation system, FIG. 2 is a target motor speed control characteristic diagram, and FIG. 3 is a circuit diagram showing the main parts of a pulse generation source circuit as an example.
4 and 5 are both time charts of circuit operation, and FIG. 6 is an overall circuit diagram of the pulse generating circuit of the present invention. In the figure, 1 is a controller, 8 is a through amplifier period for speed control, 9 is a fixed visibility control period, 10 is a through down period,
20 is the α input surface 1i'i'), 21 is the β input circuit 522
23 is a pulse number setting circuit for ending through-amplification, and 23 is a pulse number setting circuit for starting through-down. 24 is a total pulse number (M) setting circuit, and 25 is a pulse source circuit.

Claims (2)

[Claims] (1) Set the initial pulse period α for rotational speed control, the variation β of the period α, and the total number of pulses M for driving the motor, and set the pulse at the end point of the through-up control within the pulse number M. Without setting the number A and the number of pulses C at the start point of through-down control, in the motor drive pulse output circuit, the pulse period is α-β, α-2βl until the motor drive pulse period reaches A. ----'l decreases as α-nβ, and when the number of motor output pulses exceeds the number of pulses in C, 9 cycles are α-nβ, α-(n-1)β----
--'l A pulse generating circuit for driving a motor, which controls a predetermined motor speed by applying pulses that increase sequentially from α to β. (2) a pulse counter I that counts the output f of the oscillator;
When the parallel output of the oscillator output r matches the adder output determined by the initial pulse period α and the pulse period change amount β, the pulse generating circuit is constructed by a comparator and a delay circuit that reset the counter ■. .