JPS59117713A - Transmitting device of digital audio signal - Google Patents

Abstract

PURPOSE:To reproduce an audio signal by reconstituting a vertual data series with an address at each block from an intermittent reproducing data of a digital audio signal even at the vari-speed reproduction of a rotary head digital VTR. CONSTITUTION:A synchronizing signal and an address signal are added to a data of a prescribed length, and 1,024 blocks are specified by using the address signal in, e.g., 10 bits, and even if one data block is reproduced without relation to other blockes therebefore and thereafter, the data block is restored correctly to a position to which the block is to be located virtually in the data series having a spread of 1,024 blocks. Since the synchronizing signal for the block synchronism is to identify the address and data in the reproduced data series, it is enough to add one synchronizing signal even to plural blocks as shown in Fig. B. As a result, the audio signal is reproduced even at the vari-speed reproduction of the rotary head digital VTR.

Description

Detailed Description of the Invention "Field of Industrial Application" This invention relates to a digital VTR which records digital video signals and digital audio signals onto a magnetic tape using a rotating head, and which reproduces these digital signals from the magnetic tape. The present invention relates to a digital audio signal transmission device applied to.

"Background Art and its Problems" There are roughly two methods for recording digital audio signals in a digital VTR. One type uses a fixed head to record digital audio signals on tracks that extend in the longitudinal direction of the magnetic tape, and the other uses a rotating head to record digital audio signals on tracks that extend in the width direction of the magnetic tape. It is something to do. Compared to the former recording method using a fixed head, the latter recording method using a rotating head is advantageous in that the relative speed between the magnetic head and the magnetic tape is greater and it is easier to process large amounts of data.

When recording digital audio signals using a rotating head, there are two methods: multiplexing the video data and audio data without clearly distinguishing them, and performing common error correction encoding and channel encoding; There is a method in which both are encoded and recorded on a magnetic tape while distinguishing between the two.

The former recording method, which mixes video data and audio data and processes them all at once, mixes audio information, which has a relatively small amount of data, into a large amount of video data, so it is less prone to errors that occur during recording and playback. It is possible to provide stronger protection with a higher degree of freedom. However, it requires time and effort to extract only the audio data from the reproduced data, and the latter method, in which the two are clearly distinguished and recorded, also requires complex data processing.

Therefore, there is a problem in that it is difficult to edit video data and audio data separately, or to edit audio data itself by channel.

Therefore, it is convenient to record data on a magnetic tape using a rotating head, clearly distinguishing it from video data. Specific methods include recording audio data all at the beginning, middle, or P end of a video track inclined in the width direction of the magnetic tape, and recording audio data on a track separate from the video data. A method is used.

However, the method of recording audio data separately from video data in a concentrated manner also has problems. The two problems are that it is easily affected by errors due to dropouts that occur during playback, and that it is difficult to reproduce audio data during variable speed playback where the running speed of the magnetic tape is different from that during recording. If a dropout occurs in an area where audio data is concentrated, a large amount of data will be lost, and if an error occurs that exceeds the ability of error correction encoding, it will be difficult to compensate for the error data! Becomes IG.

Furthermore, during variable speed reproduction, the scanning locus of the rotary head does not match the tracks, and generally a plurality of tracks are scanned diagonally and fragmented data is reproduced from each track. In the sequence of reproduced data obtained in this way, the order of the original data is reversed, and the time differences between the obtained fragmentary data are uneven, so it is impossible to reproduce the data with high intelligibility if it is left as it is. Can't get sound. One way to improve this is to make the rotary head movable in the height direction (for example, by attaching the rotary head to one end of the piezoelectric element).

Tracking may be considered, but the problem is that the applicable tape speed range is limited to the vicinity of that during normal playback.

"Purpose of the Invention" This invention aims to
The object of the present invention is to provide a digital audio signal transmission device capable of reproducing audio data even when data is obtained only in fragments.

゛However, this invention is a digital VT in which audio data is clearly distinguished from video data and recorded on magnetic tape.
The present invention aims to provide a digital audio signal transmission device suitable for use in R.

``Summary of the Invention'' The present invention is a digital audio signal transmission device that divides a digital audio signal series into blocks and adds an address signal for specifying the data of each block. A block-format digital audio signal is written to an address corresponding to the signal, and the digital audio signal is read from this memory in a predetermined order, and information is formed to identify whether the data read from this memory is new or old. Instead, the new data read from this memory is used to synthesize the missing data and reproduce the original digital audio signal.

In addition, the present invention converts a digital audio signal sequence into an order different from the original order, performs error-correctable encoding, restores the original order on the receiving side, and then performs error correction decoding. It is something to do. The address when writing reproduced data to the memory that performs this order conversion is determined by an address signal added to each block.

Further, the present invention is applicable to a rotary head type digital VTR in which digital audio signals are recorded in an area of a recording medium that is clearly distinguished from video signals.

Embodiment An embodiment in which the present invention is applied to recording and reproducing audio data of a digital VTR will be described below.

FIG. 1 shows the configuration of a recording-side circuit according to an embodiment of the present invention, and FIG. 2 shows the configuration of its reproducing-side circuit. In FIG. 1, a digital audio signal is supplied to an error correction encoding circuit indicated by 1. One sample of this digital audio signal is 16 bits.

In the case of error correction encoding, one sample is divided into eight pits each, and processing is performed using eight bits as one word. In the error correction encoding circuit 1, encoding is performed to correct and modify errors in the transmission path, and parity data for error correction is added to original audio data.

The output of the error correction encoding circuit 1 is supplied to a shuffling circuit 2, where the front and back relationships are switched and converted into a different arrangement of data from the original time series arrangement. Through the processing of this shuffling circuit 2, burst errors that are expected to occur in the transmission path are fragmented when viewed from the original time series after deshuffling,
It becomes possible to easily correct data using an error correction code, and data containing an error in the original time series can be effectively corrected by correct data before and after it. In some cases, the method of performing shuffling processing more regularly is called interleaving.

The shuffled data sequence emerging from this shuffling circuit 2 is supplied to one input terminal of a multiplexer 3. The other input terminal of the multiplexer 3 is supplied with a synchronization signal and address data from a synchronization and address data generation circuit 4. This multiplexer 3
At the output, data in units of one block appears, to which an address signal indicating the order of the blocks and a synchronization signal for achieving block synchronization on the playback side are added for each appropriate amount of data. Although not shown, this data undergoes channel encoding processing according to the characteristics of the transmission path, is supplied to a rotary head via a recording amplifier and a rotary transformer, and is recorded on a magnetic tape. A clock and control signal generation circuit 5 is provided for recording side processing of ζ.

The signals reproduced from the magnetic tape by the rotating head are transmitted to a rotating transformer and a reproduction amplifier (not shown).

The signal is supplied via a channel decoding circuit to a synchronization and address detection circuit 6 and a deshuffling circuit 7, as shown in FIG. The synchronization signal detected by the synchronization and address detection circuit 6 is supplied to a clock and control signal generation circuit 8, and the address signal is supplied to a deshuffling circuit 7. A clock and control signal synchronized with the reproduction data generated by the clock and control signal generation circuit 8 are used for data processing in the reproduction side circuit.

The deshuffling circuit 7 returns the time series of reproduced data to the original time series. This deshuffling circuit 7 generates old and new flags.

The old and new flags distinguish whether the output data of the deshuffling circuit 7 is newly reproduced data or previous data that has been saved because the memory is not rewritten. The output data of the deshuffling circuit 7 and the old and new flags are supplied to the error correction circuit 9, and error data is corrected. In this case, the old data is
When correcting errors, check individual errors such as error date and evening [7]
be treated as such. The error correction circuit 9 outputs corrected data and an error flag, and supplies them to the error detection circuit 10 at the next stage. The error flag indicates the presence or absence of an error. In this error detection circuit 10, the presence or absence of an error is finally detected, including correction of an erroneous error.

The error correction circuit 11 is supplied with the output data of the error detection circuit 10 and the error flag, and the error correction circuit 11 performs correction by replacing the error data indicated by the error flag with an estimated value based on correct data in its vicinity. A reproduced digital audio signal is obtained at the output of this error correction circuit 11.

Note that Figures 1 and 2 show a one-channel configuration in which one data output is transmitted for one data input, but by preparing multiple channels and operating them in parallel, it is possible to create a multi-channel transmission path. It is also possible to configure . Further, by using appropriate parallelization or multiplexing means, one channel may be outputted as data of a plurality of channels, and each channel may be recorded as a parallel track.

In this invention, chain encoding is performed using an inner code and an outer code as error-correctable codes.

As shown in FIG. 3A, a CRC (C
yclic Redundancy Check)
':1-code is added to form a CRC block. As shown in FIG. 3B, n CRC blocks are collected, the outer code is encoded, and its parity (b word) is added to form an outer code block.

As shown in the third diagram, these outer code blocks are arranged in one column of a matrix.

Therefore, as shown in FIG. ) is added. The inner code and outer code are shielded codes.

A Reed-Solomon code or the like is used.

FIG. 4 shows 29-dimensional error correction encoding in one embodiment of the present invention. As shown in Figure 4A, a CRC block is obtained by adding a 2-word (16-bit) CRC code to 10 words of audio data, and as shown in Figure 4B, the CRC block total is Two words of adjacent code parity are added to the 12 words to form an outer code block. For example, a synchronization signal and an address signal are added to this outer code block to form one block of data. These outer code blocks are arranged in four columns as shown in the fourth diagram. Then, as shown in FIG. 4C, two words of parity of adjacent codes are added to the four words included in one row to form an inner code block. One sample of audio data consists of two words, and the numbers written in the fourth diagram indicate the order of the 20 samples of audio data in time series.

The error correction encoding circuit 1 provided in the recording side circuit shown in FIG. 1 performs the above-mentioned encoding and has the configuration shown in FIG. 5. Data input is multiplexer 12
and is supplied to the CRC code encoding circuit 13. A 2-byte CRC code is calculated on 5 samples (10 words) of audio data, and a CRC block (FIG. 4A) is generated at the output of the multiplexer 12.

The output of this multiplexer 12 is supplied to a multiduplexer 14 and an outer code correction circuit 15.

In this outer code correction circuit 15, a two-word parity of the outer code (for example, adjacent codes) is formed, and an outer code block (FIG. 4B) appears at the output of the multiplexer 14.

Furthermore, the output of the multiplexer 14 is sent to the multiplexer 16.
and is supplied to the inner code encoding circuit 17.

In this inner code encoding circuit 17, a two-word parity of the inner code (for example, adjacent codes) is formed, and an inner code block (FIG. 4C) appears at the output of the multiplexer 16.

Error correction circuit 9 provided in the reproduction side circuit shown in FIG.
The error detection circuit 10 has a configuration shown in FIG. The reproduced data supplied from the deshuffling circuits 7 to 41 is supplied to the inner code correction circuit 18, where error correction is performed using the inner code.

In the case of adjacent codes using two parities, two error syndromes are calculated, and depending on the error syndrome, it is determined whether the error is a one-word error or an error of 27-words or more. is determined, and in the case of a one-word error, the error word is corrected. Further, information indicating the presence of error obtained from the error syndrome is sent to the subsequent stage as an error flag using an inner code.

The output data of the inner code correction circuit 18 is supplied to the outer code correction circuit 19 and is corrected by the outer code. This outer code correction circuit 19 performs error correction decoding using adjacent codes, outputs the corrected audio data, and also supplies it to the CRC error detection circuit 20 . and C
An error flag indicating the result of error detection by the RC error detection circuit 20 and an error flag from the inner code correction circuit 18 are supplied to an error flag control circuit 21. CRC
Since error detection is performed on a block-by-block basis, even if the CRC error detection circuit 20 detects an error, some words may be determined to have no error during inner code correction. In order to rescue this correct data, the error-7 lag control circuit 21 compares the error flags from the CRC error detection circuit 20 and the inner code correction circuit 18, and determines that there is a high possibility of an error word. Error flags are raised only for things.

The error correction code in the embodiment of this invention has two stages of error correction means and one error detection means, but on the playback side, error correction and error detection using all of these means are always performed. There is no need to perform detection.

For example, by only detecting errors using CRC codes,
If error data is resynthesized through error correction, the circuit size on the playback side can be reduced1.
However, when the reproducing side is configured in this way, transmission may be performed such that part of the parity of the chain code is always missing.

FIG. 7 is a conceptual diagram of the shuffling circuit 2 and the deshuffling circuit T. In FIG. 7, 22d indicates a memory, and this memory 226-i has two frame memories. During a period when data is being written to one frame memory of the memory 22, data is not being read from the other frame memory. This memory 2
The operation of step 2 is controlled by the memory controller 23, and a write address and a read address are generated by the address generation circuit 24. The memory controller 23 and address generation circuit 24 are supplied with clocks and control signals.

In the case of the shuffling circuit 2, input audio data is regularly written into one frame memory of the memory 22, and audio data is read out from the other frame memory in an irregular order. Deshuffling circuit 7
In this case, the reproduced audio data is written to the address of one frame memory of the memory 22 that corresponds to the address signal added to the reproduced audio data, and the audio data is written from the other frame memory in a regular IK order. is read out. Therefore, as shown by the broken line in FIG. 7, the address signal detected from the reproduced data is supplied to the address generation circuit 24. Shuffling and deshuffling processing can be performed by such at/s control. Both processes may be performed in field units instead of frame units. Furthermore, in the case of the deshuffling circuit T, old and new flags are also generated from the memory 22, as shown by broken lines.

FIG. 8 shows an example of the structure of block data. FIG. 8A shows the structure of block data in an embodiment of the present invention, in which a synchronization signal and an address signal are added to data of a predetermined length (audio data or parity data for error correction). It is. If this address signal is, for example, 10 bits, it is possible to specify (210 = 1'024) blocks, and even if one data block with no prior or subsequent context is reproduced, This data block is 1024
It is possible to correctly return a block to its original position in a data series with a spread of blocks.

The synchronization signal for block synchronization is for identifying addresses and data in the reproduced data series, so as shown in FIG.
You may also add one.

Further, as described above, the deshuffling circuit T is connected to the memory 2.
2, by writing the reproduced data to the address corresponding to the address signal of the block, even in the variable speed reproduction state, the data block reproduced in fragments can be stored in the memory 22 regardless of the context at the time of reproduction. It becomes possible to rearrange it in the correct context. By synthesizing other data from the correct data in the partial playback data obtained in this way by the error correction circuit 11, the magnetic tape running speed button can be adjusted (although there is some deterioration in the FF information, it is highly intelligible). It is possible to obtain playback sound.

Furthermore, since data is read out from the deshuffling circuit 7 in a fixed address order, if the data is read out from the deshuffling circuit 7 in a fixed address order, the data that has just been reproduced by the rotary head and the data that has not been reproduced by the rotary head will be read out from the memory 22.
cannot be distinguished from data previously written. Therefore, there is a possibility that data that has been erased and reproduced will be repeatedly output. Therefore, each time data is read from the memory 22, the flag corresponding to that address is set to the old state (meaning it has been read once), and when a new data is written to that address, The flag is turned off. New and old data can be identified using the new and old flags.

There is a method that does not use the old and new flags, and a method that writes an error 4 report to the address each time data is read from the memory 22. By doing K in this way, all old data will be determined to have an error when an error is detected.
It is possible to prevent data from being treated as correct when data is corrected.

FIG. 9 shows a specific example of the error correction circuit 11 provided on the reproduction side. ”=The error flag formed as described above is sent to the selection logic circuit 2 via delay circuits 25 and 26.
supplied to T. Delay circuits 25 and 26 provide a delay of one sample clock period. Further, the error flag seen at the output of the delay circuit 25 and the input error flag are also supplied to the selection logic circuit 27. Therefore, the selection logic circuit 27 has three temporally consecutive error flags E1. E2 and E3 are supplied, and a control signal for the selection circuit 28 is generated depending on the state of the error flag.

Furthermore, one sample (16 bits) of parallel audio data is supplied to the selection circuit 28 via latches 29 and 30. The audio data appearing at the output of latch 29 and the input audio data are supplied to selection circuit 28 .

The input audio data and the audio data appearing at the output of latch 30 are provided to interpolation circuit 31 . This interpolation circuit 31 is, for example, an average value interpolation circuit. Selection circuit 2
At the output of 8, modified audio data is obtained and this audio data is returned to the selection circuit 28 via the latch 32. Furthermore, a constant value corresponding to an intermediate value of the audio data is supplied to the selection circuit 28.

Latches 29 and 30.32 provide a one sample clock delay to the data.

The selection circuit 28 outputs error-corrected data for the summable data appearing at the output of the latch 29, and selects three successive error flags El, E2 .
A selection logic circuit 28 forms a selection signal based on E3. When this error flag is 1, it indicates that there is no error, and when it is 0, it indicates that there is an error. In response to the selection signal from the selection logic circuit 27, the selection circuit 28 selects the output of the latch 32 with a pre-output hold, which selects a constant value with a constant value, and which selects the output of the latch 30 with a pre-value hold. , a diameter value hold to select the input audio data, a linear interpolation to select the output of the interpolation circuit 31, and an unmodified operation to select the output of the latch 29. Error flag E, , E2. The relationship between E3 and the correction operation to be executed is shown below.

1 on E, E2 knee 0. E3=0: Previous price hold E
,=0, E2=0, E3=l:
Diameter value hold E,=i, E2=0,
E3=1 ・Linear interpolation E, -1, E2-1, E
3=1: Unmodified ``Effect of the invention'' According to this invention, it is possible to reconstruct the original data sequence from fragmentary reproduced data of a digital audio signal using addresses for each block. It is possible to reproduce audio signals even during variable speed reproduction of a digital VTR. Further, in the present invention, since the memory used for reconstructing reproduced data is also used for deshuffling, it is possible to simplify /h-ware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a recording system in an embodiment in which the present invention is applied to a digital VTR, FIG. 2 is a block diagram showing the configuration of a reproduction system in an embodiment of the present invention, and FIGS. FIG. 4 is a route map used to explain the error correction code in one embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of an error correction encoding circuit in an embodiment of the invention, FIG. 6 is a block diagram showing the configuration of an error correction decoding circuit in an embodiment of the invention, and FIG. A block diagram used to explain a shuffling circuit and a deshuffling circuit in an embodiment of this invention, FIG. 8 is a schematic bond diagram used to explain a data structure in an embodiment of this invention, and FIG. 9 is an embodiment of this invention. FIG. 2 is a block diagram showing the configuration of an error correction circuit in an example. 1...Error correction encoding circuit, 2...
・・・・・・・・・Shuffling circuit, 7・・・・・・
...Deshuffling circuit. 9...Error correction circuit, 10...
......Error detection circuit, 11...
...Error correction circuit, 22.....Memory, 28.....Selection circuit. Writ of intellectual procedural amendment (method) by Masaharu Sugiura May 31, 1980 1 Director of the Patent Office Kazuo Wakasugi Indication of 15 cases 1982 Patent Application No. 230949 3, Comparison with the case of the person making the amendment Corrected as “Related Patent Applicant Dio Signal Transmission Device”〇

Claims (3)

[Claims] (1) A digital audio signal transmission device that divides a digital audio signal series into blocks and transmits each block of data by adding an address signal that specifies the data, which corresponds to the address signal in the memory on the receiving side. The block digital audio signals are written to the respective addresses, and the digital audio signals are read from this memory in a predetermined order, and information is formed to identify whether the data read from this memory is old or new. This digital audio signal transmission device uses new data read out from this memory to synthesize missing data and reproduce the original digital audio signal. (2) Perform error-correctable outer coding on the digital audio signal sequence, write the digital audio signal and the redundant code of the error correction code into a memory, and use the memory to convert the data sequence into a data sequence in a different order from the original order. This is a digital audio signal transmission device that divides this data series into blocks, adds an address signal to specify the data of each block, and transmits the data. writing the blocked digital audio signals and redundant data into the memory, reading the digital audio signals from the memory in a predetermined order, and forming information for identifying old and new data read from the memory. None, get the data sequence restored to the original order from this memory, perform error correction decoding using the new data of this data sequence, and correct the missing data using the correct new data of the decoded audio data sequence. A digital audio signal transmission device that synthesizes the data and reproduces the original digital audio signal. (3) A digital audio signal is recorded on a recording medium by a rotating head together with a video signal, and the digital audio signal is recorded in an area of the recording medium that is clearly distinguished from the video signal. A digital audio signal transmission device according to scope 1 or 2.