JPS59111493A - Load control system - Google Patents

Load control system

Info

Publication number
JPS59111493A
JPS59111493A JP57221233A JP22123382A JPS59111493A JP S59111493 A JPS59111493 A JP S59111493A JP 57221233 A JP57221233 A JP 57221233A JP 22123382 A JP22123382 A JP 22123382A JP S59111493 A JPS59111493 A JP S59111493A
Authority
JP
Japan
Prior art keywords
signal
period
load
frequency
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57221233A
Other languages
Japanese (ja)
Inventor
Takashi Abe
隆 阿部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57221233A priority Critical patent/JPS59111493A/en
Publication of JPS59111493A publication Critical patent/JPS59111493A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/22Arrangements for supervision, monitoring or testing
    • H04M3/36Statistical metering, e.g. recording occasions when traffic exceeds capacity of trunks
    • H04M3/365Load metering of control unit

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To avoid overload even if the number of processing requests is increased by varying the interrupting period in response to the magnitude of load of a central controller in a central controller of a telephone exchange. CONSTITUTION:The state of call processing load of the central controller CC1 is detected by a detecting section 2, the periodic signal from a basic period signal generating section 4 is varied in response to the output signal and an output is generated from the period control section 5 to a period interrupting request section 3. When the load state of the device CC1 is less than 40%, a utilizing efficiency signal (a) of the device 1 is detected by the detecting section 2 and when the signal is given to a frequency dividing circuit 50 via a selecting circuit 51, the frequency division circuit 50 performs the control command so that the selecting circuit 51 selects a frequency dividing signal T1, a period interrupting request section 3 performs the interrupting request in the period of the signal T1 to the device CC1 and frequency dividing signals T2, T3 are selected depending on the utilizing efficiency of the device CC1.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は負荷制御方式に関し、特に自動交換機における
中央制御装置の負荷制御方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a load control system, and more particularly to a load control system for a central controller in an automatic switching system.

〔従来技術と問題点〕[Prior art and problems]

一般に、自動交換機において中央制御装置がランダムに
発生する加入者がらの呼を実時間処理する場合、加入者
回路などからの要求は要求発生時点ですぐ処理に移るこ
とはしないで、−短周期(例えば16m5)ごとに該要
求の有無を検出すること(いわゆるルックイン方式)に
よりソフトウェアとの共同で処理を実行している。従っ
て前記要求数が増加するほど前記中央制御装置この負荷
が増大し、過負荷状態になると呼処理の実時間性が損な
われる。
Generally, when the central control unit in an automatic exchange processes calls from subscribers that occur randomly in real time, requests from subscriber circuits, etc. are not immediately processed at the time of request generation, but are processed in short cycles ( For example, by detecting the presence or absence of the request every 16 m5 (so-called look-in method), processing is executed in collaboration with software. Therefore, as the number of requests increases, the load on the central controller increases, and if an overload condition occurs, the real-time performance of call processing is impaired.

従来はこの過負荷状態を回避するVC足る大きい呼処理
能力の中央制御装置をあらかじめ設置して対処している
ので、自動V換機の初期設備費が増加するという欠点が
あった。
Conventionally, this overload condition has been dealt with by installing in advance a central control unit with sufficient call processing capacity to avoid this overload condition, which has had the disadvantage of increasing the initial equipment cost of the automatic V switching machine.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、中央制御装置の負荷の大きさに応じて
割込み周期を可変にすることr(より上記欠点を除去し
、該中央制御装置の過負荷状態を招かないようにする負
荷制御方式全提供することにある。
An object of the present invention is to provide a load control method that eliminates the above-mentioned drawbacks and prevents an overload state of the central controller by making the interrupt period variable according to the magnitude of the load on the central controller. It's all about providing.

〔発明の概要〕[Summary of the invention]

本発明による負荷制御方式は、自動交換機において、中
央制御装置の負荷状況を検出する検出手段と、該中央制
御装置に周期割込みを要求する割込み要求手段と、基本
周期信号を発生する発生手段と、該周期4に号を前記検
出手段の出力信号により可変にする周期制御手段とを備
えること全特徴とする。また、周期制御手段は発生手段
からの基本周期信号を分周する分周回路と、検出手段の
出力信号に応じて所定の分周信号を選択出力する選択回
路を含み構成されることを特徴とする。
The load control method according to the present invention includes, in an automatic exchange, a detection means for detecting the load condition of a central control unit, an interrupt requesting means for requesting a periodic interrupt from the central control unit, and a generation means for generating a basic periodic signal. The present invention is characterized in that it further comprises period control means for making the number of the period 4 variable by the output signal of the detection means. Further, the period control means is characterized in that it includes a frequency dividing circuit that divides the frequency of the basic period signal from the generating means, and a selection circuit that selects and outputs a predetermined frequency divided signal according to the output signal of the detecting means. do.

〔発明の実施例〕[Embodiments of the invention]

次に図面?参照して本発明について説明する。 Drawings next? The present invention will be explained with reference to the following.

第1図は本発明の負荷制御方式の一実施例全示すブロッ
ク図、第2図は第1図における周期制御部の一構成例を
示す回路ブロック図である。第1図において、自動変換
様は中央制御装置(以下CC)1と、該CC1の呼処理
負荷状況(使用効率)を検出する負荷検出部(以下DE
T)2と、前記CC1に周期割込み全要求する周期割込
み要求部(以下REQ)3と、基本周期信号を発生する
基本周期発生部(以下GEN)4と、前記DET2の出
力信号に応じて前記GEN4からの前記基本周期信号を
可変にして前MiEQ3に出力する周期制御部(以下C
NT)5を含み構成される。
FIG. 1 is a block diagram showing an entire embodiment of the load control method of the present invention, and FIG. 2 is a circuit block diagram showing an example of the configuration of the periodic control section in FIG. 1. In FIG. 1, automatic conversion includes a central control unit (hereinafter referred to as CC) 1 and a load detection unit (hereinafter referred to as DE) that detects the call processing load status (usage efficiency) of the CC1.
T) 2, a periodic interrupt request unit (hereinafter referred to as REQ) 3 that makes all periodic interrupt requests to the CC1, a basic period generation unit (hereinafter referred to as GEN) 4 that generates a basic period signal, and A period control unit (hereinafter referred to as C
NT) 5.

次に第2図において、CNT5はGEN4からの基本周
期信号To’(例えば16m5周期信周期音分周して分
周信号T1.T2 、T3  (例えばそれぜれ32m
5,48m5,54m5  周期信号)を出力する分周
回路(以下Did)50と、DET2からのCCCC用
効率信号、b、c(例えばそれぞれ40チ。
Next, in FIG. 2, CNT5 divides the fundamental periodic signal To' (for example, 16m5 periodic tone) from GEN4 into frequency-divided signals T1, T2, and T3 (for example, each of 32m5).
A frequency divider circuit (hereinafter referred to as Did) 50 that outputs 5, 48m5, 54m5 periodic signals), CCCC efficiency signals b and c (for example, 40ch each) from DET2.

60%、80%負荷信号)に応じて前記DIV50から
の前記分周信号T1.T2 、T3 k選択して1RE
Q3に出力する選択回路(以下5EL)51 ’e含み
構成される。なお該5EL51は前記DIV50の指示
により前記CC使用効率信号a、b、cとそれぞれ対応
させて前記分周信号T!、T2.T3の選択を行う。
60%, 80% load signal) from the DIV50. Select T2, T3 k and 1RE
It is configured to include a selection circuit (hereinafter referred to as 5EL) 51'e that outputs to Q3. Note that the 5EL51 outputs the frequency divided signal T! in correspondence with the CC usage efficiency signals a, b, and c, respectively, according to the instruction from the DIV50. , T2. Select T3.

次に第3図は第2図における分周回路の入出力信号の一
例を示すタイムチャートである。同図において、15m
5周期の基本周期信号T。FiDIV50(第2図に図
示)で分周され、それぞれ32m5゜48m5,54m
5周期の分周信号T1 y T2 e T3 (!:な
る。
Next, FIG. 3 is a time chart showing an example of input/output signals of the frequency dividing circuit in FIG. 2. In the same figure, 15m
Basic periodic signal T with 5 periods. Divided by FiDIV50 (shown in Figure 2), 32m5, 48m5, 54m, respectively.
A divided signal of 5 periods T1 y T2 e T3 (!: becomes.

続いて本実施例の動作について説明する。CCIの負荷
状況が40%未満のときは、DET2がCC使用効率信
号affi検出してこれ=iSEL51に介してDiV
50VC伝えルト、該L)IV50は%1SEL51が
分周信号T1を選択するように制御指示を行うので、該
分周信号T□は該5EL51からREQ3に送信される
。従って該R,EQ3は前記CCIに32m5周期で割
込み要求を行う。また前記CCIの負荷が増加して40
%以上60%未満、60%以上80%未満では前記DE
T2はそれぞれCCCC用効率信号s  C全検出し、
同様に前記DIV50からの分周信号T2.T3に基づ
いてMu記几EQ3から該CCIへの割込み要求はそれ
ぞれ48m5,54m5周期で行われる。
Next, the operation of this embodiment will be explained. When the CCI load status is less than 40%, DET2 detects the CC usage efficiency signal affi and sends it to DiV via iSEL51.
Since the 50VC transmission current L)IV50 gives a control instruction so that the %1SEL51 selects the frequency-divided signal T1, the frequency-divided signal T□ is transmitted from the 5EL51 to REQ3. Therefore, R and EQ3 issue an interrupt request to the CCI every 32m5 cycles. In addition, the load on the CCI increased to 40%.
% or more and less than 60%, and 60% or more and less than 80%, the above DE
T2 respectively detects the CCCC efficiency signal sC,
Similarly, the frequency-divided signal T2. Based on T3, an interrupt request from Mu recorder EQ3 to the CCI is made in cycles of 48m5 and 54m5, respectively.

なお本実施例におけるDET2.REQ3およびGBN
4はいずれも一般に知られているものであり、また1)
IV501’i一般的分周回路VC8EL51 ヘ17
)簡単す制御指示機能を付加したものである。更に選択
回路はハードウェアを例示したが、この選択機能は一般
にマイクロプログラムによって実行される。
Note that DET2. in this example. REQ3 and GBN
4 are all generally known, and 1)
IV501'i General frequency divider circuit VC8EL51 He17
) A simple control instruction function has been added. Further, although the selection circuit is illustrated as hardware, the selection function is generally performed by a microprogram.

本実施例は不発−全制限するものではない。すなわち、
中央制御装置の負荷状況として40%。
This embodiment does not limit all failures. That is,
The load status of the central control unit is 40%.

60%、80%未満の3段階を例示したが、このパーセ
ンテージおよび段階数は任意に定めてよい。
Although three stages of less than 60% and 80% are illustrated, the percentage and the number of stages may be determined arbitrarily.

また、基本周期信号は16m5周期に限るものではなく
、分周の整数比も任意に定めてよいことはいうまでもな
い。
Furthermore, it goes without saying that the basic period signal is not limited to a period of 16 m5, and the integer ratio of frequency division may be arbitrarily determined.

〔発明の効果〕〔Effect of the invention〕

以上の説明により明らかなように本発明の負荷制御方式
によれば、中央制御装置の負荷が大きくなるにつれ割込
み要求周期を広げることにより該中央制御装置が過負荷
になるの全回避するので、呼処理能力の大きい中央制御
装置を初期設置する必要がなく極めて経済的に呼の実時
間処理が可能たなるという顕著な効果が生じる。
As is clear from the above explanation, according to the load control method of the present invention, as the load on the central control unit increases, the interrupt request cycle is widened to completely avoid overloading the central control unit. The remarkable effect is that it is possible to process calls in real time very economically without the need for the initial installation of a central control unit with a large processing capacity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の負荷制御方式の一実施例を示すブロッ
ク図、第2図は第1図における周期制御部の一構成例を
示す回路ブロック図および第3図は第2図における分周
回路の入出力信号の一例を示すタイムチャートである。 図において、 1°°′°゛・中央制御装置CC,2・・・・・負荷検
出部DET。 3・・・・・・周期割込み要求部R,EQ、 4・・・
・・・基本周期発生部GEN、 5・・・・・・周期制
御部CNT、50・・・・・・分周回路DIV、51・
・・・・・選択回路SEL、。 7−′−\・、
FIG. 1 is a block diagram showing an embodiment of the load control method of the present invention, FIG. 2 is a circuit block diagram showing an example of the structure of the periodic control section in FIG. 1, and FIG. 3 is a frequency division diagram in FIG. 2. 5 is a time chart showing an example of input/output signals of the circuit. In the figure, 1°°'°゛・Central control unit CC, 2...Load detection unit DET. 3... Periodic interrupt request section R, EQ, 4...
...Basic cycle generation unit GEN, 5...Cycle control unit CNT, 50...Frequency divider circuit DIV, 51.
...Selection circuit SEL. 7-′-\・、

Claims (1)

【特許請求の範囲】[Claims] (1)  自動交換機において、中央制御装置の負荷状
況を検出する検出手段と、該中央制御装置に周期割込み
を要求する割込み要求手段と、基本周期信号全発生する
発生手段と、該周期信号全前記検出手段の出力信号によ
り可変にする周期制御手段とを備えることを特許とする
負荷制御方式。 (2、特許請求の範囲第(1)項記載の負荷制御方式に
おいて、周期制御手段は発生手段からの基本周期信号を
分周する分周回路と、検出手段の出力信号に応じて所定
の前記分周信号を選択出力する選択回路を含み構成され
ることを特徴とする負荷制御方式。
(1) In an automatic switching system, a detecting means for detecting the load condition of a central control unit, an interrupt requesting means for requesting a periodic interrupt from the central control unit, a generating means for generating all the basic periodic signals, and a generating means for generating all the basic periodic signals. A patented load control method that includes periodic control means that is variable based on the output signal of the detection means. (2. In the load control method described in claim (1), the period control means includes a frequency dividing circuit that divides the frequency of the basic period signal from the generating means, and a frequency dividing circuit that divides the frequency of the basic period signal from the generating means, and A load control method comprising a selection circuit that selectively outputs a frequency-divided signal.
JP57221233A 1982-12-17 1982-12-17 Load control system Pending JPS59111493A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57221233A JPS59111493A (en) 1982-12-17 1982-12-17 Load control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57221233A JPS59111493A (en) 1982-12-17 1982-12-17 Load control system

Publications (1)

Publication Number Publication Date
JPS59111493A true JPS59111493A (en) 1984-06-27

Family

ID=16763547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57221233A Pending JPS59111493A (en) 1982-12-17 1982-12-17 Load control system

Country Status (1)

Country Link
JP (1) JPS59111493A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2616025A1 (en) * 1987-05-26 1988-12-02 Lespagnol Albert METHOD AND SYSTEM FOR CONTROLLING PACKET FLOW
FR2616024A1 (en) * 1987-05-26 1988-12-02 Quinquis Jean Paul SYSTEM AND METHOD FOR CONTROLLING PACKET FLOW

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5182537A (en) * 1975-01-17 1976-07-20 Hitachi Ltd
JPS5398745A (en) * 1977-02-09 1978-08-29 Hitachi Ltd Interrupt system for input and output device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5182537A (en) * 1975-01-17 1976-07-20 Hitachi Ltd
JPS5398745A (en) * 1977-02-09 1978-08-29 Hitachi Ltd Interrupt system for input and output device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2616025A1 (en) * 1987-05-26 1988-12-02 Lespagnol Albert METHOD AND SYSTEM FOR CONTROLLING PACKET FLOW
FR2616024A1 (en) * 1987-05-26 1988-12-02 Quinquis Jean Paul SYSTEM AND METHOD FOR CONTROLLING PACKET FLOW

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