JPS59108133A - Input/output controlling method - Google Patents

Abstract

PURPOSE:To execute effectively preceding reading and to shorten the access time by invalidating data stored in an FLFO memory at the detection of the initial word of a data transfer block, and reading out the data from a main memory newly. CONSTITUTION:In order to supply a block starting signal DMAST to a common bus between I/O controlling parts 4-6 and an I/O interface 3, the I/O controlling parts 4-6 output the block starting signal DMAST only when the initial direct memory access request DMARQ1 of a data transfer block is supplied. Therefore, even if the uncessary data of 6 words are left in locations 1010-1015 after transferring the data in the locations 1000-1009 of the preceding data transfer block, said data of the 6 words are invalidated by the block starting signal DMAST added to the initial direct memory access request of the succeeding data transfer block request.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to an input/output control system, and particularly to a method for controlling the data buffering operation of an input/output interface having a data buffering function using a FIFO memory. Regarding input/output control methods.

[Prior art]

In the conventional input/output control method, the input/output interface relays data read requests and data transfer from the input/output control unit to the main memory.

In such an input/output control system, data transfer from the input/output control unit is often performed to consecutive addresses.

Therefore, in order to transfer data at high speed in response to a read request, it is necessary to predict in advance that a read request will be supplied, read the data from main memory in advance, and input the data. The data is stored in a data buffer memory using a FIFO memory in the output interface, and in response to a read request from the one person output control section, the data is read from the data buffer memory instead of the main memory and sent to the one person output control section.

The data buffer memory provided in this input/output interface is constituted by a FIFO memory, taking advantage of the feature that data transfer from the input/output control section is performed to consecutive addresses as described above. Since the buffer memory of this turnout counter interface stores the data set by pre-reading, unnecessary data after the last word of the data transfer block requested by the turnout control unit is also stored. There are often

Therefore, the input/output interface needs to know from which word in the data 1 FIFo memory of the next data transfer block from the same input/output control unit should be stored.

Therefore, it is necessary to recognize up to which word of the data buffer memory the data read out by advance reading during the previous data transfer is stored.

In particular, if the last word in the previous data transfer was l” IFO
When it is at a deep address in memory, the first word of the first time is stored at the address next to that address, so FI
There is a drawback that the time required for the data to appear on the output of the FO memory, that is, the access time becomes long.

[Purpose of the invention]

An object of the present invention is to provide an input/output control method that can shorten access time.

That is, one object of the present invention is to solve the above-mentioned drawbacks of the input/output ink 7A, which relays the read request and all the read data when the input/output control section reads data stored in the main memory using the direct memory access method. remove the
Our objective is to provide an input/output control method that can completely reduce access time.

[Structure of the invention]

The input/output control method of the present invention is a FIFO memory IJ2 for storing multiple pieces of data in an input/output interface that relays data transfer between multiple input/output control units and main memory using a direct memory access method. have,
In an input/output control method that performs advance reading in order to read (7) data from the main memory and transfer it to the input/output control unit at high speed, the input/output control unit reads one block due to multiple direct memory access requests. At the first direct memory access request when one data transfer is performed, a transfer start signal indicating the start of the data transfer block provided on the common input/output bus is sent to all the input/output interfaces, and the transfer start signal is sent to all the input/output interfaces. is configured to invalidate the data remaining in the FIFO memory in response to the transfer start signal, and store data newly read from the main memory from the beginning of the FIFO memory. The system uses a direct memory access method to transfer data between multiple input/output control units and main memory.The input/output interface, which relays all data, has a data buffer using FIFO memory for several channels, and transfers data pre-read from the main memory. In the input/output control method that transfers data to the input/output control unit at high speed,
Indicates that the data transfer block provided on the common input/output bus is started at the first direct memory access request when the input/output control unit transfers l block data by multiple direct memory access requests. The input/output interface sends a signal to the input/output interface, and the input/output interface receives the signal indicating that this is the start of this data transfer block.

It is configured to shorten the access time from the input/output control unit by invalidating the data remaining in the data buffer memory using the FIFO memory and storing newly read data from the main memory from the beginning of the FIFO memory.

In other words, the input/output control method of the present invention is an input/output control method in which data is transferred by a direct memory access method via all input/output interfaces having a data buffer 77 using FIF (J memory), in which the input/output control section is connected. A signal indicating the start of a data transfer block is supplied to the common input/output bus, and when the input/output interface receives this data transfer start signal sent by the input/output control unit along with a request to read data stored in the main memory.

Invalidates data stored in FIFO memory.

FI with the function of making a new data read request to the main memory
By storing from the first address of FO memory,
This makes it possible to shorten access time.

[Explanation of Examples]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a data processing apparatus to which the present invention is fully applied.

In FIG. 1, 1 is a main memory with a 4-way interleave configuration, 2 is a central processing unit, 3 is an input/output interface to which the present invention is applied, 4. 5. 6 is various input/output control units, 11 is a processor bus, and 12 is a common input/output bus to which a ``block start signal'' is added according to the present invention.

Further, FIG. 2 is a block diagram showing in detail the inside of the input/output interface 3 shown in FIG. 1.

In FIG. 2, 21 is a FIFO memory read buffer for storing data read from the main memory, 22 is a write buffer for storing data written to the main memory, and 23 is access to the main memory. an address register that stores address information for
24 is a counter that indicates the position of the effective word of the data stored in the FIFO memory, 25 is another control circuit, and the input/output interface 3 has various other circuits, but they are not related to the present invention, so their explanations are omitted. do.

Figure 3 is a data map showing the map on the main memory of the cheetah block read by the input/output control unit through direct memory access.
Data for 0 words has been d'U'd.

Note that for ease of explanation, the contents of the data block are shown as the same as the address value as an example.

Also, as a first cheetah block, 2000 @ 20 from ground
It is assumed that 10 words of data are also stored at address 09.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

A certain program has 1000 memory blocks in the input/output control section of the main memory.
A case will be described in which an instruction is executed to read from address to address 1009 and write to the input/output device via the input/output control unit.

The central processing unit 2 interprets this command and sends it as a command to the input/output control units 4 to 6 via the input/output interface 3. To this command, the address 1000 is added as the reading start address of the main memory 1, and the 10ok parameter is added as the number of words to be transferred.

Input/output control unit that received the command 4. 5. 6 is a direct memory access request DMARQ shown in FIG.
, 1? Send to input/output interface 3.

The input/output interfaces 4 to 6 that have received this direct memory access request 1) MARQl' supply a read request MEMQl as shown in FIG. 4(a) to read address 1 (address 100) to the main memory l. .

Assuming that the main memory 1 that received this read request MEMRQ1 has a 4-way interleave configuration, the addresses 1000 of the first bank, 1001 of the second bank, and the third
Four words of data, one word each, are successively read out from address 1002 of bank No. 1002 and address 1003 of bank No. 4, and sent to the input/output interface 3 as data MEMDATA in FIG. 4(a).

The input/output interface 3 receives the received 4-word data MEM
] JATA is stored in the read buffer 23 composed of FIFO memory. At this time, since the input/output interface 3 is being stored in the FIFO memory for the first time, the input/output interface 3 has been initialized and the main memory l is
The contents of address 1000.

PIF (sequentially stored in all memory arrays from memory array No. 0 to memory array No. 7 of J memory). The data storage state of the FIFO memory at this time is shown in FIG. 5(a). The counter 24 shown in the figure is pointing to number 0.

The data "1000" stored in the memory array number 0 of the FIFO memory is taken out from the beginning of the FIFO memory (memory array number 0) and transferred to the input/output control units 4 to 6. At this point, since the FIFO memory lJH has been initialized, the control circuit sets a flag indicating that no valid data exists.

Subsequently, data "1001" read from address 1001 of the second bank of main memory 1 is stored in memory array 1 from FIFO memory number 00 to memory array number 7.

Once stored, the counter 24 points to number 0 again. FIF first
Since the data [1Ooo] written in the O memory has already been transferred to the input/output control unit, it is stored from the memory array 0@ of the FIFO memory, as shown in FIG. 5(b). .

10 of the second bank of the main memory l before the data l-1000J is transferred to the input/output control units 4 to 6.
When the data l100IJ read from address 01 is sent to the input/output interface 3, it is stored in memory arrays 1 to 7 of the FIFO memory, as shown in FIG. 5(C).

Since the read speed of data in the main memory 1 is faster than the direct memory access requests from the input/output control units 4 to 6,
The data "1oo2" read from address 1002 of the third bank of main memory 1 and the data "1003J" read from address i in O3 of the fourth bank immediately arrive at the input/output interface 3 and are stored in the PIF (J memory). Figure 5 (
Since data l-1001J is stored as shown in dJ, data l'1o02J is stored from memory array No. 1 to memory array No. 7 of the KFIFO memory as shown in FIG. 5(e). The next arriving data ll003J is stored in the same manner from memory array No. 2 to memory array No. 7 of the FIFO memory, as shown in FIG. 5(f).

With the above operation, the first data read request M to the main memory l
Pressing EM RQ completes data storage.

The FTPO memory of the input/output interface 3 has a capacity for 8 words. Therefore, after one data read into the main memory 1, only four words are stored, so there is still unstored capacity for four words. Therefore, as shown in FIG.
This is done for address 1004.

This read request to main memory 1 MEMRQ2 output control unit 4
Although the data read request from ~6 is still occurring,
Direct memory access by the input/output controls 81X4 to 81X is performed with special consideration given to continuous memory arrays and is called advance reading. Thereafter, this preliminary reading is performed when the free area of the FIFO memory of the input/output interface 3 reaches four words, taking into account that the main memory 1 has a 4-way interleaved configuration.

The second read request MEMI-tQ2 to the main memory is made at address 1004 of the first bank, address 1005 of the second bank, and address 3
This is performed for bank address 1006 and address +007 of the fourth bank.

When data 1-1004J read from address 1004 arrives at the input/output interface 3, it is stored in the number next to the array number of the FIFO memory indicated by the counter 24. That is, the data is stored from memory array No. 2 to memory array No. 7. Further, the counter 24 is also incremented by +1.

The data read out sequentially from addresses 1005, 1006, and 1007 are processed in the same manner as shown in FIGS. 6(a) to 6(a).
The data is stored in the FIFO memory as shown in (d).

Direct memory access requests DMAQ1 and DMAQ2 from the input/output control units 4 to 6 are memory data read requests MEMQ1 for the main memory 1.

It occurs asynchronously with MEMRQ2. Therefore, when there is a direct memory access request, as shown in FIG.
It is transferred to the word extraction input/output control units 4-6. The counter 24 is also decremented by 1 when the data is transferred.

As explained above, the input/output interface 3 makes a data read request on behalf of the input/output control units 4 to 6 of the main memory 1, but in order to shorten the data access time from the input/output control units 4 to 6, it Reading is in progress. Since the main memory 1 has a 4-way interleap configuration, this preliminary reading is performed in units of 4 words.

The data is stored in the FIFO memory of the input/output interface 3. Therefore, the data stored in the FIFO memory is in units of 4 words.When storing 4 words of data, the memory address is 1.
These are addresses 003, 1007, 1011, 1015, and so on.

In many cases, the data transfer blocks requested by the input/output control units 4 to 6 for memory data communication are not limited to units of four words.

In the above example, the data transfer block was explained as 10 words. Therefore, the input/output interface 3 issues the fourth read request MEMRQ4 to the main memory 1 as shown in FIG. 4(b).
', four words of data are read out and stored in the FIFO memory of the input/output interface 3, as shown in Figure 7(a).
The state shown in ~(b) is reached.

Also, the FI after the input/output control units 4 to 6 make the 9th and 10th direct memory access requests DMARQwhh
As shown in FIG. 7(f), two words have been taken out of the FO memory, but six words of previously read data remain.

In this case, the data transfer block required by the input/output control units 4 to 6 is 10 words, so the counter indicating the number of transfer words held by each output control unit 4 to 6 initially stores 10, and - Each time a word is transferred, it is subtracted and when it becomes O, the input/output control unit ~4~6 makes a direct memory access request 1)M
Does not output ARQi.

The above operation is the same in both the present invention and the prior art.

Input/output interface 2 in conventional input/output control method
(There is no way to determine whether there is a further request for the remaining 6 words of data stored in the dFIFO memory, or whether the data is unnecessary because there is no request for it. Therefore, the data transfer for 10 words by the input/output control unit is Even after completion, there is a trench that can store data for 6 words.Also, the counter is also FI.
Points to memory array No. 5 of FO and remains 0. Next, when the input/output control unit needs to read memory data from address 2000 to address 2009 in another data transfer block shown in FIG. A direct memory access request DMA, RQklfj is output to the output interface. The input/output interface is from address 2000 to 4 in main memory.
0) The free area in the memory is only for 2 words, so 4 words of data are read from the main memory. However, two words must be discarded.

4 words of data read from main memory [”2000J
, "2001J, [2002J, l-2003J", the first two words are stored after the remaining six words of the previous data as shown in FIGS. 8(a) and (b).

Furthermore, it can be determined that the six words remaining from the previous transfer in the FIFO memory of the input/output interface are unnecessary only when the next request for address 2000 is made.

The FIFO memory of the input/output interface stores 6 words of unnecessary data followed by 2 words of valid data.
If all unnecessary data for these 6 words were not shifted out, the data [20001: could not be sent to the input/output control unit.There was a drawback that the access time for data 1'2000J requested by the input/output control unit would be long. Therefore, in the present invention, in order to supply the block start signal DMA5Ti to the common input/output bus between the input/output controllers 4-6 and the input/output interface 3, the input/output controllers 4-6l-
It is output only when the first direct memory access request DMARQld of the data transfer block is granted. That is, in this example, it is output only when requesting to read data at address 1000 and when requesting reading data at address 2000.

The input/output interface 3 receives this block start signal DMA.
8T invalidates the contents of FIFO memory.

FIFO control circuit 25. Counter 24. Initialize.

That is, the input/output interface is initialized by returning it to a state where no data transfer was performed.

In a data processing device, Or'i performs an operation called initialization.
When the power is turned on and the 1 initialize switch is operated, the master clears, that is, returns all units to their initial state.

Further, since each of the input/output control units 4 to 6 is assigned an input/output channel number, a specific input/output control unit is initialized by a command that instructs initialization only for that input/output channel number. Since this initialization is a so-called bankrupt operation, it is not always performed.

I/O interface 3 without I/O channel numbers
1' is only performed when the power is turned on" and "when the initialize switch is operated," but when the input/output control unit starts data transfer, it sends the data transfer block start signal 1) MAST to the input/output interface, and the input/output Initialize interface 3X8i7.

As a result, after transferring data from addresses 10008 to 1009 in the previous data transfer block, from address 1010 to 1015
Request for the next data transfer block (from address 2000 to address 2009) even if unnecessary Cheetaro words remain for the address.
1) By the block start signal DMA5T added to MA Q, six words of data are invalidated, and data from addresses 2000 to 2003 is transferred to PIF' (No. 0 memory array of J memory). is overlaid and stored in memory array number 3 from
The data at address 000 is FI as shown in Figure 9(a).
The data is stored in the memory array number 0 of the FO memory and can be immediately transferred to the input/output control units 4 to 6, which has the effect of shortening the access time compared to the prior art.

〔Effect of the invention〕

In the input/output control method of the present invention, in an input/output interface with a data buffering function, when the input/output control unit reads main memory data, a signal indicating that the input/output control unit is the first word of a data transfer block is sent. It would be effective to shorten the access time by invalidating the data stored in the FIFO memory and reading the data anew from the main memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 2 is a block diagram showing in full detail only the inside of the input/output interface of the embodiment shown in FIG. 1; Figure 3 is a data map showing an example of data stored in the main memory shown in Figures 1 and @2; Figure 4(a);
())) is a time chart for explaining the operation of the embodiment shown in Fig. 1, Figs. This is a storage state diagram for explaining the data storage state of 1. Main memory, 2. Central processing unit, 3. Input/output interface, 4. 5. 6. Input/output control P.
S, 1.1... Processor bus, 12... Common input/output bus. 21...Read buffer, 22...Write buffer. 23... Address register, 24... Callan l, 2
5...Control circuit, 8IEMRQ 1-MEMRQ4...Read request, DMA
RQI~CIMARQIQ...Direct memory access request, IJMAs'T...Block start signal,
Al-A4...Memory reading koto position, B'l, B2...
Data transfer block, IVIEML) ATA...data, BKI~HK4...bank, PIF (JN(J
...Memory array number. 196 Figure 3 (ρ) Culture Δ flash lρ-D, 1711-i J"/111"r-〆lri I
f, l"J-Raσ7-J-n1"JJ85 Figure rIF-ON0 Non-88B Figure 17 '2D60J '2DotJ (a) (Where) Figure β (α) (c) (c)
(ti) Figure 9 Procedural amendment (method) % formula % (Showa year Mu 1: Chome Commissioner of the Patent Office 1, Indication of case 1988 % Permit application No. 217
975 ke 2, Title of the invention Input/output control method 3, Relationship with the case of the person making the amendment Application: Shiba I1, Minato-ku, C. 'I' l I 33 sounds 1 rin (423)
Representative of NEC Corporation and Tadahiro Sekimoto 4, Agent Address: L-1137-8, Shibaffi, Minato-ku, Tokyo 108
J: ft Tomoda Hill 5, date of amendment order March 29, 1981 (shipment date) 6, column 7 of ``Brief explanation of one drawing of the specification subject to amendment'', yes; positive internal temperature ( 1) "Figure 5 (a)" on the 21st negative second line of the specification
~Figure 9 (d) J k rFigure 5 ~ Figure 9” has been corrected. /'-

Claims (1)

[Claims] An F for storing multiple pieces of data in an input/output interface that relays data transfer between multiple input/output control units and main memory using the direct memory access method.
In a human output control method that includes an IFO memory and performs advance reading in order to transfer data read from the main memory to the human output control section at full high speed, the input/output control section responds to the direct memory access request multiple times. transmitting a transfer start signal to the input/output interface indicating that it is the start of a data transfer block provided on the common input/output lot at the time of the first direct memory access request when performing data transfer of the l block; The input/output interface receives the transfer start signal from the FI.
An input/output control method characterized in that data remaining in the FO memory is invalidated and data newly read from the main memory is stored from the beginning of the FIFO memory.