JPS59107272A - Display device - Google Patents

Abstract

PURPOSE:To display various information, which are required for signal processing, in real time, by calculating a VU level, peak level, and other information and outputting prescribed pattern information corresponding to the kind and the magnitude of a level on a basis of arithmetic results. CONSTITUTION:An audio signal is converted to a digital signal by an analog- digital converter ADC, and a central controller CPU operates the VU level, the peak level, and other information on a basis of digital data in a prescribed time width which is the output of the converter ADC, and prescribed pattern information corresponding to the kind and the magnitude of the level is outputted on a basis of arithmetic results. A video display processor VDP displays the output of the controller CPU on the screen of a display device with prescribed patterns of required level information and other information.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a display device capable of displaying various types of information required for audio signal transmission, recording/playback, signal processing, etc. on a display surface. Regarding.

(Prior art and problems) When transmitting, recording and reproducing audio signals, and processing signals, the signal level of the audio signal must be determined by considering the dynamic range and recording capacity of the signal transmission path, recording medium, and equipment used. settings, recording time, etc. have to be done, and traditionally, instruments that show the peak level and VU level of the audio signal, indicators that show the maximum value of the peak level, timers, etc. are used. It is coming.

Instruments and indicators that indicate the peak level and VU level, as well as indicators that indicate the maximum value of the peak level, are generally instruments equipped with six pointers, or a single indicator with an array of light emitting elements. It is well known that mechanical clocks and electronic digital clocks have been used as clocks and timers.

By the way, when performing audio signal transmission, recording and playback, and other signal processing in good conditions, it is not only possible to know the VU level and peak level individually, but also to clearly understand the relationship between each of the above levels. However, if the VU level, peak level, etc. are indicated by separate instruments, it is desirable to be able to directly see the relationship between the VU level and peak level. It is difficult to know.

Recently, there have been expectations for the appearance of display devices that can simultaneously monitor both image information (video information) and audio signals related to it. The present invention provides a display device that can display various types of information required when processing an audio signal in real time on a display surface that can display a television image. An analog-to-digital conversion means (hereinafter, analog-to-digital conversion is referred to as AD conversion) for converting an audio signal into a digital signal, and a predetermined time width obtained by the AD conversion means. a central control device that calculates the VU level, peak level, and other information based on the digital data in the central controller, and outputs one predetermined pattern of information corresponding to the type and magnitude of the level according to the calculation results; A video display processor is provided with output data from the central control unit, and is capable of displaying required level information and other information in a predetermined pattern on the display screen. .

(Example) Hereinafter, specific contents of the display device of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a gummy diagram of an embodiment of the display device of the present invention. In the first box, 1 and 2 are input terminals for each channel signal of a 2-channel signal, and in the following explanation, input terminal 1 is The input terminal 2 is for the left channel (L channel) signal, and 2 is the input terminal for the right channel (R channel) signal.

In the numbers, the subscript lrr indicates the distinction between the left channel and the right channel. The above-mentioned bandpass filters have their passband 4; the peak level of the audio signal, and
They are said to have the same passband characteristics that allow them to pass the frequency range required for U-level foot measurements.

At 8 in the figure, TER is a timer, and VR is a variable resistor for setting the time width set in the timer TER. Ma1ko 5 ■■ is a multiplexer, CPU is a central control unit, RAM is main memory, ROM is read-only memory, VDP is a video signal generator (video display processor), and V-RAM is a video RAM (1 piece). (RAM is random access memory), CRT is a display, and in the following explanation, the display is assumed to be a cathode ray tube.

In addition, the ADC in Figure 1 is an anamigu digital converter, and 3.4+5a and 5b in the figure are data buses.
Furthermore, RFC is an RF converter, and TVS is a television receiver.

The video signal generator VDP operates as an interface between the video ram V-RAM connected to it via the data bus 4 and the central control unit CPU, and also acts as an interface between the video ram V-RAM connected to it via the data bus 4 and the central control unit CPU. The video signal generation device is configured to be capable of generating a composite video signal in which an image self-response is determined by various types of data, and which conforms to a predetermined standard method. For example, as a VDP,
Nikkei Magmira Hill's [Nikkei Elect0nics J 19
It is possible to use the video display processor (VDP) manufactured by Texas Instruments, Inc., introduced in the March 30, 1981 issue (pages 156 to 164), and the following explanation It is said that the video display processor mentioned above is used as the video signal generator VDP.

Figure 2 shows path 4 to the video display processor.
In the memory map of the video ram shown in the second leg, 1024 bytes from address 50 to address 1023 are stored in the sprite generator table ( The 768 bytes from addresses 1024 to 1771 are used as the pattern name table (PNT), and the 128 bytes from addresses 1772 to 1919 are used as the sprite attribute table (SAT). I, moreover,
32 bytes from address 1920 to 1951 are used as the color table (0'), 96 bytes from address 1952 to 2047 are unused, and 20
2048 bytes from address 48 to address 4015 are used as a pattern generator table (PGT).

Pattern generator table PGT H, for example, one specific pattern can be stored in 8 pixels x 8 pixels using 8 bytes each, so 256 by 8 x 8 pixels.
Can memorize different types of patterns. The pattern information stored in this pattern generator table PGT is
Although the pattern generator table PGT is transferred from the read-only memory ROM in the initial state of the device by the operation of the central control unit CPU, it goes without saying that the pattern generator table PGT may be configured as a read-only memory.

As mentioned above, each 8-byte storage area in the pattern generator table PGTK has 8 bytes each.
Specific patterns of ×8 pixels are stored individually, and each specific pattern can be specified by a pattern name given to each storage area where each specific pattern is stored. Make it.

Pattern generator table PG in the example shown in the second diagram
In T, 256 types of patterns can be specified by 256 pattern names from Harun name +-1 to 255 pattern names.

Next - The pattern name table PNT is displayed on display C.
Information indicating which pattern name in the pattern generator chiful PGT each of the display sections assumed on the display screen of RT is stored.
In addition, the previous gilt-1 has a storage capacity corresponding to the total number of display sections.

In the example shown in Figure 3, the total number of sections set on the display screen is ((32 columns) x (24 rows)) = 768, and since 1 byte is used as the amount of information indicating one section, as described above. The pattern name table PNT is 768 as in
It is said to have a storage capacity of 1 byte.

As mentioned above, the required number of patterns are stored in the pattern degree Generadar table PGT in the video RAM, and the required pattern name assigned corresponding to each pattern is , when the pattern name table PNTK is stored in each section of the display surface, the video display processor VD
P includes the information stored in the pattern name table PNT in the video RAM RAMK, the information stored in the pattern generator table PGT, and the information stored in the color table CT as necessary. Display C generates a composite video signal in accordance with a specific standard format in which the image content is determined by
RT and a specific pattern is displayed on the display surface of the display CRT.

The explanation in this history is a display mode in which a specific pattern stored in the pattern generator Chiful PGT is displayed in a specific section among 768 sections on the display surface of the display, This relates to the case where a pattern is displayed in a so-called graphic mode.The pattern display in this graphic mode specifies the position of the pattern by the pattern name table PNT, and displays one pattern on the display surface. When attempting to move the pattern, the pitch of movement of the pattern is one section (distance of 8 pixels) on the display screen.

Therefore, in order to reduce the pitch of movement of the pattern on the display screen and make the pattern move smoothly, it is necessary to store this pattern in the sprite generator table SGT and to change the coordinates of the pattern. Move it within the display screen at the pitch of pixels.

The pattern stored in the sprite generator table SGT may be 8 pixel x 8 pixel sprite data or 16 pixel x 16 pixel sprite data. For each pattern stored in the SGT, a sprite name is assigned individually, such as ≠0゜111-1...+-N, but each sprite name is attached to the sprite corresponding to the pattern. The smaller the numerical value indicated by the sprite name, the higher the priority of the surface.

In the memory map of the video RAM shown in FIG. 2, 1024 bytes from addresses 0 to 1023 are assumed to be used as the sprite generator table SGT, as described above. ,
In this example, the pattern is 8 pixels x 8ii! In the case of ii element, there are 128 patterns (sprite name 4O-
4127) can be stored, and the pattern can be 16 pixels x 1
In the case of 6 pixels, there are 32 patterns (sprite name 1
o-4al) can be memorized. In video ram v-RAM, sprite generator table 5GTK
It goes without saying that in this case, where 2048 bytes are allocated, the number of patterns stored in the sprite generator table SGT is twice that of the previous case.

The sprite attribute table SAT uses 4 bytes for each sprite, including the sprite position & (1 byte each for specifying the vertical and horizontal positions), the name of the display sprite (1 byte), and the color. Since the code and end code (1 byte) of the displayed sprite are set, if 128 bytes are used as the sprite attribute table SAT, information for 32 sprites is stored in this sprite attribute table SAT.

The position of the sprite is in the horizontal direction (X direction) on the display screen.
256 pixels (8 pixels x 32 sections) and vertical direction (Y direction) 1
The coordinates of 49152 pixels, which are determined by 92 pixels (8 pixels x 24 sections), are determined by the i-antinoposition (the gecko value indicating the number of pixels in the vertical direction) and the horizontal position (in the horizontal direction). The gauze value indicating which pixel it is) is the sprite attribute table SA.
It is determined by writing TK (the origin of the sprite is set to the upper left corner of the sprite), and the sprite can be moved by pinching one pixel.

In the display device of the present invention, a plurality of m+7') patterns are stored in the pattern generator table PGT, sprite generator table SGT, etc., and patterns to be displayed on the display surface of the display can be selected and patterns This data is written in the sprite attribute table SAT in correspondence with the maximum peak level of the mode of movement of the sprite, so that a specific pattern can be freely displayed on the display surface of the display. This data is written in the pattern name table PNT in correspondence with the peak level of the audio signal, the time elapsed information on the timer, etc., and the pattern selection and pattern movement mode are specified by this data. This makes it possible to display a specific pattern on the display surface of the display.

FIG. 4 shows an example of the manner in which various information is displayed on the display surface of the display device aK of the present invention.

R is a display pattern for distinguishing between that, that L channel, and the R channel on the display surface, and is shown in the horizontal direction approximately in the center of the display surface. -30, -20, -1
Codes and numbers such as 5,...4.6, 8.10 are display turns to display the decibel value of the signal level on the display screen. The vertical lines shown are a T-shaped display pattern for displaying the scale on the display surface, and furthermore, the circles and numbers in the upper left part of the display surface are for displaying the timer on the display surface. It shows the kth display pattern to be performed.

Soil 1. The white triangles pointing downward and upward in Figure 4 are V.
This is a T-time display pattern that shows the maximum value of the U level on the display surface, and the downward and upward black triangles in the figure indicate the 1-time display that shows the maximum value of the peak level. This is the first display pattern to be displayed on the display screen.Furthermore, the text in English characters shown in the lower part of the display screen is a summary of the display content to be displayed on the display screen. This is a T-shaped display pattern shown on the screen.

Various display patterns as shown in the fourth figure displayed on the display surface are stored in read-only memory ROM in advance.
At the start of operation of the display device, various display patterns stored in the read-only memory ROM are stored in the central control unit tCPU and the video display. It is transferred to the pattern generator table PGT and sprite generator table SGT in the video RAM V-RAM via the processor VDP, and is used for display operations on the display surface. This point will be discussed in detail later.

One audio signal cuff is supplied to input terminals 1 and 2,
When applied to the double-wave rectifier circuits FRt and FRr via individual bandpass filters BPFt and BPFr, the double-wave rectified output of the left channel audio signal from the double-wave rectifier circuit FR1 is sent to the multiplexer ■■. The double-wave rectifier circuit FRr supplies the double-wave rectified output of the right channel audio signal as an input signal to the multiplexer (■■).

In the configuration example shown in the first diagram, the multiplexer ■
For (2), in addition to the output from the above-mentioned double-wave rectifier circuit FR6°FRr, the output from the timer TER is also provided as an input signal, and the multiplexer (2) is input from the central control unit CPU. A switching operation is performed in accordance with the switching control signal provided, and the three input signals provided therefor are sequentially supplied to the AD converter ADC.

The timer TER in Fig. 1 can be configured as a sawtooth wave generator, for example, and the cycle of the output sawtooth wave can be made longer or shorter by adjusting the variable resistor V'R. Make it configurable. As the sawtooth wave generator, a well-known type that generates a sawtooth wave by stacking pulses in a stepwise manner can be used.

As the timer TER, we use one that generates an analog signal whose size gradually increases linearly on the time axis as described above, and sends it to the CAD converter ADC via the multiplexer MPX. is converted into a digital signal, which is sent to the central controller CP as time information.
Used in U. Instead of using the configuration shown in the first diagram, in which the number of seconds is set to 5, a timer built in the central control unit CPU may be used. In this case, press the timer input button indicated by the imaginary line frame TER8W in Figure 1 (for example, at 30 minutes, 45 minutes - 120 minutes, etc.) settings.

The central control unit CPU performs the operations shown in the fifth (2) flowchart to create data required for displaying various levels of audio signals and timer displays, and displays the data on the video display.・Processor V
4 in the DP, video RAM, and RAM, and a display as shown in the fourth figure is made on the display surface.

In the flowchart of Figure 5, in step (1) 1
1t power is turned on and the display device starts 1. Next, in step (2) 5 initialization (system initialization/reset number) is performed, and the AD converter ADC and the main memory are reset.
AM + Video RAM V-RAM, etc. are cleared, and the video display processor ■D
The registers in the PK are set, the storage area in the video RAM V-2 is used for which table, the operating mode is set, and the read-only memory is set. Predetermined types of pattern information (for example, character and number pattern information shown in the 4th □□□, timer pattern information, vertical line, vertical bar pattern) are sent from the IJ ROM to the pattern generator table PGT. information) via the video display processor VDP,
From this read-only memory ROM, predetermined types of pattern information (for example, a hood, - pattern information of upward and downward white and black triangles shown in FIG. 4, Pattern information of vertical lines and vertical bars) is transferred, and furthermore, the sprite attribute table SA is transferred from the lead-on #book memory ROM.
Sprite names, Y coordinates, color data, etc. are transferred to T.

Then, the central control unit t CPU repeatedly executes each step from step (3) to step (IQ),
First, the operation of the multiplexer MPX and the AD converter ADC is controlled and various input data are processed by the interrupt operation consisting of each step from step αυ to step a → performed at predetermined intervals by the internal counter of the central control unit CPU. The data is stored in the main memory RAM.

First, an explanation will be given of the interrupts made up of each step from step Q to step Q. Interrupts are handled by the central control unit CPU
This is carried out at regular intervals by a counter built in the converter, and controls the switching of the multiplexer MPX, starts the conversion operation for the AD converter ADC, and stores data. That is, step (11
), performs AD conversion on the sample value of the left channel signal, stores it in the main memory RAM in step (6), and performs AD conversion on the sample value of the right channel signal in step Qj. → transfer it to main memory RAM
Further, in step (g), the sample value of the timer value is AD converted, and in step CL, it is stored in the main memory RAM, and the interrupt ends. The central control unit CPU is interrupted and returns to the control operation at the point just before this point in time.

Now, in step (3), the VU level is calculated. To calculate the VU level, it is necessary to calculate the signal level of the audio signal in a predetermined time width T (for example, 300 milliseconds). Data is needed.

In other words, the VU level of the audio signal is as follows: Let the audio signal rise at a time interval of 30051) seconds, and
This is because it can be obtained in a falling phase of 1 with an i constant of 300 m') seconds.

Now, let T be the time length of the audio signal that is not used for the calculation of the VU level.In this case, then iw length Tσ)lVl has N sample values (sample values of the signal level of the audio signal).
, then the calculation of the U level begins with calculating the arithmetic mean of the N sample values existing during the L time length T described above.

For example, +T is 300 milliseconds and the sampling period is 10
If the number of samples N is 30 milliseconds, then the arithmetic mean of 30 sample values is calculated.

The calculations performed using the N sample values existing during the certain time length T mentioned above are as described above, and the steps u
This is done sequentially and individually for the left channel audio signal and the right channel audio signal stored in the main memory RAM in step ◇→. It is effective to store successive sample value data for each channel in the main memory RAM as shown in FIG. 6 for each channel in order to facilitate calculations.

That is, in FIG. 6, M11M2...an are n storage areas each of which can store N sample value data, and the moxibustion storage areas M1 to Mr+ shown in FIG. It is assumed that a sample value, which is a container, is stored in each of a total of n sections divided by vertical lines and indicated by 41.42, ≠3...≠n. Note that FIG. 6 shows only the storage area used for storing one channel of audio signal, and in order to store two channels of L and R audio signals, the storage area shown in FIG. It goes without saying that it is necessary to prepare two sets of storage areas for the M1 to 7R channels, one for the L channel and one for the 7R channel.

The VU level calculation, peak level calculation, and other calculation methods described below are based on the L channel signal and the R channel signal.
Since there is no difference between the R channel signal and the R channel signal, the following explanation will be made without distinguishing between the R channel and the R channel signal.

First, to simplify the explanation, let's assume that successive sample value data of an audio signal is stored in the main memory W from a state where the main memory ~W is cleared. The level calculation will be described as follows.

The sample value of the audio signal at time t is subjected to AD conversion, and the sample value data output from the AD converter 21A ADC is set to 81, and similarly, the samples obtained at times t21t3...tn are Each value data is S2
．． When expressed as S3...Sn, sample value data S, I82...Sn obtained one after another on the time axis are stored in the above-mentioned 7Cn storage areas M in the main memory (RAM), for each section of the seed. and store it in the following manner.

That is, the sample value data SI is stored in section +1 in the storage area M and S in the main memory section, and
The sample value data S2 is divided into sections ≠ 2 in the storage area M1,
The sample value data S3 is stored in the partition ≠1 in the storage area 'MQVC:, and the sample value data S3 is stored in the partition 3 in the storage area M, the partition +2 in the storage area ``MQVC:'', and the partition in the storage area ≠
With the storage mode such as 1 and 1,
Sequential sample value data is stored in the main memory, and the storage state shown in No. 61 is achieved.

The N sample value data of the audio signal is sequentially sent to the main memory RAM (cleared main memory in the friend state) tAM to the main memory RAM, and as for the storage area M1, all sections of it +1-≠ n is sample value data S,
~Sn is stored, and then the (N+1)th sample value data of the audio signal is stored in the main memory R.
After being sent to AM, the storage area M2 is set to 1 state with sample value data stored in all sections -11-1 to +-n. In the same way, sample value data is sent one after another to the main memo section, and the storage area M
8. M4...the hermitage is sequentially stored in all the sections +1 to +n, and is brought to a state of one.

Then, successive N sample value data of the audio signal are sent to the main memory in the cleared state as described above, and the data is stored in the storage area M.

However, once the sample value data has been stored in all the sections 4P1~in, the state is set to 1. Next, all the sample value data stored in the Mi'' storage area M is taken out. , the arithmetic mean value of it is calculated, and then, following the above state, the next sample value data is sent to the main memory card and the storage area M2 is filled with all the partitions ≠ 1 to 4Pn.
The sample value data has been completely stored in the storage area M2. Next, all the sample value data stored in the storage area M2 is extracted and the arithmetic mean value thereof is calculated. M3. After all the sample value data of all the partitions +-1 to +nK in them have been stored in each of the storage areas M3. For each M4...Mn, extract all the sample value data stored in it and find the arithmetic mean of the fidgets. The arithmetic mean value of the signal level over the time length T can be obtained one after another.

Incidentally, when a certain storage area is sent with all the ward value data, the successive sample value data mentioned above are sequentially stored in the partitions ≠ 111#2, etc. in that storage area. It is clear that by being stored in such a manner that , in the state after the sample value data has been stored in all sections of all the storage areas M, ~Mn, the storage areas M,, M2...Mn + M, + M2...
・The memory data in each item is l purlin period T.
s (Ts=%), and each storage area M, ~Mn stores N sample value data over a time span T. .

Now, in the main memory RAM which is cleared and in this state, A
The sample value data output one after another from the D converter ADC is
Data is sequentially stored in each memory area M, . Then, the central control unit tCPU takes out the sample value data S, ~Sn stored in all the sections 4p1 to 41nK in the storage area M1, and processes them as described above.
Then, the calculation result is compared with the calculation result of the previous VU level stored in the main memory.

Now, the arithmetic mean value (8
1+S2+°°°8n) If the calculation result of the previous VU level is 5vuo, then Sb and Svu.

Generally speaking, the results of the comparison will be in one of the following three cases.

5vuo (Sb, --(1) Svuo = Sb, ---・= (2) Sv
uo) Sb, --(3) If the comparison result is (1) or (2), the value of Sb1 is set as the new ■U level value svu and the VU level stored in the main memory ~ W Rewrite. If the comparison result is (3), the previous VU level Svu.

The falling time constant of the VU meter (e.g. 300 milliseconds)
By performing an operation of multiplying by a coefficient K corresponding to
Svuo is found and one step later, this KSvuo and sb are compared.

KSvuo (Sb, ・−・−(4)KSvuo =
Sb, --(5) KSvuo ) Sb, --(6) The three cases shown in (4) to (6) may occur as the above-mentioned tile comparison results, but the comparison result is (4).

In the case of (5), sb is set to a new VU level value (current ■U level value) Svu,h, and the VU level stored in the main memory is rewritten. Well, if the comparison result is (6), the KSvuoO value is set to the new V
V stored in main memory RAM as U level
[Replace J level.

In addition, in the example KN, the first operation is performed on the sample value data S, ~Sn stored in the Me storage area M1. Since operation *>, in the case of the example, the arithmetic mean value Sb1 is VIJL/Svu.

Needless to say, the information is rewritten and stored in the main memory RAM as an image.

Next, after one bar main circumference NJ 1”s has elapsed, write 1. # t
+Jf Ji! All sections of 1 sound = #1 to valve 71
When the sample value data is stored in the storage area M2 and the sample value data 82 to Sn+1 are stored in this state, the central control unit CPU calculates the j-operational mean tFiSb2 of the sample value data 82 to Sn+1 stored in the storage area M2. A comparison is made with the previously calculated VU level Svu, and the new VU I/B/L is calculated. below,
In the same way, new VU levels are calculated one after another every time one cycle of calculation passes, and one new VU level calculated in this way is stored in the main memory RAM. It is rewritten and stored in a predetermined storage area.

The calculation of the rs VU level explained so far is performed in step (3) in the flowchart shown in FIG. V on the L channel signal.
It goes without saying that the U level and the VU level for the R channel signal are stored in respective predetermined storage areas in the main memory RAMK.

Next, the calculation of the peak level in step (4) in FIG. 5 will be explained. The calculation of the peak level is performed by extracting the latest I/+2 sample value data from among the sample value data used in the VU level calculation described above and the previous peak level value. That is, taking as an example the single sample value data S, ~Sn stored in the single storage area M, which has already been described, the P and F levels are first 5.
It is determined by comparing two sample values/data, n-1 and Sn, and performing a predetermined calculation according to the comparison result.The above comparison result is as follows (
There are three cases: 7) to (9).

5n-1> Sn −・47) Sn −1= Sn −−−・−(8) Sn−1< S
n −= −(9) First, the temporary peak level value Snp and the previous peak level value S stored in the main memory RAM are determined.
Comparing with et, Spt<Snp---5Q Spt=Snp-=-IJl) 8pt) Snp...9If both are on and in the relationship of (11), then , the temporary peak level value Snp determined as described above is determined as the current peak level value Snp, and this is rewritten and stored in the main memory as the current peak level value.

First, when the above-mentioned previous peak level value SpL and temporary peak level value Snp have the relationship (b), the previous peak level value 5pLK, the falling foot count of the peak level meter (for example, 1.5 seconds) is performed to obtain KpSp_pt, and after one step, this KpSpL is compared with the above-mentioned tentative peak level value Snp.

KpSpt < 8np... (to) KpSpL
-Snp...α◆KpSpA) Snp・
...(C) And as the result of the above comparison α]
Three cases can occur, represented by
K Store as the current peak level value.

If the comparison result is 4, the previous peak value Spt is multiplied by the coefficient Kp, 1 KpSpt is set as the new peak level value Snp, and it is stored in the main memory RAM K3J.
Rewrite and store as the current peak level value.

Next, the two sample value data Sn-+ and Sn are (7)
, if the relationship in (9) exists, and one of the two sample value data used for comparison is 0.
Toki K, which shows a value close to , is determined to be a level value of -15 dB lower than the peak level indicated by the larger sample value data as the current temporary peak level Snp, and it is stored in the main memory RAM. Previous peak level value Sp
L, and depending on which of (11 to (6)) the comparison result corresponds to, explain with reference to the relationship of (11 to α→).1 Similarly to this, the current peak The level value Snρ is determined, and it is rewritten and stored in the main memory.

Well, the two drift value data Sn-, and Sn are (7)
, 2 which is in the relationship of (9) and used for comparison
In the two cases mentioned above, the sample value data is
When the two sample value data used for comparison are equal,
Is one of the two sample data used for comparison close to O? If yes, the difference between the two sample value data corresponds to a predetermined level of 9 degrees, for example, -10 dB, -5 dB, - with respect to the larger peak level.
A predetermined level value such as 3 dB is determined as a temporary peak level value Snp, and the temporary peak level value Snp is compared with the previous peak level value Spt. A new peak level value Snp is determined according to the peak level determination method described above with reference to OFJ, and is rewritten and stored in the main memory RAM as the current peak level value.

The above-mentioned calculation performed as the peak level calculation in the flowchart for the fifth factor is also in the memory area M.

M2...Mn are performed sequentially, and
The operations performed individually for the R channel and the R channel one after another are the same as in the case of the r,=VU level calculation described above.

Next, step (5) in the flowchart shown in Figure 5'
The peak level ho/do operation performed at ) is
This is carried out according to the steps specifically shown in the seventh factor. That is, both the hold value of the previous peak level stored in the main memory RAM in step (5A) and the current peak level value determined and stored in the main memory in step (4) are Read and compare to see if the current peak level is higher. If the current peak level is higher (YES)
), a timer for peak value hold is set in Stella 7' (5B), and in step (5E), the current peak level is stored in the main memory RAM as a hold value of a typical peak level, and the process ends. 1. If the comparison result in the above step (5A) is No, that is, the hold value of the previous peak level is greater than the current peak level, the timer for peak value bold is set in step (5C). The countdown continues until the time set in the timer for peak value hold in step (5D) (for example.

3 seconds) has ended, and if NO, it is over; if YES, proceed to step (5E) and store the previous peak hold value in the main memory RAM as a new peak level hold value. end.

Next, in step (6), after the acid source has been introduced in step (1) and the display device has started operating, the highest VU level and peak level are determined, and the highest VU level and peak level are determined. What is the ratio of the time value from the start of operation to the device's expected operating time (for example, if the device is a tape recorder, the time value is determined by the data tape being used)? It is calculated from the output of the timer TER, and the result is stored in the main memory RAM.

Next, in step (8), the VU level value calculated in step (3), the peak level value calculated in step (4), the hold value of one peak level calculated in step (5), and step (6) Determine which position on the display screen, which is graduated in decibels, corresponds to the maximum VU level value, peak level value, etc. calculated in step (7). In step (9), add up the position on the display screen occupied by the time rate, and then
), create data to be written in the pattern name table PNT and sprite attribute table SAT, and then in step αQ write the above data to the video display processor VDP.・The video display processor VDP creates a composite video signal from the data written to the video RAM V-RAM as described above, and transfers it to the display CRT. A monitor TV that sends signals to the RF converter RFC and receives the display screen of the display CRT and the output signal of the above-mentioned RF converter.
Various signal levels, time rates, etc. are displayed in required patterns on the display screen of the TVS receiver.

An example of the manner of displaying the various tabs and the manner of displaying the line spacing ratio (timer display) displayed on the display surface as described above will be explained as follows.

First, even if the power is turned on and the display device is ready for operation, the display on the display screen of the display CRT when there is no signal input to the input terminals 1 and 2 is as shown in Figure 8. , input terminals 1 and 2, R channel signal 1
; For the L channel, vertical bars are arranged on the display surface of the display between the left side of the line and the peak level of the signal, and the instantaneous An instantaneous signal is displayed, and 7:
, for the R channel, a pattern with vertical bars arranged from 1 to the left of the letter R displayed on the display surface to the peak level of the signal,
The instantaneous signal is displayed, and the above-mentioned instantaneous signal is displayed in such a way that the length of the row of vertical bars expands and contracts as the peak level of the signal fluctuates. ing.

The display from (1) to the peak level of the signal is done by an array of vertical bars.
Write data to the generator table PGT, and then use the peak level data of the signal to determine the area where the vertical bar patterns described above are arranged, and write the pattern name in the pattern name table PNT in correspondence with that area. This can be easily done by writing . In that case, for example, the vertical bar displayed to the left of the OdB position is colored light blue, and the vertical bar displayed to the left of the OdB position is colored light red. It is also easy to display the

Since the peak level 1k of the L and R channel signals changes instantaneously, the past peak levels close to the current time are continuously displayed for a short period of time (for example, 3 seconds). This is significant when processing audio signals, and can be done by displaying the hold value of the peak level in a constant pattern, for example, as a vertical bar. The pattern is the hold value at ~peak level.

This peak level hold value pattern PH is such that when the peak level of one new signal exceeds that value, the peak level hold value pattern PH is rewritten by the one more peak level value. is already mentioned above, but if a peak level value exceeding it does not appear for a certain period of time (e.g. 3 seconds iJ+), 1. 3 seconds) K
Wow, keep displaying this. The bold value of the peak level is the pattern genera
It can also be displayed using T and pattern name table PNT, or alternatively, sprite generator table S
It can also be displayed using GT and sprite attribute table SAT.

The VU level is displayed as a thin vertical white line on the screen of the display, as indicated by the symbol VU in FIG.

(1'lVU level display is shown in sprite generator table SGT and sprite attribute table SAT.
This can be easily done using

The pattern VUm shown by the white z-square in No. 41 is
This is a pattern that indicates the maximum value of the VU level, and the pattern Pm indicated by a black triangle in FIG. 4 is a pattern that indicates the maximum value of the peak level.
m nato is sprite generator table SG
It can be easily displayed by using T and sprite attribute table SAT.

The time rate pattern shown by Trn◆ in the group in FIG. 4 can also be displayed using the pattern generator's own table PGT and the pattern name table PNT.

(Effects) As is clear from the detailed explanation above, the display device of the present invention can hold the peak level of the audio signal, hold the peak level (lit, VU level, maximum value of VU drop, peak level The maximum value, time rate, etc. can be displayed simultaneously on the same screen in real time in a single list, making it easy to adjust and monitor the signal level during audio signal transmission, recording and playback. Since it is easy to enlarge the display surface, it is also easy to make it possible for multiple people to view the screen at the same time. It can be well adapted to requests such as side-by-side signal monitoring, and can also be used to easily display the signal level in a stereo playback device, for example, by using a home TV receiver. The device of the present invention can be effectively used in various fields and modes of use.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the display device of the present invention,
FIG. 2 is an example of the memory map of the video RAM, FIG. 3 is an explanatory diagram of the divisions of the display surface, FIGS. 4 and 8 are diagrams showing examples of display patterns on the display surface, and the fifth and seventh examples The figure is ) O-chart, and FIG. 6 is an explanatory diagram of the &'' state of sample value data to the storage area. 1, 2 ・, - input terminal, BPFt, BPFr - bandpass filter, MPX... Multiplexer, ADC...
・AD converter, TER-=timer, CPU... central control unit, RM... main processor, CRT...
Display, RFC...RF Humbater, TVS
,,-TV receiver, patent applicant: Victor Japan Co., Ltd., 6...

Claims (1)

[Claims] 1. An analog-to-digital conversion means for converting an audio signal into a digital signal, and a VU level based on the digital data within a predetermined time span obtained by the analog-to-digital conversion means. and the peak level, and depending on the calculation result, 1 is determined according to the type and magnitude of the level.
This is a central control unit that outputs predetermined pattern information, and a video controller that receives the output data of the above-mentioned central control unit.
The display device 2 is equipped with a display processor so that either the VU level or the peak level of the audio signal can be displayed on the display screen in real time. The VU level, the peak level, and the hold level of the peak level are calculated based on the digital data within a predetermined time range obtained by the analog-to-digital conversion means for converting into a signal and the analog-to-digital conversion means. and a central control unit that outputs predetermined pattern information corresponding to the type and magnitude of the level based on the calculation result, and a video display processor to which the output data of the first central control unit is given, The display device 3 is capable of displaying the required one of the VU level, peak level, and peak level hold level of the audio signal on the display screen in real time. The conversion means calculates the VU level and the peak level based on the digital data within a predetermined time span obtained by the above-mentioned 7S Og digital conversion means, and calculates the VU level and the peak level. A central control unit calculates the maximum value up to that point and outputs a predetermined pattern information corresponding to the type and magnitude of the level based on the calculation result, and a video controller to which the output data of the central control unit is given. The display processor is equipped with a display processor, and is capable of displaying required values among the VU level and peak level of the audio signal, the maximum value of the VU level, and the maximum value of the peak level σ) on the display surface in real time. 1 display device. 4. An analog-to-digital conversion means for converting an audio signal into a digital signal; The central I11 control outputs one predetermined turn information corresponding to the type and magnitude of the level based on the calculation result, and also outputs predetermined pattern information corresponding to the timer information. and a video-display processor fed with the output data of the above-mentioned central control unit, which outputs one or both of the VU level and the peak level of the audio signal on a display surface. A display device that can display in real time and also display a timer on the display surface in real time.