JPS59106047A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a memory capacity and the processing efficiency, by constituting a memory with a half word as a unit length and designating two continuous addresses optionally to remove restrictions on arrangement of the memory. CONSTITUTION:When a read instruction is given to a CPU, a memory 9 is addressed through a CPU register 2, an address control circuit 5, adders 6 and 7, etc. That is, address 0 (lower byte 9b) and address 1 (upper byte 9a) are designated when an even address is the upper address, and address 1 (9a) and address 2 (9b) are designated when an odd address is the upper address. A swapping circuit 13 reads out data and exchanges or does not exchange upper and lower bytes in accordance with the least significant bit and outputs data to a data bus control circuit 3 through a gate circuit 14. In case of write, the similar processing is performed. Thus, the memory is constituted with a byte unit (1/2 word) as a unit length to improve the use efficiency of the memory capacity and the processing efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microcomputer capable of executing instructions in units of different bits.

[Conventional technology and melting point]

In a normal 16-bit or higher computer, word instructions (for example, in the case of a 16-bit machine, instructions for 16-bit data operate on data on word boundaries). In the case of a word-based instruction, the instruction contents are written into the memory at two addresses, an even address and an odd address following it, but the instruction is read out by addressing the even address. In this way, in the past, instructions were issued one after another by specifying addresses at even addresses, so for example, the upper byte of the 2 bytes (16 bits), such as N0P (no operation), WAIT, etc. Even a simple instruction that is ``0'' requires a 16-bit word.

For this reason, the memory capacity cannot be used fully efficiently, and all 2-byte instructions must be processed at all times, resulting in inefficient data processing.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is possible to access any consecutive bytes in memory as one word without being bound to word boundaries, and it is also possible to reduce the number of bits constituting a simple instruction, thereby reducing memory capacity. It is an object of the present invention to provide a microcomputer that can be used efficiently and has improved processing efficiency.

[Key points of the invention]

The present invention provides a memory with a capacity of 172 words at each address, so that two consecutive addresses can be specified arbitrarily, and in the case of a simple instruction, it is possible to process an instruction of 1/2 word. It is something.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an arithmetic unit, a CPU register 2,
It is connected to a data bus control circuit 3 and an instruction register 4 via a data bus DB. An address control circuit 5 is connected to the CPU register 2. This address control circuit 5 outputs address data according to the case from the CPU register 2, and this address data is sent to the first and second adders 6.7. Furthermore, among the address data output from the address control circuit 5,
The least significant bit LSB is output from the output line 5a and sent directly to the second adder 7 and to the first adder 6 via the inverter 8 as a +1 signal. Then, the address of the memory 9 is designated by the outputs of the adders 6 and 7. The memory 9 is configured in byte units, with an upper byte 9a in the memory being configured by an odd address and a lower byte 9b in the memory being configured by an even address. Further, a swap circuit 11 is connected to the data bus control circuit 3 via a gate circuit 10. This swap circuit 11 is controlled by the least significant bit LSB output from the address control circuit 5 to the output line 5&.When the least significant bit (LSB) is 10'', the upper byte of the input data is output to The lower byte is input to the even address side of the memory 9, ie, the lower byte 9b of the memory 9, via the output line Ilb. 11, when the least significant bit LSB is "1", the upper byte of the input data is output to the output line 11.
b to the lower byte 9b of the memory 9, and the lower byte is input to the upper byte 9k of the memory 9 via the output line 11g. And the upper byte 9 of this memory 9
The upper byte data read from the lower byte 9b is sent to the swap circuit 13 via the 8-bit pass line 12m, and the lower byte data read from the lower byte 9b is sent to the swap circuit 13 via the 8-bit pass line 12b. Sent to 13.

The swap circuit 13 is connected to the lowest pin (LS) output from the address control circuit 5 to the output line 5a.
It is controlled by H, and the lowest bit (LSB) is '
When it is "0", the upper byte and lower byte are not exchanged and output, and when the least significant bit (LSB) is "1", the upper byte and lower byte are exchanged and output. Then, 2 bytes (16 bytes) are output from the swap circuit 13.
The data of the pit) is sent to the data bus control circuit 3 via the gate circuit 14, and further transferred to the instruction register 4. This instruction register 4 consists of an upper register for the upper byte and a lower register for the lower byte, and the instruction fetched from the data bus DB is transferred to the instruction decoder/CPU.
It is transferred to the control circuit 15.

This instruction decoder/CPU control circuit 15 decodes the input instruction, performs gate control of the gate circuit 10.14, sends a length signal to the address control circuit 5, and further controls the CPU and system. .

Next, the operation of the above embodiment will be explained. First, an explanation will be given of the operation when a read command is given from the CPU with an even numbered address as the uppermost address. The address control circuit 5 is CP
According to the data held in the U register 2, address data specifying an even address, for example, address 0, is output and input to the first and second adders 6 and 7. At this time, the least significant bit LS
Since B is 10'', the output of the inverter 8 becomes 1'' and provides a "+1" signal to the first adder 6. Therefore, the address data is r+IJ only in the first adder 6, and its output becomes "1". On the other hand, the second addition η, vessel 7 is
The input address data rOJ is output as is.

Therefore, memory 9 has addresses 0 (lower pie) 9b) and 1
The address (upper byte 9a) is addressed, and its storage contents are read out to the swap circuit 13. In this swap circuit I3, the least significant bit LSB of address data is on.
In this case, the upper byte and lower byte read from the memory 9 are not exchanged and are output to the data bus control circuit 3 via the gate circuit 14.

In addition, a series of instructions from the CPU with odd-numbered addresses as high-order
When given to the PU register 2, the address controller 5 outputs address data specifying an odd address, for example address 1, and inputs it to the first and second adders 6 and 2. At this time, the LSB (lowest bit) is "1", so
A “+1” signal is input to the second adder 7. Further, since the least significant bit (LSB) is inverted to "O" by the inverter 8, the 1' adder 6 outputs the address data "1" as is in the "+1" operation. And the second adder 7
is the address data “1” by the above 1’-+IJ signal.
” as r+IJL, outputs address data specifying 2@ ground. Therefore, memory 9 is at address 1 (upper pie) 9a)
and address 2 (lower byte 9b) are specified, and the stored contents are sequentially output to the swap circuit 13. This swap circuit 13 operates at the lowest bits (I, S) of address data.
When B is '1'', the upper byte and lower byte are exchanged for the data read from the memory 9, and the gate circuit 1
4 to the data bus control circuit 3.

Next, the operation for loading data into the memory 9 will be explained. When writing data into the memory 9, addressing is done in the same manner as in the case of reading data described above.

That is, when address data specifying an even address, for example address 0, is output from the address control circuit 5,
Addresses 0 and 1 of memory 9 are designated.

On the other hand, the memory loading data is transferred from the data bus control circuit 3 to the swap circuit 11 via the gate circuit 10.
sent to. The swap circuit 11 uses the lowest bit of the address data output from the address control circuit 5).
If the LSB is 0'', data is not exchanged, and the upper byte is output to the output line lla, and the lower byte is output to the output line llb.As a result, the memory 9 has the lower byte at address 0 and the lower byte at address 11''' The upper byte data is written to the address.

Furthermore, when the address control circuit 5 outputs address data specifying an odd address, for example address 1, the addresses 1 and 2 of the memory 9 are specified as described above. Furthermore, when address data at an odd address is output from the address control circuit 5, its least significant bit LSB becomes '1#', the swap circuit 1 exchanges the upper byte of the input data with the lower pi)Th, and outputs the output line lla The data of the lower byte is output to the output line Ilb, and the data of the upper byte is output to the output line Ilb. As a result, the lower byte data is written into the memory 9 at address 1 and the upper byte data is written into address 2.

Next, an example of an instruction set for a byte/word microcomputer will be described. Figure 2 (
A) shows the basic word format: OP field (3 pits), regl field (2 pits), X2 field 1 pit, reg2 field (2 pits).
It consists of bits). As shown in FIG. 2(b), the operation code OP has eight types of instructions from "0OOJ to [1llJ." When the operation code OP is "o10J to "1llJ, each field is In other words, the regl field indicates the register address of the first operand.X2
The field indicates the addressing mode of the second operand. In this case, when X2-0, the contents of reg2 are used as the second operand, and when X2-1, regl is used as the index register, and the generated memory address is used as the second operand.

The reg2 field indicates the register number serving as the second operand.

So, if the above operation code is a 1-byte extension instruction of 000J, its format is as shown in Figure 3 (
As shown in a), the OP field (3 bits), op'
It consists of a field (3 bits) and a reg field (2 bits). Then, as the content of the OP' field changes from "000" to "1llJ", the third
The command is shown in Figure (b). Furthermore, if the content of the OP' field is "000J," the reg field is used as the OP' field as shown in FIG.
It has the meaning shown in .

In addition, in FIG. 2(a), the operation code O
When P is a 2-byte extended instruction of "001", its format is as shown in FIG. That is, 1
The byte is the OP field (3 bits), regl field (2 bits), X2 field (1 bit), r
It consists of the eg2 field (2 bits), and the second byte contains the X1 field (1 bit) and the function y
It consists of fields (7 bits). By putting an extended operation code, extended addressing mode, etc. in the second byte, for example, byte transfer instructions, arithmetic instructions such as EX-OR, pit test, transfer instructions between memories, indexes, relocation registers, etc. Constructs instructions such as subroutine branch instructions, wide range branch instructions, and segment change instructions.

Therefore, when the CPU executes an instruction read from the memory 9, the upper 8 bits of the instruction read from the memory 9 to the data bus DB via the swap circuit 13 and the data bus control circuit 3 are stored in the instruction register 4. Import into upper register. Then, the instruction/CPU control circuit 15 judges whether the instruction is a 1-byte alloy, and if it is a 1-byte instruction, the instruction is executed as is, but if it is not a 1-byte instruction, the lower 8 The bit is taken into a lower register in the instruction register 4, and the instruction decoder/CPU control circuit 15 decodes and executes the instruction. Furthermore, at the execution stage of the above instruction,
If the operand is 16 pits, 16 pits are taken into the instruction register 4 at the same time. If the operand is 8 bits, it is taken into the upper register in the instruction register 4 and processed.

By configuring it as in the above embodiment, the program becomes close to the size of an 8-bit architecture, and can be converted into a ROM, etc., and has unique data transfer and computing power of 16 bits. It turns out.

In the above example, the case where the implementation was performed on a 16-bit microcomputer was shown as 8 bits, 4 bits.
A certain bit I/) can also be implemented in a 32-bit microcomputer I/).

〔Effect of the invention〕

As described above, according to the present invention, the memory is configured with a unit length of 1/2 of one word, and two consecutive addresses can be arbitrarily specified. can be accessed as one word without being bound by word boundaries, so the operand can be set to 0 arbitrarily, and there are no restrictions on memory placement.

In addition, in the case of simple wisdom, an instruction can be configured with a capacity of 1/2 of one word, and therefore memory space can be used efficiently, and an alloy of 1/2 word can be executed. This can improve processing efficiency.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and FIG. 1 is a block diagram showing the circuit configuration, FIG. 2 is a block diagram showing the circuit configuration, FIG. The format diagrams (FIG. 2fb), FIG. 3(b), and FIG. 4(b) are diagrams showing the content of each instruction word. 1...Arithmetic unit, 2...CPU register, 3...
Data bus control circuit, 4... Instruction register, 5... Address control circuit, 6
, 7... Adder, 9... Memory, 10.14...
Gate circuit, 11.13... Swap circuit, 15...
・Instruction decoder/CPU control circuit.

Claims (1)

[Claims] In a microcomputer, a memory having a unit length of 1/2 word, an instruction storage means for storing instructions subsequently received from the memory, and a predetermined pit of 1/2 word of the instruction stored in the instruction storage means are provided. Decipher and follow this 1
/2 When it is determined that a word is necessary or not, the above 1/2 word is considered as one instruction, and when it is determined that the following 1/2 word is necessary, the following 1/2 word is written from the instruction storage means. A microcomputer comprising an instruction decoding means for reading the instruction and converting the instruction into an instruction having a length of one word.