JPS5896327A - Interface circuit - Google Patents

Abstract

PURPOSE:To obtain a device which operates stably, by outputting a gate signal from a control means, and allowing a coincidence detecting circuit to detect the coincidence between a data kind signal inputted from an external circuit and a selection signal outputted from the control means, etc. CONSTITUTION:A control means after outputting a selection signal outputs a gate signal, and a coincidence detecting circuit detects the coincidence between a data kind signal inputted from an external circuit and the selection signal outputted from the control means. For example, a data kind signal 7 and a selection signal 9 from a control circuit 5 are inputted to a coincidence detecting circuit 1, which once detecting their coincidence, sends a coincidence detection signal 11 to an AND gate 12. Then, the control circuit 5 outputs a gate signal 10 to a flip-flop 13, which then sends a synchronizing gate signal 14 to the AND gate 12. The AND gate 12 ANDs a data strobe signal 8, the coincidence detection signal 11, and synchronizing gate signal 14 to input an AND signals 12 to a register 3, thus storing data 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit, and more particularly, to an interface circuit that receives data between a microcomputer and an asynchronous external device.

FIG. 1 is a block diagram of an inter 7142 circuit which is the background of this invention, and FIG. 2 is a waveform diagram of each part of FIG. 1.

Next, the configuration and operation of a conventional interface circuit will be explained with reference to FIGS. 1 and 2. - The data type signal 7 and the control circuit 5 are input to the number output circuit 1 from the outside.
From this, the universal selection belief @9 is given. The data type signal 7 represents the type of data 6 input to the register 3, and the selection signal @9 output from the control circuit 5 is input to the register 6.
This is for selecting data given to . - The number output circuit 1 detects a match between the data type signal 7 and the selection signal @9, and if they match, provides a match detection signal 11 to the AND gate 2. A data strobe signal 8 and a gate signal 10 from the control circuit 5 are applied to the AND gate 2 from the outside. This gate signal @10 is derived after the selection signal 9 is output. AND gate 2 has data strobe signal 8, one output @11 and gate signal @1o
The output signal 12 is given to the register 3. The register 3 stores data 6 at the timing when the AND signal 12 is input. Data 6 stored in register 3 is given to register 4. Register 4 stores data 6 based on a signal given from control circuit 5. Note that the register 4 and the control circuit 5 are built in, for example, a microcomputer.

As mentioned above, in the conventional interface circuit, since the gate signal 1o outputted from the control circuit 5 and the data strobe signal 8 inputted from the outside are asynchronous,
In the ND gate 2, the timing of the data strobe signal 8 and the gate signal 1o may not be synchronized, and a signal with a very wide pulse width may be output, such as the AND signal 12' shown in FIG. . For this reason, the register 3 may not normally store data based on the AND signal @12'.

Therefore, the main object of the present invention is to provide an interface circuit which can eliminate the above-mentioned drawbacks and which can operate stably.

To summarize the invention, after outputting a selection signal from the control means, a gate signal is output, and a match between a data type signal inputted from the outside and a selection signal outputted from the control means is detected by a number output circuit. do.

Further, the gate signal outputted from the control means is stored in synchronization with the strobe signal inputted from the outside, and data is stored in the register based on this signal, the coincidence detection signal, and the strobe signal, thereby allowing the external The interface circuit is configured to synchronize the signal input from the ninth section with the interface circuit.

The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention. This FIG. 3 is the same as FIG. 1 except for the following points. That is, in order to synchronize the data strobe signal @ 8 and the gate signal 10, 7 rip 70 rip 1 is used as a state storage means.
3 is provided. When the flip 70 tube 13 receives the gate signal 10 from the control circuit 5, it stores the gate signal 10 at the timing of the fall of the data strobe signal 8. Then, the synchronous gate signal @14 is given to the AND gate 2.

FIG. 4 is a waveform diagram of each part of FIG. 3. Next, the specific operation of one embodiment of the present invention will be described with reference to FIGS. 3 and 4. - The number output circuit 1 provides a number output @11 to the AND gate 2 when the data type signal 7 and the selection signal 9 match. The control port l110 outputs the bale gate signal 10 which outputs the selection signal 9.
It is given to lip flop 13. The flip 70 tube 13 stores the gate signal 10 at the timing of the fall of the data strobe signal @8, and provides the synchronous gate signal 14 to the AND gate 2. The AND gate 2 performs the logical product of the data strobe signal 8, the coincidence detection signal 11, and the synchronization gate signal 14, and provides the logical product signal 12 to the register 3. The register 3 stores data 6 at the timing when the AND signal 12 is input.

In this way, the gate signal 10 is converted into the data strobe signal 8.
Even if the gate signal 10 falls during the period of the data strobe signal @8, the synchronous gate signal 14 is held until the next falling edge of the data strobe signal 8, so that the AND signal 12 will have the same pulse width as data strobe signal 8. Therefore, the AND signal 12 does not output the AND signal 12 with a narrow pulse width because the data strobe signal 8 and the gate signal 10 are not synchronized as in the conventional case. Therefore, data 6 is reliably stored in register 3.

As described above, according to the present invention, since the gate signal is synchronized with the strobe signal and used as a signal for storing data in the register, data can be reliably stored in the register.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an interface circuit that forms the background of this invention. FIG. 2 is a waveform diagram of each part of FIG. 1. FIG. 3 is a block diagram of one embodiment of the present invention. FIG. 4 is a waveform diagram of each part of FIG. 3. In the figure, 1 is a coincidence detection circuit, 2 is an AND gate, and 3
is a register, 5 is a control circuit, and 13 is a flip 70 tube. Agent Makoto Kuzuno - (1 other person) Figure 1 Figure 2 Gotoge Sho/2' 3rd/41st iAze Hinoki Arashi 2

Claims (1)

[Scope of Claims] An interface circuit that receives data, a strobe signal, and a data type signal representing the type of # data, and stores the data in a register if the data is desired data, comprising: a control means for outputting a selection signal for selecting data to be selected and a gate signal after outputting the selection signal; detecting coincidence between the data type signal and the selection signal and outputting a coincidence detection signal; a coincidence detecting means for storing the gate signal in synchronization with the strobe signal, and a state storing means for storing the gate signal in synchronization with the strobe signal, and storing the data in the register based on the minus number output signal, the state storing means output, and the strobe signal. An interface circuit with gate means for storing.