JPS5889869A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5889869A JPS5889869A JP56187631A JP18763181A JPS5889869A JP S5889869 A JPS5889869 A JP S5889869A JP 56187631 A JP56187631 A JP 56187631A JP 18763181 A JP18763181 A JP 18763181A JP S5889869 A JPS5889869 A JP S5889869A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- gate
- polysilicon
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 42
- 229920005591 polysilicon Polymers 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 abstract description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 14
- 238000005530 etching Methods 0.000 description 13
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 2
- 238000001444 catalytic combustion detection Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、２層ポリシリコン膜を有する半導体装置の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having a two-layer polysilicon film.
ＣＣＤや高密度のダイチミックメモリー、スタティック
メモリー等の高密度集積回路では、２層−ポリシリコン
ゲー）ＭＯ８構造“が川伝られている。In high-density integrated circuits such as CCDs, high-density dichroic memory, and static memory, the 2-layer polysilicon (MO8) structure is widely used.
これらの構造では、上記２つのポリシリコン導電膜の間
を絶縁する眉間絶縁膜を必要としている。These structures require a glabella insulating film that insulates between the two polysilicon conductive films.
高密度９寸法縮小化を指向するｖｔ、纏ｘの代表的な製
造工程では、この層間絶縁膜形歳には、例えば８ ’Ｋ
Ｉａ ＯＣ８（５ｅｌｅｃｔｉｖｅ ０ｘｉｄｅ Ｃ
ｏａｔｉｎｇ ｏｆＳｉｌｉｃｏｎ ｇａｔｅ の略称
）法が用いられている。この方法は被酸化シリコン表面
の不純物濃度の差によシ、酸化速度が異なることを利用
した膜厚の異なる酸化膜の同時形成線である。この５Ｋ
ＬＯＣ８法を用いて、第１のゲート電極となるポリシリ
コン膜止め酸化膜（層間絶縁膜）と、基板シリコン表面
に設け゛る第２のゲート酸化膜とを同時に形成する。ポ
リシリコン上と基板シリコンの部分で不純物濃度が異な
る。例えばポリシリコンのリン濃度１０” ｏｆ’ 、
基板ｆ）ｙｊ−ｆｙ素濃度１ｏ１６ａＩｒｓトスると
、９００℃で約ｉ倍、８００’Ｃで４倍、ポリシリコン
上の方が酸化速度が速い。しかし１０００°Ｃ以上では
酸化速度の差はなくなる。この方法が２層ポリシリコン
ゲー）ＭＯ８構造を有するＶＬＳＩデバイスのポリシリ
コン膜電極間の容量を低減できかつデバイスの性能を向
上できる製造工程として用いられることが知られている
。In the typical manufacturing process of VT, which aims for high-density 9-dimensional reduction, the interlayer insulating film shape is, for example, 8'K.
Ia OC8 (5elective Oxide C
A method (abbreviation for oating of Silicon gate) is used. This method utilizes the fact that oxidation rates differ due to differences in impurity concentration on the silicon surface to be oxidized, and oxide films of different thicknesses are simultaneously formed. This 5K
Using the LOC8 method, a polysilicon film stopper oxide film (interlayer insulating film) that will become the first gate electrode and a second gate oxide film provided on the silicon substrate surface are simultaneously formed. The impurity concentration differs between the polysilicon layer and the substrate silicon layer. For example, the phosphorus concentration of polysilicon is 10''of',
When the substrate f) yj-fy elemental concentration is 1o16aIrs, the oxidation rate on polysilicon is about i times faster at 900°C and 4 times faster at 800'C. However, above 1000°C, the difference in oxidation rate disappears. It is known that this method can be used as a manufacturing process that can reduce the capacitance between polysilicon membrane electrodes of a VLSI device having a two-layer polysilicon MO8 structure and improve the performance of the device.
以下従来例を第１図に従って説明する。Ｐ型（１００）
１２Ω−１の基板１上に５００人の第１の酸化膜２を形
成し、この上に、リンをドープした（不純物濃度１０２
０ｃｌＩｒ３）第１の所すシリコン膜３を４０００人の
厚さに被着し、ついで、間膜３をフォトエツチングによ
りゲート部だけ残す。A conventional example will be explained below with reference to FIG. P type (100)
A first oxide film 2 of 500 layers was formed on a substrate 1 of 12Ω-1, and phosphorus was doped thereon (impurity concentration 102
0clIr3) A first silicon film 3 is deposited to a thickness of 4,000 mm, and then the interlayer film 3 is photo-etched to leave only the gate portion.
次にＮＨ４Ｆ ： ＨＦ ＝ ５ ： １のエツチング
液で、上記第１のゲートポリシリコン膜３直下の酸化膜
２のみを残し、それ以外の酸化膜をエツチング除去する
（第１図（ａ））。９００’Ｃ水蒸気圏内で酸化して、
１０００人の層間絶縁膜４と、５００人の第２ゲート酸
化膜４′とを形成する。（第１図φ））そして、さらに
、リン−をドープした第２のポリシリコン膜６を上記層
間絶縁膜４および第２ゲート酸化４′上に被着して第１
ゲート電極３第２ゲート電極６の２層ゲート構造に形成
する。（１図（Ｃ））従来法の問題点は破線で囲った部
分６で示した層間絶縁膜のくびれ構造にある。このくび
れ部分６は第１のゲートポリシリコン電極膜３をマスク
として、第１ゲート領域以外の酸化膜２のエツチング除
去の際、第１ポリシリコンゲート３直下へのエツチング
の入シ込みがある″こと及びＳ Ｘ Ｌ ＯＣ８４によ
る第１のゲートポリシリコン膜３のエッジエの反り上り
により、第１図で示すように、このポリシリコン膜３の
先端側壁の下方部分で、層間絶縁膜４が極端に薄くなっ
てくびれを生じ、それが絶縁耐圧の低下、さらにひどい
場合にはピンホールの発生による絶縁劣化を起すことが
あった。Next, using an etching solution of NH4F:HF=5:1, only the oxide film 2 directly under the first gate polysilicon film 3 is left, and the other oxide films are removed by etching (FIG. 1(a)). Oxidizes in a 900'C water vapor sphere,
An interlayer insulating film 4 of 1000 layers and a second gate oxide film 4' of 500 layers are formed. (FIG. 1φ)) Then, a second polysilicon film 6 doped with phosphorus is deposited on the interlayer insulating film 4 and the second gate oxide 4', and the first
A gate electrode 3 and a second gate electrode 6 are formed in a two-layer gate structure. (FIG. 1(C)) The problem with the conventional method lies in the constricted structure of the interlayer insulating film shown by the portion 6 surrounded by a broken line. This constricted portion 6 is caused by etching intrusion directly under the first polysilicon gate 3 when the oxide film 2 in areas other than the first gate region is removed by etching using the first gate polysilicon electrode film 3 as a mask. As a result of this and the warpage of the edge of the first gate polysilicon film 3 due to the S The thinning caused constrictions, which lowered the dielectric strength and, in worse cases, caused pinholes to form, leading to insulation deterioration.
本発明の目的はこの欠点を解決する手攻を提供すること
である。本発明は上記ポリシリコンエツジ部酸化の際に
同時に形成される基板シリコンの酸化膜成長の影響で層
間絶縁膜にくびれのできることをできるだけ避けるため
、第１ゲート領域直下以外の酸化膜をも残したまま、第
１のゲートポリシリコン膜を酸化して、比較的厚い酸化
膜を形成した後、全面をエツチングし、第２の素子を形
成する活性領域上の第１の酸化膜をエツチング除去する
。このエツチングでは、ポリシリコン膜上と、それ以外
の部分の酸化膜厚の差が大きいので、第１の酸化膜を丁
度除去できるエツチング条件にしておけば、第１のゲー
ト部）ノシリコン膜上には十分な厚さの酸化膜を残すよ
うにエツチングできる。実験によると、ドープしたポリ
シリコン上に形成した熱酸化膜と基板シリコン上に形成
した熱酸化膜との各エツチング速度は、バッフアートフ
ッ酸液（ＮＨ４Ｆ：ＨＦ−＝６＝１）ノ液温２０’Ｃに
おいて、ポリシリコン上熱酸化膜で、９７０人／分。The aim of the invention is to provide a strategy to overcome this drawback. In the present invention, in order to avoid as much as possible the formation of constrictions in the interlayer insulating film due to the influence of the growth of the oxide film on the substrate silicon, which is simultaneously formed during the polysilicon edge oxidation, the oxide film is left in areas other than directly under the first gate region. After that, the first gate polysilicon film is oxidized to form a relatively thick oxide film, and then the entire surface is etched to remove the first oxide film on the active region where the second element is to be formed. In this etching, there is a large difference in the thickness of the oxide film on the polysilicon film and on the other parts, so if the etching conditions are set to just remove the first oxide film, the thickness of the oxide film on the polysilicon film (on the first gate part) will be removed. can be etched to leave a sufficiently thick oxide film. According to experiments, the etching rates of a thermal oxide film formed on doped polysilicon and a thermal oxide film formed on a substrate silicon depend on the solution temperature of a buffered hydrofluoric acid solution (NH4F:HF-=6=1). At 20'C, thermal oxide film on polysilicon, 970 people/min.
基板シリコン上で９６０人／分であり、顕著なエツチン
グ速度の差は認められなかった。このことから所望の膜
ｐ１のポリシリコン上の酸化膜を残して、基板シリコン
上酸化膜を完全に除去することが可能でああという事実
が得られた。次に第２ゲーム酸化膜および層間絶縁膜を
形成することによって、第１ポリシリ−コンのひさしに
よる影響を少なくすることができる。また−第１ポリシ
リコン膜先端部で酸化膜を残して酸化することによシ、
酸化種（Ｈ２Ｏ）の基板シリコン面への拡散をおさえ、
基板シリコンの酸化を制限して、上記第１ポリシリコン
膜先端部での同ポリシリコンの反り上りを減少するとい
う効果力「ある。以下本発明の実施例について説明する
。The etching rate was 960 etching per minute on the silicon substrate, and no significant difference in etching rate was observed. This has led to the fact that it is possible to completely remove the oxide film on the silicon substrate, leaving the oxide film on the polysilicon of the desired film p1. Next, by forming a second game oxide film and an interlayer insulating film, the influence of the first polysilicon canopy can be reduced. Furthermore, by oxidizing the first polysilicon film while leaving an oxide film at the tip,
Suppresses the diffusion of oxidizing species (H2O) to the silicon surface of the substrate,
There is an effect of limiting the oxidation of the silicon substrate and reducing the warpage of the polysilicon at the tip of the first polysilicon film.Examples of the present invention will be described below.
（実施例１）
第２（ｆｆｌ（ＩＬ）〜（１５）に製造工程順での半導
体装置の断面図を示す。たとえばＰ型（１００）１２Ω
−α基板１に第１ゲート酸化膜２をＳＯＯ人の厚さに形
成し、リンをドープした（不純物濃度１０”ＣＩｒ’）
−第１のゲートポリシリコン膜３を設は兎（第２図（
ａ））。ツＩ／１で、８００℃、Ｈ２： ０２ ＝ １
．８ ： １．０で、水蒸気圏内で酸化し、酸化膜４を
形成する。(Example 1) Sections 2 (ffl (IL) to (15)) show cross-sectional views of semiconductor devices in the order of manufacturing steps. For example, P type (100) 12Ω
-A first gate oxide film 2 was formed on the α substrate 1 to a thickness of SOO and doped with phosphorus (impurity concentration 10"CIr')
- The first gate polysilicon film 3 is formed (see Fig. 2).
a)). At TS I/1, 800℃, H2: 02 = 1
．． 8: At 1.0, it is oxidized in a water vapor atmosphere and an oxide film 4 is formed.
この場合、酸化膜厚は上記ポリシリコン膜３土で、１７
００人、それ以外で１ｏｏｏ人である（第２図（ｂ））
。このとき、望ましい条件としては、ポリシリコン上に
酸化膜を残して、エツチングしなければならないため、
ｆきるだけこの酸化膜厚の差は大きい方が良い。次にｎ
Ｊ ： ＨＦ ＝ ５ ： １のエツチング液で酸化膜
４をエツチングし、ポリシリコン上のみ酸化膜４を約６
ｏｏ人の厚みに残す（第２図（Ｃ））。この場合、酸化
膜のエツチング速度は、前述のように、ポリシリコン上
あるいは。In this case, the oxide film thickness is the above polysilicon film 3, 17
00 people, and 1ooo other people (Figure 2 (b))
. At this time, the desirable conditions are that the oxide film must be left on the polysilicon and etched.
It is better that the difference in oxide film thickness is as large as f. Then n
Etch the oxide film 4 with an etching solution of J: HF = 5:1, and remove the oxide film 4 only on the polysilicon to a thickness of about 6
Leave it to the thickness of oo person (Figure 2 (C)). In this case, the etching rate of the oxide film is higher than that on polysilicon or on polysilicon, as described above.
それ以外でも変わらない。９００’Ｃ、Ｈ２： ０２−
１、ａ ： １．Ｏで水蒸気圏内で酸化し、５００人の
第２ゲート酸化膜４′と、１６００人の層間絶縁膜４と
を同時に形成する（第２図（ｄ））。さらに、第２のゲ
ートポリシリコン膜５を４０００人の厚さに形成する（
第２図（ｅ））。第１図、第２図を化量してわかるよう
に、第１図で示したような層間絶縁膜４のくびれ部分６
は第２図示の本実施例では観測されない。Other than that, it doesn't change. 900'C, H2: 02-
1, a: 1. It is oxidized with O in a water vapor atmosphere to form a second gate oxide film 4' of 500 layers and an interlayer insulating film 4 of 1600 layers at the same time (FIG. 2(d)). Furthermore, a second gate polysilicon film 5 is formed to a thickness of 4000 nm (
Figure 2(e)). As can be seen by quantifying FIGS. 1 and 2, the constriction 6 of the interlayer insulating film 4 as shown in FIG.
is not observed in this embodiment shown in the second figure.
（実施例２）
層間絶縁膜の酸化条件としては、前述の如く一１ｏＯｏ
′Ｃ以上では１ｓＫＬＯＯ８法テノ酸化膜成長速度に顕
著な差がなくなるために一１０００℃以度比の大きい、
実用的な温度範囲７５０〜８６０°Ｃが適切である。な
お、さきに示したようにポリシリコン上とそれ以外の部
分での酸化膜厚の差は大きくとらなければならない。プ
ロセスに余裕をもつためには酸化膜厚の差の大きいより
低温及び高水蒸気圧の条件が必要である。しかし低温に
なればなるほど成長速度がともに低下するので、酸化に
時間を要し実際的ではない。そのため高圧酸化法による
酸化を用い、少なくとも、その条件設定のための時間を
含めても３時間以内に所望の酸化膜が得られるようにし
た。(Example 2) The oxidation conditions for the interlayer insulating film were as described above.
Since there is no significant difference in the growth rate of the teno oxide film using the 1s KLOO8 method at temperatures above 1000°C,
A practical temperature range of 750-860°C is suitable. As shown above, the difference in oxide film thickness between the polysilicon layer and the other portions must be large. In order to have margin in the process, conditions of lower temperature and higher water vapor pressure with a larger difference in oxide film thickness are required. However, as the temperature decreases, the growth rate also decreases, and oxidation takes time, which is impractical. Therefore, oxidation by high-pressure oxidation was used so that the desired oxide film could be obtained within at least three hours, including the time for setting the conditions.
、本実施例では、第２図（ＩＬ）〜（・）において、第
２図（ａ）は実施例１と同様にし、そ、の後の各工程に
したがい、まず、７５０’Ｃにおいて、水蒸気圧３．７
３ｋｑ／ｃｄの気圏内でポリシリコン膜３上に２６００
人、それ以外のところは１ｏｏＯ人の酸化膜４を形成す
る（第２図（ｂ））。次にＮＨａＦ： ＨＦ ＝５：１
のエツチング液で酸化膜４をエツチングし、ポリシリコ
ン膜３上に約１４００人の酸化膜を残す（第２図（Ｃ）
）。以下実施例１と同様にして、第２９べ一１′
ゲート酸化膜４′および厚い層間絶縁膜４を同時に形成
する（第２図（＋１） 、 （ｅ） ）。ここで層間絶
縁膜４は２４００人である。なお、ここでは一部の酸化
工程に高圧酸化法を用いた摂、時間が許せば、全ての酸
化工程に用いても同様の効果が得られる。In this example, in FIGS. 2 (IL) to (・), FIG. Pressure 3.7
2600 on the polysilicon film 3 in the atmosphere of 3kq/cd
In the other areas, an oxide film 4 of 100 people is formed (FIG. 2(b)). Next, NHaF: HF = 5:1
The oxide film 4 is etched with an etching solution of about 1,400 mm, leaving an oxide film of about 1,400 layers on the polysilicon film 3 (Fig. 2 (C)).
). Thereafter, in the same manner as in Example 1, a gate oxide film 4' and a thick interlayer insulating film 4 are simultaneously formed on the 29th base 1' (FIGS. 2(+1) and (e)). Here, the thickness of the interlayer insulating film 4 is 2400. Note that although high-pressure oxidation is used for some of the oxidation steps here, the same effect can be obtained by using it for all of the oxidation steps if time permits.
本発明の上述の各実施例で得た半導体装置について、次
のような効果確認実験を行った０従来の５ｘＬｏｃｓ法
を用いた第１図（１１）構造と本発明の工程に従って製
造した第２図−（６）の構造の測定試料ウエノ・をそれ
ぞれ３スライスずつ作った。The following effect confirmation experiments were conducted on the semiconductor devices obtained in each of the above-described embodiments of the present invention. Three slices of each measurement sample Ueno having the structure shown in Figure-(6) were prepared.
このウェハは１−２０チツプを含み、チップ中に上記構
造のものが４０００個存在する。耐圧測定は各条件３ス
ライスから１０チツプずつをまんべんなく選び（計３０
点）、第１．第２ポリシリコンゲート電極間に電圧をか
けて、リーク電流が１μムに′なったときめ電圧値を耐
圧とした。また平均良品率は第１．第２ポリシリコンゲ
ート°電極間に±、１６ｖの電圧をかけて、リーク電流
が±１０ｎム以下のものを良品としてとり、各３スライ
ス、１２０チツプ測定によシ求めた。下表かられかる１
０１・−
ように本廃明の方法によるものは、従来法に比べて、耐
圧値のバラツキの減少が明らかであり、ＶＬＳＩ製造工
程へ応用して大きな効果を発揮できる。なお本発明実施
例ではポリシリコンゲートを用いたが、ＭｏＳｉ ゲ
ートないしは、高融点金属硅化物を用いても良い。This wafer contains 1-20 chips, and there are 4000 of the above structures in the chip. For pressure resistance measurements, 10 chips were evenly selected from 3 slices for each condition (30 chips in total).
point), 1st. A voltage was applied between the second polysilicon gate electrodes, and the voltage value when the leakage current reached 1 μm was determined as the withstand voltage. Also, the average non-defective product rate is 1st. A voltage of ±16 V was applied between the second polysilicon gate and the electrodes, and those with a leakage current of ±10 nm or less were considered good, and the measurements were performed on 3 slices each and 120 chips. Recipe 1 from the table below
01.-, the method according to the present invention clearly reduces the variation in breakdown voltage value compared to the conventional method, and can be applied to the VLSI manufacturing process with great effect. Although a polysilicon gate is used in the embodiment of the present invention, a MoSi gate or a high melting point metal silicide may also be used.
以上から本発明はＣＣＤ、メモリー等の２層ポリシリコ
ンゲート構造を用いたデバイスの歩留向上に大きく寄与
することがわかる。From the above, it can be seen that the present invention greatly contributes to improving the yield of devices using a two-layer polysilicon gate structure such as CCDs and memories.
第１図（！Ｌ）〜（Ｃ）は従来例の断面図、第２図（ａ
） 〜（６）は本発明の一実施例を説明するための半導
体装置の断面図である。
１・・・・・・Ｐ型（１００）１２Ω−１シリコン基板
、２・・・・・・第１ゲート酸化膜、３・・・・・・第
１のゲートポリシリコン膜、４・・・・・・層間絶縁膜
、第２ゲート酸化膜、６・・・・・・第２のゲートポリ
シリコン膜、６・・・・・・層間絶縁膜のくびれ。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
１２図Figures 1 (!L) to (C) are cross-sectional views of the conventional example, and Figure 2 (a)
) to (6) are cross-sectional views of a semiconductor device for explaining one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type (100) 12Ω-1 silicon substrate, 2... First gate oxide film, 3... First gate polysilicon film, 4... ... interlayer insulating film, second gate oxide film, 6 ... second gate polysilicon film, 6 ... constriction of interlayer insulating film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 12
Claims (2)
上に不純物をドープしたポリシリコンあるいは高融点金
属硅化物から成る膜を第１ゲート電極に選択形成する工
程と、前記第１の絶縁膜を残置して、１０００℃未満の
温度で熱酸化膜を上記第１ゲート電極上および上記第１
の絶縁膜上に形成する第１酸化工程と、前記残置した第
１の絶縁膜の所定領域の基板シリ゛コン面を露出して後
、この露出したシリコン基板面にふたた〜び第２の絶縁
膜を形成する第２酸化工程と、第２のゲート電極膜を被
！形成する工程とを含むことを特徴とする半導体装置の
製造方法。(1) A step of selectively forming a film made of impurity-doped polysilicon or high melting point metal silicide as a first gate electrode on a first insulating film formed on the entire surface of a silicon substrate; A thermal oxide film is formed on the first gate electrode and the first gate electrode at a temperature of less than 1000° C., leaving an insulating film of
After the first oxidation step of forming on the insulating film and exposing the silicon surface of the substrate in a predetermined region of the remaining first insulating film, a second oxidation step is again performed on the exposed silicon substrate surface. A second oxidation step to form an insulating film and a second gate electrode film! 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.
る特許請求範囲第１項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the oxidation is performed in a high-pressure oxidizing atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56187631A JPS5889869A (en) | 1981-11-20 | 1981-11-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56187631A JPS5889869A (en) | 1981-11-20 | 1981-11-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5889869A true JPS5889869A (en) | 1983-05-28 |
| JPS6312389B2 JPS6312389B2 (en) | 1988-03-18 |
Family
ID=16209485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56187631A Granted JPS5889869A (en) | 1981-11-20 | 1981-11-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5889869A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60198855A (en) * | 1984-03-23 | 1985-10-08 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JPS615574A (en) * | 1984-06-20 | 1986-01-11 | Hitachi Micro Comput Eng Ltd | Manufacture of semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5394780A (en) * | 1977-01-14 | 1978-08-19 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS558062A (en) * | 1978-07-03 | 1980-01-21 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor |
| JPS5559778A (en) * | 1978-10-30 | 1980-05-06 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method of fabricating semiconductor device |
-
1981
- 1981-11-20 JP JP56187631A patent/JPS5889869A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5394780A (en) * | 1977-01-14 | 1978-08-19 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS558062A (en) * | 1978-07-03 | 1980-01-21 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor |
| JPS5559778A (en) * | 1978-10-30 | 1980-05-06 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method of fabricating semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60198855A (en) * | 1984-03-23 | 1985-10-08 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JPS615574A (en) * | 1984-06-20 | 1986-01-11 | Hitachi Micro Comput Eng Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6312389B2 (en) | 1988-03-18 |
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