JPS5889851A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5889851A
JPS5889851A JP56187018A JP18701881A JPS5889851A JP S5889851 A JPS5889851 A JP S5889851A JP 56187018 A JP56187018 A JP 56187018A JP 18701881 A JP18701881 A JP 18701881A JP S5889851 A JPS5889851 A JP S5889851A
Authority
JP
Japan
Prior art keywords
wire
cost
materials
quality
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56187018A
Other languages
Japanese (ja)
Inventor
Hisashi Yoshida
吉田　恒
Susumu Okikawa
進 沖川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP56187018A priority Critical patent/JPS5889851A/en
Publication of JPS5889851A publication Critical patent/JPS5889851A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To reduce the cost of a material by partially replacing a noble metal wire as a connecting wire between an element and a lead with a base metal wire. CONSTITUTION:A signal wire 12a between the connecting wires 12 is an Au wire and a power wire 12b is an Al wire. Accordingly, the cost of the device can be reduced without damaging reliability as a whole by forming one part of the connecting wires, particularly, a wire which is difficult to be disconnected or corroded, by the low-cost material except the noble metals. When the surface of the element 11 is downward directed without using connecting wires and connected to leads 13 through bumps 15, it is also though that the quality of materials of several kinds is used while balancing reliability and cost in consideration of the quality of materials to be attached without limiting the quality of materials of the bumps to one kind.

Description

【発明の詳細な説明】 本発明は１貴金属を図った半導体装置に関する〇一般Ｋ
ＭＰ導体義装としてはダイオード・トランジスタ及びＩ
Ｃ更には計測器・カメラ等個々の特種用途剛の半導体装
置があるが、一般的にはこれらの構造は第１＠にＩＣの
断面図で示す如く、半導体素子（チップ）１と［ｆｌｌ
ＩＩ２とリード３とレジン４等より成る。この場合、Ｉ
［Ｉ絖ｌＩ２の接続方法は熱圧着・超音波ボンディング
及び抵抗熔Ｉ［ＩＩＩＩＩ各糧の方法が採用される。[Detailed Description of the Invention] The present invention relates to a semiconductor device using a noble metal.
MP conductor devices include diodes, transistors and I
C Furthermore, there are semiconductor devices for individual special purposes such as measuring instruments and cameras, but generally, these structures consist of a semiconductor element (chip) 1 and [fll
Consists of II2, lead 3, resin 4, etc. In this case, I
[The method of connecting the wires is thermocompression bonding, ultrasonic bonding, and resistance welding.

ところで、このようなＩＣＥ於いては接続線２は過ｍｎ
本（ｎ−５〜１００本）あるが、その曽はすべて同一の
材質のもめを使用している。例えば熱圧看法によるボン
ディングではＡｕ＠、Ａｕ合金線及びＡＪ締、超音波を
使用するボン、ディングではυ線、その合金線及びＣ−
ｕ＠、抵抗溶接法によるボンディングではＡｕ１ｉ及び
その合金線。By the way, in such an ICE, the connection line 2 is
There are 5 to 100 books, all of which are made of the same material. For example, in bonding by thermo-pressure observation, Au@, Au alloy wire and AJ tightening, in bonding using ultrasonic waves, υ wire, its alloy wire and C-
u@, Au1i and its alloy wire for bonding by resistance welding method.

Ａｇａ及びその合金線、す線ｐｃｕｌｌｉ等である・こ
のため、接続線にＡｕ１ｉ等の貴金属を使用したもので
は、近年のように貴金属（Ａｕ、　Ａｇ、　ｐｔ）の価
格が暴騰しまた今後も価上りが予想される場合、全ての
接続線を同一材質にするのは材料コストの面で問題があ
る。Aga and its alloy wires, pculli wires, etc. For this reason, the prices of precious metals (Au, Ag, PT) have skyrocketed in recent years and will continue to rise in connection wires that use precious metals such as Au1i. If uplinks are expected, using the same material for all connection lines poses a problem in terms of material cost.

このため、接続ｌＩを貴金属−から非金属ｌＩＫ全部変
更することが考えられる。しかしながら、比較的細い線
の場合長期間使用によりレジンと線が反応し腐蝕したり
、温度サイクル試験により締が引っ張られ断線したりす
る場合があり貴金属（Ａｕ。For this reason, it is conceivable to change the connection lI from a noble metal to a non-metal lIK. However, in the case of relatively thin wires, the resin and wire may react with each other and corrode after long-term use, or the wires may break due to tension during temperature cycle tests.

Ａｇ）の如く腐蝕に強く且つ延性のある材質のものをど
うしても使用せざるを得ない場合がある。There are cases where it is necessary to use a material that is resistant to corrosion and ductile, such as Ag).

したがって、本発明の目的は牛導体装置の信頼性な低下
することなく接続線の材料コストを低減して完成品のコ
ストを従来品に比べ低コストにすることができる半導体
装置を提供することにある。Therefore, an object of the present invention is to provide a semiconductor device that can reduce the material cost of connecting wires without deteriorating the reliability of the conductor device, thereby making the cost of the finished product lower than that of conventional products. be.

以下、本発明を図示の実施例によりａＩｊ！する。Hereinafter, the present invention will be explained with reference to the illustrated embodiments. do.

第２図に本発明の一例としての°半導体の構造要部拡大
図を示す。この装置はパワーＩＣ’についての例であり
、１１は半導体素子（通称ベレット）、１２は飯１Ｒ１
ｉＩ、１３はリードフレーム、１４はモールドレジンで
ある。FIG. 2 shows an enlarged view of the main structure of a semiconductor as an example of the present invention. This device is an example of a power IC', 11 is a semiconductor element (commonly known as a pellet), 12 is a rice 1R1
iI, 13 is a lead frame, and 14 is a mold resin.

この場合接続１１１２のうち傷４１１１２ｍとパワー纏
１２ｂは太さが異なるが同時に材質を変えている。In this case, among the connections 1112, the scratch 41112m and the power wrap 12b have different thicknesses, but they are also made of different materials.

即ち係号！１ｉ１１２ａはＡｕ　１１％パワー纏１２ｂ
はリ一である。In other words, the number! 1i112a is Au 11% power wrapped 12b
is the first.

半導体素子をリードフレームＫｉｌ定する方法は合金、
＊脂接着、ソルダ（ろう付）勢各種ある。The method for determining the lead frame of semiconductor elements is alloy,
*Various types of adhesive and solder (brazing) are available.

またＩＩ続＠１２を、接続する方法も熱圧着、麺音波熔
接、抵抗熔接等舎種ある。また封止材もレジン封止以外
にセラミックやガラス剤止勢がある。There are also various methods for connecting the II connection @12, such as thermocompression bonding, sonic welding, and resistance welding. In addition to resin sealing materials, there are also ceramic and glass sealing materials.

このように接続線の＝部、特に断線したり腐蝕され難い
締を貴金属以外の低コスト材料にて構成することにより
、全体として信頼性を損わないで装置の低コスト化を連
成できる。この場合、接続線を２種類以上とすることに
より接続作業は別機械を行わねばならないがトータルコ
ストとして１ａｎよりも低減される。In this way, by constructing the = section of the connecting wire, especially the fasteners that are not easily broken or corroded, from a low-cost material other than precious metals, it is possible to reduce the cost of the device without sacrificing overall reliability. In this case, by using two or more types of connection wires, the connection work must be performed using a separate machine, but the total cost is lower than 1an.

ここで、本発明は主に貴金属線を１部非貴金属線に置き
換え材料コスト低減を計ることであるが、逆に信頼性の
面から従来非金属一種類で接続ＩＩを使用していたもの
を４９に腐蝕し易いところ又番１断線し易いところをし
―い材質である貴金属−を使用し信頼性を向上させる目
的で使用することも出来る。Here, the present invention is mainly aimed at reducing material costs by replacing some of the noble metal wires with non-noble metal wires, but conversely, from the viewpoint of reliability, the connection II, which conventionally used only one type of non-metal, has been replaced with a non-noble metal wire. It is also possible to use noble metal, which is a material that protects the parts that are easily corroded and the parts that are easily broken, for the purpose of improving reliability.

また、前記説明は接続線を接続する場合について説明し
たが半導体装置のある構造のものは第３図に示す如（素
子１１にバンプ１５と称して接続線に代る央起を有して
おり、接続線を使わずに素子１１の面を下にしバンプ１
５を弄してリード１３と接続するものもめる。この場合
もパンツの材質をｌｓ類とせず、付けるべき相手方の材
質Ｖ考九傷麺性とコストをバラン子を取り数種蒙の材質
にすることが考えられる。In addition, although the above description has been made regarding the case where connection lines are connected, a semiconductor device with a certain structure has a central part called a bump 15 on the element 11 in place of the connection line, as shown in FIG. , without using connection wires, place element 11 face down and bump 1.
Play around with 5 and find the one that connects to lead 13. In this case as well, instead of using the same material as the pants, it is conceivable to consider the material of the other party to be attached, take into consideration the fragility and cost, and use several different materials.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の断面図、°第２図は本発明装置の断面図
、第３１！１は変彫例の断面図である。 １．１１・・・素子、２，１２・・・ｔａ纏、３，１３
・・・リード、４，１４・・・レジン、１５・・・）（
ンッ。 第　　１　　図 第　　２　　図 ／２ 第　　３ｔ！２１Fig. 1 is a sectional view of a conventional device, Fig. 2 is a sectional view of the device of the present invention, and Fig. 31!1 is a sectional view of a modified example. 1.11...Element, 2,12...TA wrap, 3,13
...Reed, 4,14...Resin, 15...)(
Hmm. Figure 1 Figure 2/2 3rd t! 21

Claims (1)

【特許請求の範囲】[Claims] １、素子とリードとを襞ＩＩＲ−にて接続を行なう半導
体装置において、前記接続線に２種線上の材質の線材を
使用したことを特徴とする半導体装置。1. A semiconductor device in which an element and a lead are connected by a fold IIR-, characterized in that a wire made of a material similar to that of a type 2 wire is used for the connection line.
JP56187018A 1981-11-24 1981-11-24 Semiconductor device Pending JPS5889851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56187018A JPS5889851A (en) 1981-11-24 1981-11-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56187018A JPS5889851A (en) 1981-11-24 1981-11-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5889851A true JPS5889851A (en) 1983-05-28

Family

ID=16198752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56187018A Pending JPS5889851A (en) 1981-11-24 1981-11-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5889851A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093281A (en) * 1988-07-13 1992-03-03 Mitsubishi Denki Kabushiki Kaisha method for manufacturing semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093281A (en) * 1988-07-13 1992-03-03 Mitsubishi Denki Kabushiki Kaisha method for manufacturing semiconductor devices

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