JPS588623B2 - A communications device that transmits two independently timed binary data signals on a single four-phase modulated carrier wave. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to communication devices, and more particularly to methods and apparatus for transmitting and receiving two independently timed PCM (Pulse Code Modulation) signals carried on a single four-phase modulated carrier.

Four-phase modulation techniques also include four-phase shift keying, QPSK,
Also known as 4-phase modulation, 4-level phase modulation, and 4-phase modulation.

As commonly implemented, the input to the four-phase modulator is either two synchronized bit streams or a single continuous bit stream that is decomposed into two parallel bit streams prior to carrier modulation.

The timing of the synchronous bit streams must be generated by the same oscillator or phase-locked oscillators and must coincide when bit stream state transitions occur.

In a four-phase modulator, the receiver can detect the phase shift due to the modulation, but the absolute phase state cannot be measured unless a transmitted phase reference is also provided.

A transmitted phase reference requires additional power and is generally not used.

Receivers are typically designed to operate on the available information in the received signal to closely demodulate and recreate the original POM bit stream.

In the case of a synchronous four-phase device, there are four possible PCM signal states, e.g. 00, 01, 10, 11, with no change for 00, +90° change for 01, -90° change for 10, 11 Accurate signal reproduction is achieved by digitally encoding carrier phase changes of 180° relative to the signal.

Since carrier phase changes are uniquely detectable, the receiver decodes exactly the original PCM signal state.

This type of encoding is known as four-difference encoding.

However, this type of encoding is not possible for asynchronous PCM input signals.

An early patent directed to a conventional four-phase modulator with synchronous inputs was D.F. Babcock's U.S. Patent No. 2,87.
No. 0,431 and No. 2,905 of M. L. Doerts et al.
, No. 812.

U.S. Patent No. 3,242,262 to C.M. Melas et al.
No. 4, a four-phase modulator is disclosed which applies two separate and unrelated channels of information as an example. The recognition of the two original channels is effected by the use of known preambles.

Continuous identification is not performed. Another four-phase modulation method with an asynchronous data input is discussed in an article by Lucio M. Barresa in the August 1971 issue of Microwave, page 10.

No device is disclosed that performs strict recognition of asynchronous channels.

The parent application, Ser. No. 225,823, filed February 14, 1972, discloses an asynchronous four-phase communication apparatus for processing mutually asynchronous input signals having known characteristics such as frame bits. .

The PN scrambling sequence obscures the frame bits if the received channel falls into the wrong sequence.

In another embodiment, mutually asynchronous input signals having no known characteristics are processed by applying low index frequency modulation to each channel's clock.

According to the teachings of the present invention, two mutually asynchronous PCs with exact recognition and reproduction of the original PCM transmitter input channel
A new and improved method and apparatus for four-phase transmission of M signals is provided, where the PCM input signal does not need to have known characteristics.

This method, referred to as asynchronous 4-phase, processes the data before transmission.
Uniquely identifies one of the channels.

The receiver looks for this unique symbol and thereby identifies the channel.

The device encoder receives the PCM signal, performs conditioning, scrambling (optional), channel identification, differential encoding operations on the data, and outputs a data stream suitable for driving a phase modulator.

Two independently timed PCMs with the same nominal bit rate
sources are processed simultaneously by the encoder.

Also included within the encoder is equipment for internally generating data suitable for equipment testing.

The input to the encoder consists of two mutually asynchronous bipolar PCM data streams designated as channels A and B.

Each channel of data undergoes signal processing consisting of timing extraction, data scrambling, and differential encoding operations.

In addition, channel A data is processed such that it is uniquely identified by the receiving circuitry and is well differentiated from channel B data.

This additional processing consists of slightly increasing the clock speed of the A channel using a frequency translation loop.

Circuitry in the receiver distinguishes between A and B channels based on their respective frequencies.

Another receiver circuit reduces the modified A channel rate by the same constant ratio to restore the original rate.

The input data is changed from bipolar to return to zero (RZ) signal type.

The RZ bit stream drives a ringing filter, which is a high Q resonant circuit tuned to the clock frequency.

The purpose of the ringing filter is to selectively extract the clock frequency from the input signal spectrum.

The ringing filter output is sent to a phase locked loop (PLL) which locks to the clock frequency to generate a structured clock for use in subsequent processing circuitry.

The clock obtained from the PLL returns the RZ data to non-zero (NR
Z) Drive a flip-flop that converts to data.

In normal operation, the NRZ data and its associated clock are connected to a data scrambler.

The scrambling operation is performed modulo 2 by adding the NRZ data to an internally generated pseudo-noise sequence.

A scrambling operation is performed on the input data for the following reasons.

First, it ensures that active data is always sent on the channel even if the input data is temporarily all zeros.

This also allows the bit synchronizer at the receiving end to be in lock.

Second, the spectrum is broadened more uniformly into the occupied band by subtracting strong spectral components that would otherwise occur due to the characteristics of the input data.

Third, it provides a means for error testing the link.

When these oripoints are not needed, the scrambler can be omitted without affecting the device according to the invention.

The data output from the scrambler is sent simultaneously to two flip-flops timed by timing signals of the same frequency but 180 degrees out of phase with each other.

These two timing signals are the data clock fIN
is obtained from a two-part toggle that acts on .

The purpose of this circuit is to split the scrambled data stream into two parallel data streams occurring at half the original bit rate.

These two data streams, arbitrarily referred to as even and odd, are connected to a multiplexer or data selection switch.

The multiplexer sample rate is slightly faster than the effective input rate fIN by a fixed amount Δf.

To compensate for this high rate of data, a multiplexer inserts exactly Δf times as many stuff bits into the data stream per second.

The generated data is NRZ to distinguish it from the original NRZ signal.
Designated as Z'.

The input to the multiplexer is split into even and odd parts so that the data bits in each part remain unchanged for the indeterminate time being sampled.

The multiplexer output NRZ' is differentially coded.

A slight increase in channel A timing and data rate is done in the rate translation loop.

This loop divides the input frequency fIN by x and combines this with the original frequency to produce a slightly higher output frequency f0.

That is, f0=fIN+(fIN)/x=[(x+1
)/x] The fIN receiver circuit performs the reverse operation so that the output rate and data content it produces are no different from the original input.

At the receiver translation loop output, the velocity translation loop includes the digital equivalent of a single sideband modulator that produces the sum of two frequency sums.

Mathematically, this operation is sin(w1+w2)=sinw1cosw2+cos
It is expressed as w1sinw2.

After filtering, a phase-locked loop is used to actually generate the high output power used to drive the multiplexer.

The multiplexer output NRZ' is then differentially coded.

A differential encoding operation produces a transition in the output data for each input data bit of logic one.

This operation results in data information being conveyed in the relative transition of the data rather than the absolute value of the data itself, and avoids the data ambiguity present at the receiving end due to the absence of an absolute phase reference in the receiver.

Channel B data undergoes similar scrambling and differential encoding operations as channel A data.

However, channel B has no frequency translation.

In addition to the normal mode of operation described above, there is a test mode in which input data is disconnected from the scrambler and replaced with certain logic levels.

This allows the pseudonoise (PN) sequence of the scrambler to be sent unchanged to the differential encoder for subsequent transmission.

Although the PN sequence has a random nature, the pattern is deterministic and can be tested bit by bit at the receiving end for the occurrence of bit errors.

Test mode uses an internally generated crystal controlled clock.

This provides a stable clock for the scrambler and differential encoder when in test mode, allowing testing to occur even when there is no input data source.

Each channel is equipped with a separate oscillator.

Each channel is also provided with another switch so that one channel can be tested independently of the other.

Channel A test mode is activated by placing the switch in the TEST position or when there is no data input to channel A.

Loss of input signal activates a test mode on channel A to ensure continuous transmission of data to the receiver, where the circuit monitors the stuff bits for the presence of operational errors.

In this way, high operating error rates can be avoided even when the channel A input is disconnected.

Channel B test mode is activated only by placing the switch in the TEST position.

When the data input to channel B is removed, the clock derived from the phase lock oscillator is inhibited when the phase lock loop goes out of lock, effectively inhibiting output from channel B.

In this way, the generation of output data at speeds exceeding the normal clock speed due to the searching action of an out-of-lock phase lock loop can be avoided.

The channel recognizer resolves ambiguity at the receiver between the transmitted A, B channels versus the received I (in-phase) and Q (four-phase) channels.

If the I or Q channel being measured exceeds the local reference by a predetermined amount, it is identified as an A channel and treated accordingly.

In this case it is assumed that the unmeasured channel is the B channel.

Conversely, when the channel being measured does not exceed the local reference by a certain amount, it is identified as the B channel and the other channel is assumed to be the A channel.

Once the A and B channels of data are recognized, they are differentially code decoded and the B channel is output to the decoder for descrambling.

The channel A data rate is restored to its original rate and the stuff bits inserted by the encoder are removed before the channel A data is applied to the decoder for descrambling.

The decoder performs a descrambling operation on its input data and outputs a bipolar T-carrier compatible waveform.

The two channels A and B can be processed simultaneously by the decoder.

The decoder performs the inverse operation of the operation performed by the encoder to restore the output data to its original form. Each channel A, B descrambler performs the encoding operation performed by the scrambler of the encoder device. Correspondingly operate different codes.

The decoder also includes circuitry to detect the presence of stuff bits in the scrambled data of channel A'.

Once a stuffed bit is detected, a synchronization pulse is generated to enable subsequent removal of the stuffed bit.

Stuff bit detectors are also utilized to provide operational error monitoring capabilities.

If the operating error rate becomes excessive (eg >10-4), bipolar PCM outputs are inhibited for both channels.

Referring to Figures 1, 8, and 9 of the drawings, Figure 1 shows the asynchronous 4
8 shows a basic block diagram of the entire phase transmitter/receiver device, FIG. 8 shows a functional block diagram of the four-phase modulator of FIG. 1, and FIG. 9 shows a functional block diagram of the four-phase demodulator of FIG. The functional block diagram of FIG.

A pair of independently timed and mutually unsynchronized PCM (Pulse Code Modulation) data channels A, B are applied to encoders 1, 3, respectively, shown in detail in FIG. 2.

Encoders 1 and 3 each include a code A scrambler 2 and a code B scrambler 4.

Scrambler codes A and B are sufficiently different that the scrambled PCM signals are distinguishable at the receiver portion of the device.

Scramblers are of conventional design and can take many specific forms.

As mentioned above, the scrambler is not essential to the invention, but provides certain practical advantages.

The output of each scrambler is coupled to a pair of binary differential encoders 6 to modify each PCM channel for four-phase modulation.
, 8.

However, the output of scrambler 2 is applied through a data rate modifier 5 which changes the data rate of channel A.

A binary differential encoder 6,8 combined with a binary differential decoder in the receiver performs binary polarity ambiguity resolution within the four-phase channel of each phase.

The binary differential encoder itself is also conventional.

The outputs of encoders 1, 3 are applied to a four-phase modulator 10, which is shown in detail in FIG.

Each of the two phase shifters 212, 214 has one PCM
Controlled independently by channel 1.

The binary data driving each phase shifter is scrambled and coded differently.

A binary zero on the differential encoder input causes no change in the corresponding phase shifter output.

A binary 1 results in a 180° phase shift.

Phase shifters 212 and 214 act on the 0° carrier obtained from carrier oscillator 216 and power splitter 218.

A 90° delay device 220 receives the phase shifter 214 output and provides a −90°/+90° phase shift signal, which is coupled to the adder 222 along with the phase shifter 212 output.
to provide a four-phase signal on line 224 to a power amplifier and/or carrier frequency converter 226, which is a conventional device selected to match the available transmission medium 28.

Similarly, the transmission medium is the receiver front-end filter,
Determine the type of carrier frequency converter and amplifier 30.

The output of block 30, which is also a conventional communication circuit, is applied on line 32 to a four-phase demodulator 34, shown in detail in FIG.

The received signal on line 232 is applied to a power splitter 236 and a carrier reconstruction loop 238 which maintains a constant phase relationship to one of the four phase states of the received signal. -Includes lock oscillator.

The output of the carrier reconstruction loop oscillator provides a phase reference for demodulating the four-phase signal.

The power splitter 236 uses a phase reference signal (any zero
) and a −90° reference signal (phase reference signal delayed by 90° delay unit 244);
The received signal is split for application to H.242.

At this point in the receiver, there is no unique relationship between the phase finder output and the original input to the transmitter's four-phase modulator.

Unless the carrier reconfigurable oscillator loses phase lock due to loss of signal or very high noise level, the carrier reconfigurable oscillator will phase lock into one of four possible phase states and maintain this phase relationship. This ambiguity arises because

Phase detector 2 directed on inphase or I channel
The 40 output is applied to a conventional timing reconstruction circuit 246 to provide the I channel clock pulses and to a conventional filter and sampler circuit 248 which provides the complete I channel binary signal.

Similarly, the phase detector 2 directed by the 4-phase or Q-channel
42 output is applied to a timing reproduction circuit 250 and a filter and sampler circuit 252.

1, Q channel binary numbers and clock signals are applied to the channel recognition circuit 64, and thereafter are respectively applied to the binary differential decoder 5.
4,56.

(2) The channel represents, for example, one of the original A channel, or the B channel, or the original channel with reversed polarity.The channel recognition circuit looks at the data rate of each channel and controls the switch 58 to correctly classify the channels.

A binary differential encoder and decoder for each channel eliminates polarity ambiguity.

Data rate changer 59 restores channel A to its original rate.

Channels A and B are then connected to a pair of descramblers 60 and 6.
2.

The descramblers 60, 62 match the scrambling codes A, B of the transmitter section.

FIG. 2 shows a functional block diagram of the transmitter encoder for channels A and H.

The encoder receives PCM signals in a 50% bipolar T carrier and performs scrambling and differential encoding operations on them, with each output being a binary data stream suitable for driving a phase modulator. be.

The A channel encoder also changes the data rate.

Two asynchronous PCMs with nominal 1.544Mb/s speed
The signal sources are processed simultaneously.

However, the invention is not limited to such PCM sources.

Bipolar PCM data from each data channel is coupled to each interface stage 102, 122 where it is converted to return to zero (RZ) format.

RZ format data is transmitted to each clock reproduction circuit 104, 124.
and further applied to interface stages 106, 126, which also receive the reproduced clock signal and convert the RZ format data to non-return-to-zero (NRZ) format.

Details of clock reproduction circuits 104 and 124 are described below in conjunction with FIG.

Interface stages 102, 106, 122, 126 are conventional and implementations of this circuit are known in the art.

With particular reference to Channel A of FIG.
Gives fIN output.

Switch 108 normally connects clock reproduction circuit 104 to 2f.
Although connected to receive the IN output, the switch is connected to a local clock source, such as a crystal oscillator 110, for testing purposes.

Switch 108 applies the 2fIN signal to clock speed translation loop 116 and divide-by-two block 112, shown in detail in FIG.

The output of block 112 is fIN, clock speed translation loop 116, scrambler 11, shown in detail in FIG.
4, applied to data rate processing unit 118;

Clock speed translation loop 116 provides two clock signal outputs at speeds fIN+Δf and Δf.

As will be appreciated, the clock rate fIN+Δf is the changing clock rate for channel A data.

Scrambler 114 also receives NRZ data from block 106 and provides a scrambled NRZ output to data rate processor 118.

Processor 118 receives fIN+Δf and Δf clock signals and receives fIN+Δf from clock rate translation loop 116.
It provides a modified data output indicated by the modified clock speed NRZ' for application to a binary differential encoder 120 which also receives a clock signal.

The output of binary differential encoder 120 is applied to four-phase modulator 10 of FIG.

Referring to the channel B portion of FIG.
4 is applied.

The scrambler receives a reproduced clock signal fIN from switch 128 or, in test mode, a local clock signal from block 130, for example a crystal oscillator.

The scrambled NRZ output from block 134 is sent to a binary differential encoder 138 which also receives a clock signal fIN.
is applied to provide an output to the four-phase modulator 10 of FIG.

FIG. 3 shows the clock reproduction circuits 104, 124 in detail.

Input data in RZ format is first applied to a high-Q resonant filter 150, also known in the art as a ringing filter.

This filter "resonates" at its resonant frequency when there is a string of zeros at its input.

The time constant of the envelope delay is Q/■ cycles.

Therefore, with a Q of about 30, the filter output will be 1 of its initial value.
10 consecutive zeros can occur before decaying to /e.

A signal that is relatively stable in frequency is therefore present at the filter output to phase-locked loop 152.

Loop 152 is conventional and includes a voltage controlled oscillator (VCO) operating at twice the clock frequency fIN, which is divided by two and fed back to a phase detector (not shown), thus providing two outputs, 2fIN and fIN is available.

Filter 150 also drives an in-lock detector 154, which is, for example, a comparator that compares the signal obtained from the filter with that obtained from the phase-locked loop.

When the phase lock loop is locked to the input, a signal is provided to a display 156, which may be, for example, a light emitting diode.

Figures 4 and 12 show details of each scrambler and descrambler operation.

The scrambler basically consists of a six-stage shift register 162 with a feedback tap that can generate a pseudo-noise (PN) sequence.

The selected feedback taps yield a maximum length 2N-1 bit string, where N is the number of register stages.

In this case N=6, so the column length is 63 bits and the feedback tap is taken from stage 6,1 or stage 6,1.

The scrambled output is the modulo-2 addition of the data input and the output Y of the feedback shift register.

Blocks 160 and 164 represent the modulo 2 addition function.

This scrambled output (X+Y) is directly applied to the input of a similarly configured feedback shift register 404,
When the shift register output (Y) is added modulo 2 to the input, the original data input X to the scrambler is recreated.

The channel A scrambler uses feedback taps 6,1, while the channel B scrambler uses taps 6,5.

Blocks 402 and 406 direct the modulo 2 addition function.

The use of a scrambler to uniquely identify channels is accomplished by using a different pseudonoise (PN) sequence for each data channel.

In order to properly descramble the data, the opposite operation must be performed at the receiving end, and these descramblers are configured as shown in Figure 12 to be consistent with the unique PN sequence generated by their respective scramblers. Constructed as shown.

FIG. 5 shows the clock speed translation loop in detail.

The purpose of the clock speed translation loop is to provide an output clock signal at a speed of fIN+Δf.

In this particular example, Δf is fIN+255.

It will be clear to those skilled in the art that Δf may take other values.

The velocity translation loop includes the digital equivalent of a single sideband modulator that generates the sum of two frequencies.

Mathematically, this operation can be expressed as follows.

sin(fIN+Δf)=sinfINcosΔf+c
osfINsinΔf.

The clock speed translation loop therefore functions to generate a Δf clock frequency and add fIN to it to provide a modified clock speed signal fIN+Δf.

The loop is applied to the 90° shift block 170.
IN, 2fIN receives a clock speed signal at its input;
Block 170 provides Sin fIN at its output.

Block 170 is, for example, a D-type flip-flop that receives fIN on its data input and 2fIN on its clock input.

The fIN input clock is also applied to one input of a divide-by-255 counter 174 and an exclusive OR gate 180.

The 2fIN clock speed input signal is also applied to the 255 divide block 176.

The block 174 output fIN+255 is applied to another 90° shift block 178 which also receives the block 176 output 2fIN+255.

Block 178 is also a D-type flip-flop.

The output of block 178 is sinΔf and is applied to the other input of exclusive-OR gate 180, which therefore provides sinΔfcos fIN at its output.

Exclusive OR gate 172 is the sin fI of block 170
It receives the N output and the cos Δf output from block 174 and provides sin fIN cos Δf to an adder 182, which also receives the output of exclusive-or gate 180 and provides a summation term equivalent to sin(fIN+Δf).

This signal is applied to a bandpass filter 184 at frequency fIN+Δf, and the filtered signal is then applied to frequency fIN+Δf
is applied to a conventional phase-locked loop 186 which provides the correct clock signal at its output.

An in-lock detector, such as comparator 188, receives the loop output and input and provides a signal indicating when the loop is in lock.

FIG. 6 shows data rate processing unit 118 in greater detail.

Reference is also made to Figures 7a, b, c which illustrate a series of waveforms useful in understanding the operation of data rate processing devices.

The purpose of the data rate processor is to convert the scrambled NRZ data at clock speed fIN to clock speed fIN+Δ.
f into scrambled NRZ data.

To do this, we add a "stuff" bit or Δ bit to every 256th bit, as explained below.

Those skilled in the art will appreciate that the stuff bits are preferably logic ``0''s, but may also be logic ``1''s, or alternating ``1''s and ``0''s, or other deterministic patterns.

Stuff bits define frames of data.

The scrambled NRZ data is applied to first and second flip-flops 192,194.

The flip-flops are timed by the even and offset phases of the fIN clock applied to the output of divide-by-two counter 190 such that flip-flop 192 provides an "even" data output and flip-flop 194 provides an "eclipse" data output.

These outputs are applied to a multiplexer 196, shown as a switch for simplicity, which selects between the even and marginal data outputs of the flip-flops and the stuff bits.

The multiplexer or switch connects the Δf clock and fIN+
Controlled by data select logic block 198 which receives the Δf clock.

Let the data rate of channel A be Δf, in this example fIN+2
To increase by 55, increase the length of each of the original bits by 1+
It is recognized that it is necessary to shorten the length by 255.

Sampling of switch 196 must occur at a faster clock speed.

However, if the input scrambled NRZ data is not separated into even and odd phases, the sampling point will slide relative to the input data's slow clock speed,
This results in an undefined sample at the end of the 55 bit period.

This can best be understood with reference to Figures 7a, b, c.

FIG. 7A shows exemplary scrambled NRZ data as applied to flip-flops 192,194.

Each successive cell of data is designated by an even (E).

The fIN clock time is equal to the width of each data cell and is indicated by the 360° arrow above cell E1.

The original data in Figure 7A is incorrect and the clock speed fIN + Δf
The sample time for each data cell advances progressively.

This is shown in a somewhat exaggerated manner by the arrows below the data cells in Figure 7A.

For example, the first sample, sample S1 in data cell E1, occurs at the center of the data cell.

Assume that fIN and fIN+Δf clocks coincide at this particular time.

However, in the next data cell O1, the sample S2 taken according to the input clock fIN occurs at the center of the data cell, while the sample S2' taken according to the fIN+Δf clock is in progress.

As samples continue to occur in successive data cells, for example in cell E3, fIN+Δf clock samples continue to occur in the data cell until sample S5' occurs at the boundary between E3 and O2, causing an undefined sampling. occurs progressively faster.

The deviation from sample point S5 to sample point S5' is simply a 180° shift.

It is clear that the sample points shift throughout the entire 360° range.

That is, over a 256-bit period, there is a difference of 3 between the input clock speed fIN and the fast clock fIN+Δf.
There is a 60° shift.

To overcome this sampling problem due to the increased fIN +Δf sampling rate, the scrambled NRZ data is separated into even and odd bit streams as shown in Figures 7B and 7C.

By doing this, the range of possible sample times over a 360° period is completely contained within the width of the bit cell.

This is illustrated schematically with reference to bit cell E1 of waveform 7B.

Accordingly, data selection switch or multiplexer 196 of FIG. 6 alternately samples the even and odd data bit streams from flip-flops 192, 194 to provide 255 bits of information data, which is then stuffed in real time as the 256th bit. Add bits or delta bits.

Figures 7D to 7H are useful in understanding the subject matter of Figure 6.
Another timing waveform is shown.

These figures show the relative timing in five parts during two frame intervals.

The original clock fIN is shown for reference.

Serial data (scrambled NRZ format) is shown schematically as bit cells labeled B1 to B510.

Similarly, the odd (from flip-flop 194) and even (from flip-flop 192) bit cells are B1
They are named B509 (odd number) and B510 (even number) from B2.

Δf and fIN+Δf clock pulses are shown.

Within the data selection logic 198, the "odd force" and "even force" pulses are derived from the fIN+Δf clock.

The "stuff enable" pulse is derived from fIN+Δf clock after the Δf clock pulse occurs.

Odd/even activation pulses are inhibited during stuff activation pulses.

Data sampling occurs on the positive transition edge of the clock pulse.

Therefore, for example, when the odd bias is high, the positive transition clock (
The odd bit B509 is sampled with the fIN+Δf) pulse.

Note the relative shifted positions of the B509 and B1 samples within each bit cell (indicated by arrows and dashed lines).

These locations are at the extremes of the sampling points throughout the frame, and the bits are adjusted to avoid unclear samples.
Within ten minutes of the cell.

It will be apparent to those skilled in the art that the precise logical arrangement of FIG. 6 may take many forms within the scope of these teachings.

It will be apparent to those skilled in the art that various other devices may be provided to increase the clock speed of the data from channel A.

For example, one or more memories may be provided into which data is read at a first rate and read out at a second rate.

The invention is not limited to the particular devices for increasing clock speed as disclosed herein.

Referring to FIG. 10, the channel recognition circuitry and data rate changer of the asynchronous four-phase receiver of FIG. 1 are shown in detail.

Channel recognition circuit 64 eliminates ambiguity at the receiver between the transmitted A, B channels versus the received I (inphase), Q (four-phase) channels.

The channel recognition circuit does this by measuring the relative timing of the I or Q channel data rate to a reference.

If the I or Q channel being measured exceeds the criteria by a certain amount, it is identified as an A channel and treated accordingly.

In this case, the unmeasured channel is assumed to be the B channel.

Conversely, if the channel being measured does not exceed the criterion by a certain amount, it is identified as a B channel;
The other channel is assumed to be the A channel.

Once the A and B channels of data are recognized, the B channel is decoded differently and then descrambled.

The A channel is applied to a data rate modifier 59 which restores it to its original rate and removes any stuff or delta bits inserted by the transmitter before the signal is applied to the descrambler.

The reference is typically a local clock reference, but the clocks of the two channels I,Q may also be compared with each other.

Channel recognition circuit 64 receives the double frequency I,Q channel clock signal applied to switch control logic 302.

Although either the I or Q clock is tested, the channel being tested must have correct data as determined by the INLOCK signal applied to logic 302 before it is monitored.

For example, a crystal oscillator operating at twice the fIN clock frequency (channel B clock frequency) of 3.088 MHZ applies a clock signal to counter 306.

Counter 306 is a 2048 division counter and provides the basis for resetting counter 304.

It is necessary to distinguish between the modified timing versus the one extended by a factor of 256+255.

This amount of scaling beyond the 2048 counts results in about 2056 counts, or about 8 extra counts.

If the channel being monitored exceeds 2052, ie, exceeds the reference interval of 2048 counts by 4 extra counts, a decision is made for channel A.

A count equal to or less than 2052 will result in a channel B decision.

Therefore, counter 304 is timed by the I or Q clock input and the code decoded output of the count is applied to logic 302 which looks for 2052 counts before the 2048 reference count from counter 306. If the count is received, determine channel A;
If the reference count is received before the 2052 count from counter 304, the reference signal provided by oscillator 308 determines channel B, thereby making the determination and providing the control signal to channel classification switch 58, instead of the other channel. It is recognized that the clock signal may be from any channel.

The channel B output from switch 58 is differentially decoded by applying the NRZ data and clock signals to differential decoder 314, the output of which is applied to another circuit shown in FIG. 11, described below.

It is clear that the embodiment described above is a digital implementation of the functionality of a frequency discriminator.

This functionality can also be implemented in other ways, such as using an analog discriminator or a single sideband modulator.

Channel A NRZ' data and clock are further applied to differential decoder 316.

The code-decoded NRZ' data and channel A clock are applied to data rate changing circuit 59.

Circuit 59 performs the inverse function of data rate changer 5 in the transmitter part of the device.

That is, this increases the data rate of channel A information to 255
Decreased by a factor of +256.

This also removes the stuff or delta bits and provides the original timed channel A data signal.

Data rate modifier 59 receives the channel A double frequency clock signal and also the output of differential decoder 316.

Stuffing using a velocity translation loop similar to the transmitter circuit
Delay the timing by the amount necessary to remove the bit.

Double frequency clock signal 2f' (where f' is fIN+
Δf) is applied to the two-part block 317 and the 90° shift block, which is a D-type flip-flop as shown in FIG.
The sinf output is given to 18.

The f' clock is a 256 division counter 322, and also a co
It is applied to the exclusive OR gate 320 as the sf' signal.

Divider 322 provides cosΔf and SlnΔf' outputs to each exclusive OR gate 318,320.

The output of gate 318 is sin f'cosΔf' and the output of gate 320 is cos f'(-sinΔf'
).

These two signals are summed in a summer 324 that applies the signal sin(f'-Δf') to a bandpass filter 330.

Mathematically, this operation is (sin f') (cosΔf
')-(cos f') (sinΔf')=sin(
f′−Δf′).

Δf'=f'+256 and f'-Δf' is 255+256
Since xf', this is the exact amount of frequency reduction required to restore the modified A channel to the original A rate.

The output of filter 330 is phase-locked loop 33
2, the phase-locked loop 332 locks onto the filtered signal to generate a clock at the desired rate fIN.

A lock detector or comparator 334 looks at the loop inputs and outputs and provides a signal indicating a lock condition.

The stuff bits must also be removed and the data is fIN
The time is re-timed at the slow A speed.

The presence and location of stuff bits and the serial data stream of the modified A channel are determined by circuitry forming part of FIG. 11, described below.

A Δ bit sync pulse is generated to determine when periodic stuff bits occur.

This pulse is applied to the counter 322 and resets the 256 division counter so that the counter overflow has a constant temporal relationship to the occurrence of the stuff bit.

All data bits except stuff bits are sampled, which effectively eliminates stuff bits from the data stream.

The demultiplexer control unit 326 is the demultiplexer 32
8 and receives the output from counter 322.

The demultiplexer samples all bits except the stuff bits, thereby effectively eliminating the stuff bits from the output data stream.

The sample bits are then retimed into a flip-flop included in demultiplexer 328 at the slow data rate, buffered, and applied to the circuit of FIG.

Figures 10b-10d illustrate various timing waveforms that are useful in understanding Figure 10a, particularly with respect to demultiplexer 328 and demultiplexer control 326.

As was done in Figures 7d-7h, Figures 10b-d show the relative timing of each portion during two frame periods.

NRZ' data from differential decoder is bit cell B1
Stuff bit cell (B25
6 and B512).

A fast clock f'=fIN+Δf is shown above the bit cell.

The Δ bit sync pulse from FIG. 11 (delayed by a half clock pulse due to inherent circuit delays) resets the 256 counter 322.

Counter periods are shown as cells 1 through 256, with '0'
Occurs when a cell is reset.

The counter has two Δf' outputs (Δf'=f'+256=
(fIN+Δf)+256), one of which is shown in Figures 10b-10d.

The NRZ' data is split into odd and even at demultiplexer 328 in the manner shown in FIG. 6 (not shown in FIG. 10a).

The demultiplexer control 326 receives the original fIN clock from the PLL 322 and generates "even bias" and "odd bias" pulses as shown which are inhibited by the Δ bit pulse.

Therefore, the generation of a positive transition fIN clock pulse and an odd or even energization pulse results in the sampling of odd and even NRZ' data, thereby providing output data at the original channel Δ rate.

Note the relative positions of the samples in cells B254 and B2 (indicated by arrows and dashed lines).

As in Figure 7d, these are extreme examples of sample point locations within a bit cell.

Referring to the details of FIG. 11, a stuff bit detector providing a stuff bit or delta bit synchronization pulse to data rate changer 59 of FIG. Shown with utensils.

Also shown is an error detection circuit that inhibits channel A and channel B outputs when no stuff bits are detected.

Stuff bit detector has been modified (i.e. faster)
Receives Channel A scrambled data and Channel A clock signal at rate f'.

The stuff bits are 255 of the channel A data bits.
Recall that it is desirable to have a logic 0 inserted after each.

Basically, stuff bits are detected by comparing received data bits delayed for exactly 256 clock intervals and noting which bits at the interval are consistently logic zero. Ru.

A 256-bit shift register 354 is used to delay the data.

Another 256-bit shift register is used for searching, acquiring, and tracking stuff bits and is referred to as the tracking register.

The Stuff Bit Detector operates in three modes: search, acquire, and track.

In search mode, one frame of data is shifted to the register 35.
A bit-by-bit comparison is made with the previous frame of data stored in 4, and information regarding which bits meet the criteria for stuffing bits is placed in shift register 352.

The frame defined by the stuff bits is 256
Consists of bit data.

All cells of trace register 352 must be empty before entering search mode.

Because of the random data given, on average 1/1 of the cell
464 are filled during one frame search.

Following the one frame search mode, shift register 352
Enter acquisition mode where another cell inside is not filled.

Alternatively, cells may remain filled during the search mode provided that the bit comparator continues to meet the stuff bit criteria in each successive frame.

If this criterion is not met, previously filled cells are cleared or emptied.

The acquisition mode continues for as many data frames as necessary until only a single cell remains filled.

This cell and its position correspond to the stuff bit.

On average, half of the cells filled for random data are cleared in each successive frame during acquisition mode.

For example, during one frame of search mode data, 128
If 64 cells were filled, then after the first frame of data in acquisition mode 64 cells are cleared (on average) and 64 cells still remain filled.

On average, 32 cells remain filled following the second frame of data, 16 cells remain after the third frame, and converge to a single cell after the seventh frame of data in acquisition mode. .

The acquisition mode by clearing cells that do not meet the stuff bit criteria after each frame of data ensures convergence to actual stuff bits when stuff bits are present.

Finally, only a single cell corresponding to the stuff bit remains filled in the trace register.

When this happens, acquisition mode stops and tracking mode begins.

Average acquisition time to converge to stuff bit is approximately 1.5m
It is s.

The rare chance of getting a stuff bit within 4ms is 0.999
Greater than 9.

While in trace mode, a single cell corresponding to a stuff bit can be cycled through the trace register.

In addition, a bit comparator 356 continuously tests each new frame of data according to the stuff bit criteria, and the output from this comparator clocks the stuff bit time as determined by the rotating bit in the trace register. occurs.

This clock increments up/down counter 368 if the comparator output meets the stuff bit criteria, otherwise the counter is decremented.

The counter is clamped in reset during search and acquisition mode and can only be counted in tracking mode.

The counter can be incremented unless it is already at a full school count of 15.

Conversely, it can be decremented as long as it contains a count greater than zero.

In this way overflow and underflow are avoided.

This counter registers the number of bits during the stuff bit period.
Provides the ability to make stuff bits traceable even in noisy environments where errors occur.

A bit error rate of greater than 33% is required to cause the stuff bit detector to change from tracking mode to searching mode.

If the counter decreases to zero, the cell in trace register 352 corresponding to the stuff bit is no longer available for rotation and is instead cleared.

Once cleared, all cells in the trace register are empty and this condition initiates search mode.

The rotation bit in the tracking register is used as a timing pulse to synchronize the data rate changer of FIG.

This pulse is called "Δbit sync."

The number of filled cells in trace register 352 determines the mode of operation of the stuff bit detector.

Shift register monitor 366 has three outputs depending on the contents of register 352.

If each of the 256 cells is empty, a search mode over exactly one frame of data is initiated to fill cells that are stuffing bit candidates.

This is accomplished by monitor 366 applying a logic "1" to AND gate 358.

An acquisition mode is implemented that is continuously repeated through successive frames of data when one or more cells are full.

For this mode, monitor 366 uses AND gate 360
Apply a logic "1" to.

During each cycle all filled cells of the trace register are successively tested against their corresponding received data bits according to the stuff bit criteria.

Filled cells that fail the test are emptied until convergence to a single filled cell.

When only a single cell is filled, tracking mode is entered and a stuff bit is assumed to have been found.

In this case, monitor 366 energizes counter 368.

Monitor 366 includes a two-stage shift register (not shown) that monitors the cell status of trace register 352.

Each filled cell in the tracking register generates a shift clock for a two-stage shift register that is reset once per frame.

At the end of each frame, the state of the two-stage shift register is sampled and stored.

A decode gate (not shown) determines whether the two-stage shift register receives zero, one, or more shift clocks during the 256-bit frame interval.

This stored information determines whether the stuff bit detector operates in search, acquisition, or tracking mode for the next frame interval.

As an optional feature, operational error generator 372 also receives the track mode output of monitor 366 and the down count of up/down clock generator 370.

The output from monitor 366 indicates an error-free condition, while the down count from clock generator 370 indicates an error.

When a predetermined number of errors occur during a selected time period, error rate monitor 378 triggers one shot 380 for a short period of time.

The one-shot is continuously retriggered as long as the bit error rate is greater than once per 10,000 bits.

A second retriggerable one-shot 374 is triggered by the individual error pulses and generates a 1/4 second long pulse that turns on an LED indicator 376 that is observed by the equipment operator.

Since the active error pulse is obtained from a comparison of successive stuff bits, an error occurring in one stuff bit position will result in two active error pulses.

The output of one shot 380 is applied to an OR gate 382 which also receives another input from another source, which is a manual inhibit signal.

The output of OR gate 382 is applied to blocks 390 and 398 to inhibit output data.

The remainder of the apparatus shown in FIG. 11 includes channel A, which receives scrambled data and clock signals for each of the channels;
B descramblers 384 and 392 are included.

The scrambler is matched to the scrambling code of the transmitter section of the device.

Test mode detectors 386, 394 are connected to each scrambler device and provide visual indications on indicators 388, 396 when the device is in test mode, as described above.

The output of the descrambler is applied to an NRZ-to-bipolar format converter 390, 398 which receives each clock signal of the channel.

The outputs of blocks 390 and 398 are the initial Channel A and Channel B PCM data.

Although the best mode of carrying out this invention has been disclosed herein, it will be obvious to those skilled in the art that modifications may be made to the disclosed embodiments without departing from the scope of the invention.

The invention is therefore to be limited only by the scope of the appended claims.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the entire asynchronous four-phase communication device. FIG. 2 is a block diagram of the encoder section of FIG. 1. FIG. 3 is a block diagram of the clock reproduction circuit of FIG. 2. FIG. 4 is a block diagram of the scrambler of FIGS. 1 and 2. FIG. 5 is a block diagram of the clock rate translation loop of FIG. FIG. 6 is a block diagram of the data rate processing device of FIG. 2. Figures 7a through 7h are timing diagrams useful in understanding the data rate processor of Figure 6. FIG. 8 is a block diagram of the four-phase modulator of FIG. 1. FIG. 9 is a block diagram of the four-phase demodulator of FIG. 1. FIG. 10a is a block diagram of the channel recognition circuit and data rate changer of the asynchronous four-phase receiver of FIG. Figures 10b-10c are timing diagrams useful in understanding Figure 10a. 11a-11b are block diagrams of the delta or stuff bit detector, error detector, descrambler, and format converter of the asynchronous four-phase receiver of FIG. FIG. 12 is a block diagram of the descrambler of FIG. 1. 1, 3... Encoder, 2, 4... Scrambler, 5... Data speed changer, 6, 8
...Binary differential encoder, 10...4
Phase modulator, 34...Four phase demodulator, 54, 56...
...Binary differential decoder, 60, 62...
Descrambler, 64...Channel recognition circuit.

Claims (1)

[Scope of Claims] 1. A communication device for transmitting two independently timed binary data signals on a single four-phase modulated carrier wave through a transmission medium, comprising: (a) forward two independently timed binary data signals; receives a binary data signal, and while maintaining the independent timing of each of the signals, changes the data rate of one of the signals to continuously generate a signal with the changed data rate and a signal with the data rate unchanged. (b) a carrier wave that receives said independently timed and encoded data signal from a forward encoder device and that is four-phase modulated in accordance with said signal; a device that generates a signal; (c) a device that applies the four-phase modulated carrier signal to the transmission medium; and (d) receives the four-phase modulated carrier signal from the transmission medium and demodulates the carrier signal in four phases. (e) a device that receives the first and second demodulated signals and determines whether or not the data rate of the first and second demodulated signals is changed;
(f) a recognition device that receives the first and second demodulation signals and recognizes which of the two independently timed binary data signals each demodulated signal corresponds to; Responsive to the recognition, differentially decoding those of said first and second demodulated signals whose data rate is not changed, and the data rate of said two independently timed binary data signals is changed. differentially decodes the first and second demodulated signals whose data rate has been changed, and returns the data rate to the original data rate. and a fourth signal corresponding to the variable data rate of the two independently timed binary data signals. A communications device that transmits two independently timed binary data signals.