JPS588353A - Multiplier - Google Patents

Abstract

PURPOSE:To improve the performance of a binary multiplier, by storing an output of a switching circuit to a register, shifting the output of the register by the specified number of bits and applying them to a carry save adder. CONSTITUTION:A multiplicand is stored to a register 1, a multiplier is stored in a register 2, and the content of the register 2 is outputted with multipliers 4- 9 via a switching device. The output is added via carry save adder CSA circuits 10 and 11 and after being stored in registers 16-19, the output is added at tree shaped CSA circuits 12-15. On the other hand, a part of the registers 1 and 2 is multiplied 27 and 28, one of the output is switched 29 and 30 and given to a register 25 via CSA circuits 22 and 23 with the output of the circuit 15.

Description

[Detailed description of the invention] The present invention relates to binary multiplication systems.

In the past, various configurations of devices have been proposed as devices for multiplying binary numbers, but one configuration that is often adopted for high-speed processing in recent multiplication devices is the Booth. The structure is such that a large number of partial products are generated at once using an algorithm, etc., and these are added by a multi-input adder in which carry-save adders are connected in a tree shape.

Referring to FIG. 1, the conventional multiplication device includes register 1 for storing a 72-bit multiplicand, register 2 for storing a 28-bit multiplier. A switching circuit 3 selectively outputs the multiplier from the cough register 2 for each bit processed from the lowest order, and a partial product using Booth's algorithm based on the output from the register 1 and the switching circuit 3. generates output lines 101.102. . . , multipliers 4, 5, 6, 7, 8, which output to 105 and 106. and 9. A carry-save adder (hereinafter referred to as C8A) 10 and 11. which adds the parts/products from the multiplier 4-9.
Registers 16 and 18 . which store carry signals of the addition results from these C8AIOs and 11 . Registers 17 and 1 that store the sum signal of the addition results
9. These registers 16.17.1g.

A tree-like C3A12゜1 that adds the contents of and 19
3.14. and 15. Register 20 for storing the carry signal of the output of C8AI5 at the final stage. A register 21 for storing the sum signal. adders 22 and 23 . which add the contents of these registers 20 and 21; flip flop24. and a register 25.

Referring to FIGS. 1 and 3, in the operation of this device, multipliers 4 to 9 take the partial products of the contents from register 1 and circuit 3, and then adders 10 and 11 add the partial products. Register 16°17.18. and stored in 19.

Next, registers 16, 17, 18 . And the contents from 19 are tree-like C3A12, 13, 14. and 15 and partially stored in registers 20 and 21. - times of addition process 12 bits of the 28 bits of the multiplier. Therefore, the -th addition result is the C8AI3
and the registers 16.17.18. and 19
The zero-order partial products and additions are taken. Timing t in Figure 3
3 to t6 are spent for this operation. Note that since the lower 12 bits of registers 20 and 21 are lost in each cycle, these are added by adder 22 and the result is stored in register 25 to complete the multiplication operation. As shown in FIG. 3, it takes five clocks from the start of the first multiplier operation to the storage operation in the register 25. In this operation, the feedback operation via signal lines 107 and 108 is the first partial noodle addition cycle (tl tx).
In this case, the multiplication function is not fully fulfilled, that is, in this cycle (tx-tz), the contents of registers 20 and 21 are r
It is OJ, and there is a drawback that "0" is simply added to the partial product po generated at timing t19.
Next, although the device shown in Figure 1 can generate partial products for a 12-bit multiplier per cycle, it generates partial products for a 4-bit multiplier in the most popular partial product cycle (is-ts). There is also the drawback that it is just a matter of doing so. One way to eliminate this latter drawback is to make the number of bits processed per cycle a divisor of the number of bits of the multiplier. In the example in Figure 1, it is 28 bits, so its divisors are rlJ, r2J, r4J, r7J,
r14J.

There are 6 types: ``28'' and ``28''. The divisor is riJ, r2J
.

When set to "4" and "7", the performance deteriorates significantly, and when set to "28", the amount of metal is too large. With the divisor "14", 11 stages of C8A must be added compared to the 12-bit processing described above, and therefore 14 stages per cycle.
(Pitsu) Even if the configuration is such that the execution of 1-processing and multiplication ends at the timing of 4 cycles.

This method has the disadvantage that the clock interval increases due to the increase in signal delay time, making it impossible to improve performance.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a multiplication device with improved performance by adding less hardware.

A multiplication device that performs binary multiplication according to the present invention includes a multiplicand storage means for storing a multiplicand, a multiplier storage means for storing a multiplier, and a part of the contents of the multiplier storage means that is divided into a plurality of parts and sequentially outputted. partial multiplier supply means; first multiplication means for multiplying the output of the multiplicand storage means by the output of the partial multiplier supply means to create a plurality of partial products; a first storage means group for storing;
The carry/save unit connected to this first group of storage means
and second multiplication means for multiplying the output of the multiplicand storage means by a portion of the contents of the multiplier storage means to create one or more partial products.

a selection means for selecting and outputting the output of the carry-save adder means and the output of the second multiplication means; a second group of storage means for storing the output of the selection means;
means for shifting the output of the storage means group by a predetermined number of bits and inputting the shifted output to the carry-save adder means.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 2, one embodiment of the present invention includes register 1, which stores a 72-bit multiplicand, and register 2, which stores a 28-bit multiplier. A switching circuit 3 for selectively outputting the 24-bit multiplier from the register 2 in 12-bit increments.
A partial product is generated using Bootli's algorithm based on the output from the register 1 and the switching circuit 3, and an output line is generated.

Multipliers 4, 5, 6, 7°8 output to 101-106,
and 9. Based on the contents of register 1 and the contents of bits 24 to 27 of register 2,
multipliers 27 and 28 .that generate friend part products using the algorithm of oth) and output them to output lines 109 and 110;
C3A10 and 11. which add the partial products from multipliers 4, 5, 6, 7°8, and 9; Registers 16 and 18 . which store carry signals of the addition results from C3A10 and 11. Registers 17 and 19 . that store the sum signal of the addition result. These registers 1
6゜17.1B, and add the contents of 19 IJ-
C3A12, 13, 14. and 15. C of the last stage
3A15 switching circuits 29 and 30 that output either one of the output from the knee et al. and the output from the multipliers 27 and 28; Registers 20 and 21 . which store the outputs of switching circuits 29 and 30 . Adder 22 which adds the contents of the upper bits of registers 20 and 21. an adder 2 that adds the contents of the lower bits of the registers 20 and 21;
3. It is comprised of a flip-flop 24 that stores the signal from the adder 23, and a register 25 that stores the output of the adder 22.

Next, the operation of this embodiment will be explained in detail.

Referring to FIG. 2 and FIG. 4, first, the timing to
Then, the multiplicand is set in the register i, and the multiplier is set in the register 2. At timing t1 of one clock edge, registers 16, 17, 18 . and bit 1 of register 2 in 19
Partial products corresponding to numbers 2 to 23 are set. In the operation of the conventional device shown in FIG. 3, logic "01" is set in registers 20 and 21 at t1.

As shown in FIG. 4, in the operation of this embodiment, the timing t'
1, partial products corresponding to bits 24-27 of register 2 are set in registers 20 and 21. That is, in the first partial product generation cycle (between 1 and L1't), partial products corresponding to bits 24 to 27 of register 2 are generated by multipliers 27 and 28 and sent to signal line 10.
9 and signal line 110, and is further output to switch '12
9 is the partial product of the signal line 109, and the switch 30 is the signal line 11
It is controlled to select a partial product of 0. □ At timing t2, partial products corresponding to register 20 bits θ to 11 are set in registers 16, 17, 18 and 19,
The sum of partial products corresponding to bits 12 to 27 of register 2 is set in register 20 and register 21.

In this partial product addition cycle (from tl to 1.), switch 29 uses the contents of signal line 111, switch 3
0 is controlled to select the contents of signal line 112.

At timing t3, register 20. The sum of all partial products is set in and 21, but in this partial product addition cycle (from 1 to tl), the switch 29 is set to the content of the signal line 111, and the switch 30 is set to the content of the signal line 112. controlled to select. At timing t4, the contents of the registers 20 and 21 are added by the adder 22, the result is set in the register 25, and the multiplication □ is completed.

The multiplication execution time in this embodiment shown in FIG. 4 is faster by one clock compared to the conventional device shown in FIG. This increase in speed is achieved by eliminating the two drawbacks of the prior art devices mentioned above.

In this embodiment, switching circuits called switches 29 and 30 are used to switch the inputs to the registers 20 and 21, but when selecting the contents of the signal line 109 and the signal line 110, the signal line 111 and signal line 11
Means for setting 2 to “0” and signal line 111 and signal line 11
When selecting the content of each of 2 and 2, signal line 10
9 and signal li! By providing means for setting 110t to "0", these switching circuits can be replaced by OR gates.

Further, in this embodiment □, the bit width of the multiplier is set to 28 bits, but it goes without saying that the present invention is applicable to bit widths other than this.

The present invention has the advantage of improving performance compared to conventional devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional device, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram for explaining the operation of the conventional device shown in FIG. 1, and FIG. FIG. 3 is a diagram for explaining the operation of the embodiment shown in FIG. 2; In the figure, 1, 2, 16, 17, 18, 19°20.
21, 25...Register, 3, 26, 29゜3
0... Sui, thousand, 4, 5, 6, 7, 8, 9゜2
7.28... Multiplier ζ 10.11, 12, 1
3゜14.15...Carry save adder (C8A).・22, 23.・・・・・・Adder, 24・old・・flip flow#=IV￥1 Mayuzumi 2 sides

Claims (1)

[Claims] A multiplication device that performs binary multiplication, comprising a multiplicand storage means for storing a multiplicand, a multiplier storage means for storing a multiplier, and a part of the contents of the multiplier storage means divided into a plurality of parts. partial multiplier supply means for sequentially outputting; first multiplication means for multiplying the output of the multiplicand storage means by the output of the partial multiplier supply means to create a plurality of partial products; a first storage means group for storing partial products of;
The carry/save unit connected to this first group of storage means
an adder means, and a second multiplication means for multiplying the output of the spinning number storage means by a part of the contents of the multiplier storage means to create at least one partial product. a selection means for selecting and outputting the output of the carry-save adder means and the output of the second multiplication means; a second group of storage means for storing the output of the selection means;
and means for shifting all the outputs of the storage means group by a predetermined number of times and inputting the shifted data to the carry-save adder means.