JPS5880724A - Timing device - Google Patents

Abstract

PURPOSE:To decrease the number of interface lines among circuits and to realize a high-speed operation with high accuracy for a timing device without increasing the hardware quantity, by performing a parallel operations by means of a high- speed adder having a small bit width and using the same circuit to perform the parallel operation. CONSTITUTION:The 1st and 2nd logical circuits 100 and 200 have the same structure and are set into a timing device. These logical circuits contain the timer registers 101 and 201, the TOD registers 102 and 202 which show the time elapsed from a prescribed time point, and the comparing registers 103 and 203. In addition, the 1st and 2nd adders 106 and 206 are provided to the circuits 100 and 200 respectively, and at the same time the 1st and 2nd carrying registers 107 and 207 are added in correspondence to the adders 106 and 206 respectively. Such adders 106 and 206 perform the parallel operations, and the output of this operation is compared with the outputs of the registers 103 and 203 through the comparators 111 and 112. Thus the number of interface lines is reduced between the circuits 100 and 200, and a high-speed operation is made possible with high accuracy of a timing device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to timing i+ttt used in data processing devices such as electronic computers.

Such timing devices often include a timer register that holds a numerical value indicating the remaining time until the R1 fixed point;
114. Indicates the elapsed time from the FJT fixed point. The lowest bit of these registers is, for example, 1 μsl.
□F, so the contents of the timer register include 1μ
The value -1 is added every S, and the value →1 is added every 1 μs to the contents of the TOD register.

Figure 1 is a block diagram showing the conventional layout of this building.
) is the timer register, (2) is the TOD register, (3)
are comparison registers, (4) and (5) are selectors, (6) is an adder, (7) is a carry register, (
8), (9), (10 are selectors, (
11) is a comparator, (1 is a selector, and ζ and η
is the output of timer register (1), (4) is the output of TOD register (2), and each register (n, t2i
.

The number of customers in (3) is 8 bytes and 1. Assign numbers 0 to 7 starting from the lowest digit. The output is 2 bytes of numbers 0 and 1, 3η is the output of 2 bytes of numbers 2 and 3, 0
'3 is the numerical value -1, (41) is the numerical value +1. The sum output of o41-digit adder (6), +35, field 13 is the timer register (
Each input line to 1), 6 is the carry output of the adder (6),
(S)3 indicates the output of the carry register (7).

When setting initial values, the selector (9) is set for one month, and desired values are set in the timer register ill and the comparison register (3), respectively. Next, assuming that P)r constant frequency 1υ1 is 1 μS, 8 steps are set in 1 μs, numbers are numbered from 0 to 7 in the order of the steps, and at the 0th step, the selector (4) is The selector (5) selects the output of the counter (1). The selector (5) selects the 2 bytes numbered 0.1 and adds -1 to it using the adder (6). The sum output (→ selector (9)) After that, it is input to the 2 bytes at number 0.1 of the timer counter (1), and the carry is input to the carry register (
7). In the next step of the first stage, the selector (5) outputs 2.3M bytes of the timer register (1), the selector (8) outputs the signal ≠
) is the output of the 2.3@byte of the timer register (1), and the logic of the signal (g) is "1", and the minus is -] is added, and the signal (if the logic of the full signal is "0", 0 is added. Shiso 111 output (b) passes through the selector (9) to timer counter (1) 2,
No. 3 2 Pies) [Input, and the carry is input to the carry register (7). In this way, when the third step is completed and the time 1 is reached, the value -1 is added to the value of the timer counter (]) and the value is incremented by 7L. Next, in the fourth step, selector (4) 1m, J: selects the output of TOD register (2), selector (5) selects 2 bytes of 0°1, selector (8) selects +1; Select TOi) register (
Add +1 to the 2 bytes at number 0.1 of 2)'P2's a output (3A goes through the selector (9) and goes to the TOD register (2)
It is input to the 2 bytes of O and 1 of ' and is simultaneously input to the comparator (li
) [sum output (binary 2 bytes and comparison register (:+l
O') 0 and the first two bytes are compared, and the carry of the result of the above addition is input to the carry register (7). In the next 519th step, the selector (5) is TO
Select the 2nd and 3rd bytes of D register (2), selector 8) selects the contents of carry register (7), and complete the 7th step in this way.
+1 is added to the 8 bytes of D register (2).

In the conventional timing device, as described above, the process of adding -1 to the contents of the timer register (1) and the process of adding +1 to the contents of the TOD register (2) are processed in series. However, in order to perform high-speed processing, there was a drawback that the wide adders in the bits had to be spaced apart.

This invention was made to eliminate the drawbacks of the conventional ones as described above, and it is possible to obtain highly accurate timing information by performing parallel processing using multiple high-speed adders with a small number of bits 1-1. The purpose is to construct a timing device that can be supplied.

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, (100) is a first logic circuit, (200) is a second logic N path, and the first logic circuit (100) and the 2 logic circuit (
200) have the same structure.

In the figure, (101) is an even number (0) in the timer register.
, 2, 4, 6) byte registers, (201) is the odd numbered (1, 3, 5, 7th) byte register in the timer register, (102") is the odd numbered (102") register in the TOD register. 1, 3, 5, 7M) byte register, (202
) Register of even numbered bytes (0, 2, 4° 6th) in the TOD register, (103) Register of odd numbered bytes (1, 3, 5, 7) in the ld comparison register, (2
03) is an even number in the comparison register (0゜2.4.6)
is a register of bytes. (104).

(204) , f'105) , (205) ,
(108), (208), (109).

(209) , (110) , (210) , (
112) and (212) are selectors, (1,
06) is the first adder, (206) is the second number,
These adders (106) and (2os) receive a numerical value of 0 for 1 byte input. -1. This is an adder that adds +1, and the bit width is halved compared to adder (6) in FIG.

(107) is a first carry register, (207) is a second carry register, (111).

Each comparator (211) has one byte of bits, which is half the number of bits compared to comparator (11) in FIG.

Also (131), (151), (231),
(251) Fi registers (101) and (
102), (2o2), output of (201), (1
32) and (232) are each selector (105)
.

Input to (205), (134), (234) F
i are the sum outputs of adders (106) and (206), (135) and (235), respectively.

(271) are the timer registers (101) and
The inputs to (201), (136) and (236) are respectively the soda machine (106').

Carry output of (206), (152), (252)
are carry registers (107) and (207), respectively.
) output, (153).

(253) are TOD registers (102) and
(202) shows the input.

When setting the initial value, selector (109), (20
9) and register (101), (103)
, (201).

(203) respectively set desired numerical values. The initial value of the registers (102) and (2 (12) is 0. Next, assuming that the predetermined period is 1 μS, if 8 steps are set in 1 μs, the steps are numbered 0 to 7 in order. This is the same as the case of Figure 1 of Asahi. Figure 3 is a timing chart showing the operation of the circuit of Figure 2, and in the figure, the steps of TO~T7Fi are shown. The operation of the circuit in FIG. 2 will be explained with reference to FIG. 3. In step TO, the register (10
Contents of the 0th byte in 1) tζ adder (106) adds -1 and the sum output (134) is added to the selector (109)'
! Input the byte as an input (135) through z, store the carry output (136) in the carry register (107), and at the same time add +1 to the 0th piton contents of the register (202) using the adder (206). Addition sum output (234)
is input to the corresponding input (235) via the selector (209), and the carry output (236) is output to the digit-hit register (207).

In step Tl, the contents of the first byte of the register (102) are added to the carry register (20) by the adder (106).
7) is added and the sum output (134) is input to the byte as input (153) via the Th selector (109), and the carry output (136) is sent to the carry register (1
, 07), and at the same time add -1 to the contents of the first byte of the register (201) when the contents of the carry register (107) is logical "1". In other cases, add 0. The sum output (234) is input via the selector (209) (
253) into the relevant byte, and enter the carry output (23
6) is input into the carry register (207).

In steps T2 to T7, registers (101), (102), (201),
If a similar operation is performed on the 2nd to 7th bytes of (202), the timer register and T
Processing for each 7th byte of the OD register can be completed at the same time.

Also, from step TO to T7, the TOD register (202
).

(102), adder (206), (
106) is stored in the comparison register (203).
), corresponding byte of (103) and comparator (211)
, (Ill).

In the above embodiment, the timer register and TOD register are both composed of 8 bytes and are processed by two 1-byte width adders, but the present invention is not limited to the numerical example described above. it is obvious.

As described above, according to the present invention, the timing device is constituted by a circuit that performs parallel calculations using several small high-speed adders of bit 1], and the plurality of circuits that perform the parallel calculations are mutually connected. Since the circuits are the same and the number of interface signal lines between these circuits is reduced17, the speed can be increased without increasing the amount of hardware, and a high-speed timer can be provided at low cost. There is an effect that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing chart for dividing the operation of the circuit shown in FIG. 2. (100) ...First logic circuit, (200)...Second logic circuit, (101), (2(11)...Timer register, (102). (202')...TOD register, (103), (2
03)...Ratio soft register, (1,06)...First adder, (2(16)...Second power 11 adder, (1,
07)...First carry register, (207)...
・Second carry register, (111), (211)・
...Each comparator. Agent Shin Kuzuno −

Claims (1)

[Claims] A numerical value that compares the magnitude relationship between a timer register to which -1 is added at every predetermined cycle, a time clock register to which +1 is added to at every predetermined cycle, and the contents of the time clock register. In a timing device having a comparison register for timekeeping, each of the above registers is regarded as a cascade of 2m (m is a positive integer) register units of n bits, and the registers are sequentially numbered from 0 to (2m) from the lower digit unit of the cascade. -1), each even numbered register unit in the above timer register, each odd numbered register unit in the above time mechanism register, and each odd numbered register unit in the above comparison register. , a first logic circuit having an 11-bit sugar 1 agenerator, a first carry register, and an n-bit first comparator, and each odd-numbered register unit in the timer register. and a second logic having each of the even-numbered register units in the time clock register, an n-bit second adder, a second carry register, and an n-bit second comparator. Assuming that the circuit has 2m steps within the above-mentioned predetermined period and the steps are numbered from 0th stage to (2m-1)th stage in order,
kth (k=0, 2, 4, =2(m-1))
In the second step, the first adder is used to add k=0 to the contents of the second register unit in the timer register.
If the content of the second carry register is "1", add -1, otherwise add O, input the result to the register unit, and input the carry signal to the register unit mentioned above. Input E7 to the No. 1 carry register, and use the second adder to add the contents of the No. 2 register unit in the time clock register to the case where k = 0 and the case of the first carry register. If the content is "1", add +1, otherwise add 0, input the result to the relevant register unit, and input the carry signal to the upper M+', second carry register. and in the (k+1)th step, the content of the second carry register is added to the content of the (k+1) register unit in the time clock register using the first adder. input the result into the register unit, input the carry signal into the first carry register,
And if the content of the first carry register is "1", add 11 to the content of the (k+1) register unit in the timer register using the second adder, and so on. In the case of , O is added and the result is input to the register unit I - means for inputting the carry signal to the second carry register; - the contents of each register unit of the time clock register are updated; 4. A timing quadrature arrangement comprising: means for comparing the contents of a corresponding register unit of a comparison register with each time a comparison register is stored.