JPS5875133A - Charging voltage detecting circuit of flash gun - Google Patents

Abstract

PURPOSE:To detect charging voltage of a main capacitor by converting it to digital information without using a regular A-D converting circuit, by detecting said charging voltage by use of an oscillating circuit containing a neon tube which flickers on frequency corresponding to said voltage. CONSTITUTION:Between working voltage supply lines L1, L2 of a flash gun, a series circuit of a resistance R1 and a capacitor C2 is provided in parallel with a main capacitor C1, and to a connecting point of the resistance R1 and the capacitor C2, one end of a neon tube Ne is connected. When a main switch SW1 of the flash gun is turned on, the neon tube Ne flickers repeatedly jointly with the capacitor C2. The flickering period of the neon tube Ne, that is to say, the oscillating period becomes shorter as charging voltage of the main capacitor C1 becomes higher, therefore, by detecting the flickering period of the neon tube Ne by turning and off a transistor TR1, information of a charged state of the main capacitor C1 can be fetched.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a charging voltage detection circuit for a flashlight, and more specifically, a charging voltage detection circuit for a flashlight, and more specifically, a charging voltage value for a main capacitor.
The present invention relates to a charging voltage detection circuit for a flash light emitting device that can obtain digital information values without using a conversion circuit.

In recent years, automatic exposure cameras have been put into practical use that have a so-called AE lock function, which stores automatic exposure shooting conditions and allows multiple frames to be taken using the stored shooting conditions. It is already well known that it is widely used as a means of However, what can be done with a conventional auto exposure camera with an AE lock function is
The worst part is AE lock photography against natural light, and an automatic exposure camera that also remembers the amount of light emitted by the flash device during flash photography and regenerates the flash with the same amount of light has not yet been put into practical use.

By the way, the light emitting capacity of a flashlight emitter is determined by the charging voltage of the main capacitor when the flashlight discharge tube starts emitting light and the discharge time of the flashlight discharge tube. All that is required is to memorize the voltage and discharge time. These detection means are required as a prerequisite for storing the charging voltage and discharging time.

In view of the above-mentioned points, an object of the present invention is to convert the charging voltage of the main capacitor into digital information and detect it by skillfully utilizing an oscillation circuit including a neon tube that blinks at a frequency corresponding to the same voltage. The present invention provides a charging voltage detection circuit for a flashlight emitter.

According to the present invention, since the charging voltage of the main capacitor can be obtained as the blinking period or blinking frequency of the neon tube, the charging voltage of the main capacitor can be converted into digital information and detected without using a normal A-D conversion circuit. can do. Therefore, the circuit configuration is extremely simplified, and it can be easily installed even in cases where there are severe limitations on space, cost, power supply, etc., such as in the case of flashlight emitters.

Hereinafter, the present invention will be explained based on an illustrated embodiment.

FIG. 1 shows an electrical circuit of a flashlight emitter, which is equipped with a charging voltage detection circuit according to an embodiment of the present invention. This electric circuit includes a power source E1 such as a dry battery and a main switch SW.
1, and is provided with a DC-DC converter 1 that boosts the electromotive voltage of a power source such as a dry battery to a high voltage of about aoo V, and this DC! - operating voltage supply lines l, , L, drawn out from the DC converter 1;
In between, both lines L1. DC supplied through L2
-11) A main capacitor CI charged by the boosted voltage from the C converter 1 is connected. A series circuit of a resistor R1 and a capacitor C2 is provided in parallel with the main capacitor C3, and one end of the neon tube Ne is connected to the connection point between the resistor R8 and the capacitor C2. The other end of the neon tube Ne is connected to the base of an NPN transistor Tr+, and the emitter of the transistor Tr+ is connected to the line L1. In addition, the collector of the transistor Tr+ is connected to the input terminal of the inverter IN, and a constant voltage of about 6V for driving the IC +VDD is connected through the resistor R3.
It is connected to the positive voltage end of a constant voltage circuit that generates voltage, and receives the voltage applied by the constant voltage element VDD. The constant voltage circuit includes a resistor R2 and a Zener diode ZD connected between lines L and L2.

It is formed by a series circuit of Zener diode ZD
, and a voltage stabilizing capacitor C7 is connected in parallel with the voltage stabilizing capacitor C7.

The neon tube Ne cooperates with the resistor R1 and capacitor 02 to repeatedly blink at a period corresponding to the charging voltage of the main capacitor C3, and corresponds to the charging voltage of the main capacitor C1. It constitutes a type of oscillation circuit that oscillates at a certain frequency. That is, the second
As shown in the figure, one end of the resistor R1 is connected to the positive side of the main capacitor CI.
A voltage corresponding to the charging voltage of the main capacitor C1 is charged to the capacitor C2 through the resistor R1, and when the charging voltage of the capacitor 02 reaches the lighting voltage of the neon tube Ne, the neon tube Ne lights up and a voltage is applied to the base of the transistor Tr1. The lighting current flows through the transistor Tr.
+ turns on. When the neon tube Ne continues to be lit, the charge in the capacitor C2 becomes a lighting current for the neon tube Ne and is discharged, and the charging voltage of the capacitor C2 decreases. When the charging voltage of the capacitor 02 reaches the extinguishing voltage of the neon tube Ne, the neon tube Ne can no longer remain lit and goes out. Then, capacitor C2 becomes resistor R again.
8, and when the charging voltage reaches the lighting voltage of the neon tube Ne, the neon tube Ne lights up again. In this way, the neon tube Ne can repeatedly blink. Therefore, this resistor R1, capacitor 〇2 and neon tube Ne
constitutes a kind of oscillation circuit.

The blinking period, that is, the oscillation period, of the neon tube Ne is the third
As shown in the figure, the higher the charging voltage of the main capacitor C1, the shorter the charging voltage becomes. Therefore, if the blinking cycle of the neon tube Ne is detected, information on the charging state of the main capacitor 01 can be extracted. be able to.

Therefore, in the charging voltage detection circuit of the present invention, the neon tube Ne
The above information is extracted by turning on and off the transistor Trx depending on the presence or absence of the lighting current. That is, the resistor R1, the capacitor C2, the neon tube Ne, and the transistor Trl constitute a voltage-frequency conversion circuit for the charging voltage of the main capacitor C1.

Returning to FIG. 1 again, the inverter IN□, whose input terminal is connected to the collector of the transistor Tr1, connects its output terminal to one input terminal of the NAND circuit Nl), the input terminal of the inverter 1N2O, and the inverter IN□ (- are connected to the input terminals of the inverter IN3.
-The output terminal of IN2 is an AND circuit AD.

The other input terminal of the NAND circuit ND is connected to the other input terminal of the NAND circuit ND through the resistor R4, and the other input terminal of the NAND circuit ND is connected to the inverter I.
Output level of N2 (hereinafter referred to as "I" level) Color low level (hereinafter referred to as "L" level)
When it is inverted, the NAND circuit ND.

It serves to delay the transition of the other input terminal of ND to L'' level by a predetermined period of time, and to generate a pulse-like latch signal of 6L'' level at the output terminal of NAND circuit ND. The time width t1 of this latch signal (see FIG. 4(b)) is determined by the resistance R
It is proportional to the product of the resistance value of C4 and the capacitance value of capacitor C4.

The output terminal of the above inverter INs is the inverter I
The other end of the resistor island is connected to the other input end of the AND circuit AD, and is also connected to the line L through a capacitor C6. A discharge diode D1 is connected in parallel with the resistor R7, and one input terminal of the AND circuit AD is connected to the output terminal of the NAND circuit ND. The resistor R3 and capacitor C6 prevent the other input terminal of the AND circuit AD from changing to the ``11'' level when the output of the inverter IN is inverted from the ``L'' level to the ``H'' level. Delay, AND circuit A
It serves to delay the generation of the reset signal generated at the output terminal of D. This delay time width t2 (see FIG. 4(C)) is proportional to the product of the resistance value of the resistor R6 and the capacitance value of the capacitor C3 (7). And the diode D1 is
The output of inverter IN goes from “II” level to ILL.
"When the level is inverted, the charge in the capacitor C6 is rapidly discharged through the diode D1, and almost at the same time as the output of the inverter IN is inverted, the AND circuit AD is inverted.
, serves to stop the reset signal output from .

On the other hand, one input terminal of the AND circuit AD2, in which the output terminal of the inverter IN2 is connected to the other input terminal, is connected to an oscillation circuit that generates a clock pulse for timing the extinguishing time width of the neon tube Ne. ing. This oscillation circuit is an inverter IN.

~IN,, is composed of a resistor RJ and a capacitor 〇〇, and the output terminal of the inverter IN is the inverter IN.
60 input terminal, the output terminal of inverter IN is connected to the inverter IN70 input terminal, and the inverter I
A resistor R6 is connected between the output terminal of N7 and the input terminal of the inverter IN, and a capacitor 06 is connected between the output terminal of the inverter IN6 and the input terminal of the inverter IN. The output terminal of the inverter IN is the output terminal of the oscillation circuit, and the AND circuit AD,
is connected to one input end of the The AND circuit AD serves as a gate circuit that allows the output of the oscillation circuit to pass only when the output of the inverter IN2 is at "H" level.

The output terminal of the AND circuit AD2 is connected to the clock signal input terminal of a 4-bit binary counter 5, and the counter 5 counts up clock pulses input from the oscillation circuit. The reset signal input terminal of this counter 5 is connected to the AND circuit AD,
It is connected to the output terminal of the circuit AD, and is reset by a reset signal output from the same circuit AD. And each data of the binary counter 5 - output terminal Q. -Q is connected to each data input terminal of the 4-bit latch circuit 6, and the latch signal input terminal of the latch circuit 6 is connected to the output terminal of the NAND circuit ND.

The counter 50 count and reset timing, and the latch timing of the latch circuit 6 are shown in FIGS.
) will now be explained in some detail with reference to the time chart shown in ( ). Main capacitor〇.

After the charging voltage of the capacitor C2 reaches the lighting voltage of the neon tube Ne and the neon tube Ne lights up, when the neon tube Ne goes out again, the transistor Tr
1 is turned off and the input terminal of inverter IN becomes "ti".
level. Therefore, as shown in Figure 4(a),
The output of inverter IN is inverted to 'L' level, the output of inverter IN2 becomes 11' level, the gate of AND circuit AD is opened, and inverter IN, ~I
The oscillation output of the oscillation circuit consisting of N, etc. is input to the binary counter 5. Therefore, the binary counter 5 starts counting clock pulses. After the neon tube Ne is turned off, the main capacitor C8 is charged again, and when the neon tube Ne is turned on, the transistor Trl is turned on and the input terminal of the inverter IN becomes ``L'' level.

Therefore, the output of the inverter It-IN is
), the output of inverter IN2 becomes 'L' level, the gate of AND circuit AD2 closes, and the clock pulse from the oscillation circuit is supplied to counter 5. (Then, the clock pulse count ends. The counter 50 count contents at this end point represent the extinguishing time width of the neon tube Ne in units of one period of the clock pulse. At the same time, when the "H" level output of the inverter IN is applied to one input terminal of the NAND circuit ND, the other input terminal of the NAND circuit ND is still '' due to the delay circuit of the resistor R2 and the capacitor C1. Since it is at the "H" level, the output of the NAND circuit ND changes to the "L" level, and after the elapse of time t obtained by the delay circuit, the other input terminal of the NAND circuit ND changes to the "7L" level. As the output of the NAND circuit ND increases, the output of the NAND circuit returns to the ``)I'' level again. Therefore, the Ll level output of the NAND circuit ND is applied as a latch signal to the latch circuit 6, and the circuit 6 receives the 50 count contents of the pi-terry counter.
Latch. And when the neon tube Ne goes out again,
Counting of the next clock pulse begins. In this way, each time the neon tube Ne is turned off, a clock pulse is counted by the counter 5, and this clock pulse is counted by the latch circuit 6.
is latched to. Therefore, the J latch circuit 6 always holds information corresponding to the latest extinguishing time of the neon tube Ne, and this information corresponds to the charging voltage of the main capacitor 〇.

Each data output terminal of the latch circuit 6 is connected to each data input terminal of another 4-bit latch circuit 7, respectively. This latch circuit 7 is a charging voltage storage means, and its latch signal input terminal is connected to a latch control circuit of the circuit 7.

In this latch control circuit, a series circuit of a capacitor C7 and a resistor RyiRs is provided between lines L and L2, and the connection point between resistors R1 and R8 is connected to the gate of a field effect transistor FET. . The transistor PET has a source connected to the 2-in L, and a drain connected to the operating voltage +V from the constant voltage circuit through the resistor R.
DD is being applied. Also, transistor FET
The connection point between the drain of t and the resistor is a NAND circuit ND2
The other input terminal of the second circuit ND2 is connected to the line L through a resistor R1o.

The above operating voltage +VDD is applied via the storage command switch SW2.
is applied. Further, the output terminal of the NAND circuit ND is connected to the other input terminal of the NAND circuit ND4, and the NAND circuit ND is connected to the NAND circuit ND,
Together, they constitute an RS flip-flop circuit. That is, the output terminal of the NAND circuit ND4 is connected to the other input terminal of the NAND circuit ND, and the output terminal of the NAND circuit ND3 is connected to the other input terminal of the NAND circuit ND.
D, respectively. One input terminal of the NAND circuit ND receives an operating voltage VDD through a resistor R1, and is connected to a line L1 through a memory release switch SW. The output terminal of the NAND circuit ND4-, which is the output terminal of the latch control circuit, is connected to the latch signal input terminal of the latch circuit 7 and one input terminal of the AND circuit AD, respectively.

Such a latch control circuit has a memory command switch SW2.
with the memory release switch SW open,
When a flash discharge tube F, which will be described later, emits a flash, the charge in the capacitor C1 is discharged through the discharge tube F → resistor R8 → resistor R1, and the gate of the field effect transistor F RT is reverse biased, causing the transistor Fri, ,
The drain-source resistance becomes high (> Rs+),
As a result, one input terminal of the NAND circuit ND2 becomes H" level. Therefore, the output of the NAND circuit ND2 becomes "L".
The output of the NAND circuit ND4 is inverted to the H'' level, and the count contents held in the latch circuit 6 are latched by the latch circuit 7.
Since the RS flip-flop circuit consisting of 3°ND is set, from now on, unless the memory release switch SW is closed, even if the memory command switch SW2 is opened, the flash discharge tube F will not flash again. However, the contents of the latch circuit 7 do not change, and the latched state is maintained. However, when the memory release switch SW is closed, one input terminal of the NAND circuit ND3 becomes "L" level, the R8 flip-flop circuit is reset, and the output of the NAND circuit ND is
It becomes L'' level, and the latched state of the latch time m7 is released.

Each data output terminal of the latch circuit 6 is connected to one input terminal of exclusive OR circuits EOR1 to FOR4, and each data output terminal of the latch circuit 7 is connected to an exclusive OR circuit. EOR1～EOR
4, respectively. and,
The output terminal of each exclusive OR circuit EOR, ~EOI(, is connected to each input terminal of the NOR circuit NR,, respectively, and the output terminal of the NOR circuit NR,, is connected to the other input terminal of the AND circuit AD3. The AND circuit AD sends a control signal to the DC-DC converter 1 only when the latch circuit 7 is in the latched state and the contents of the latch circuit 7 and the contents of the latch circuit 6 match. The output terminal is connected to the control signal input terminal of the DC-DC ninverter 1.

Therefore, the above exclusive OR circuit FOR, ~EO
R,, NOR circuit NR,, AND circuit AD, etc. are DC-
The DC-DC converter 1 constitutes a step-up operation control means for the DC converter 1, and the DC-DC converter 1 has an "H" signal at the control signal input terminal.
``When a level control signal is applied, the oscillation operation for boosting the voltage is stopped.

On the other hand, the flash discharge tube F has a main thyristor SCR, and a diode r between the lines L1 and L2.
) 3 to form a series circuit. The trigger circuit for causing this flash discharge tube F to emit flash light is as follows:
Resistor R7-2 to R, , capacitor c8. c',,
It is composed of a Zener diode ZD, a thyristor SCR, a diode D2, and a trigger transformer T1. That is, in this trigger circuit, a resistor R12 and a Zener diode Z are connected between the lines L and L2.
Series circuit consisting of D2, resistor R83, and thyristor SC
R,, and a series circuit consisting of a diode D2 are connected to each other, and the resistor R62 and the Zener diode ZD are connected to each other.
A capacitor C8 is connected between the connection point between the thyristor SCR and the diode D2 and the connection point between the thyristor SCR and the diode D2. Further, resistors R14 and R13 are connected between the gate of thyristor 8CR and the above 24758, and between the gate and cathode of thyristor 'SCR, respectively. Furthermore, one of the above trigger transformers
One end of the primary coil and one end of the secondary coil are connected in common to the cathode of the thyristor S (, R), and the other end of the primary coil is connected to the resistor R1 via the capacitor 〇.
, and the thyristor 8CR, and the other end of the secondary coil is connected to the trigger electrode FT of the flash discharge tube F. In order to operate the trigger circuit, a light emission command switch SW4 is connected in parallel with the Zener diode ZD2. This light emission command switch SW4 may be a synchro switch provided on the camera, or may be a test light emission switch provided on a flashlight emitter.

In the trigger circuit, when the light emission command switch SW4 is closed, the electric charge of the capacitor C8, which has been charged in advance with the polarity shown in the figure, is transferred to the light emission command switch SW, -+resistor R1.
4, "j I! J Star 8CR, <7) Gate → Discharge via the cathode of the same thyristor S CR,
Thyristor 5CR1 is triggered. This results in
The same thyristor SCR, ignites, and this time, the electric charge of the capacitor C0, which had been charged in advance with the polarity shown in the figure, is discharged in the path of the thyristor SCR,, → trigger transformer T, and the primary coil of trigger transformer TI. A high voltage trigger pulse is generated in the secondary coil and applied to the trigger electrode FT of the flash discharge tube F.

The flash discharge tube F is controlled to emit light by a series control method, and as mentioned above, it forms a series circuit with the main thyristor 8CR2 and the diode D, and the line L
,,L, are connected between. And the resistance R1,
A capacitor is connected between the connection point of and thyristor SCI't, and the connection point of the thyristor SCR and diode D. and a resistor R16 are connected, and resistors R17 and R88 are connected between the gate of the thyristor SCR, and the cathode of the line L1 and the thyristors 8CR and 2, respectively, A circuit for triggering the thyristor 5CR2 is formed.

The circuit for triggering this thyristor S CR is activated simultaneously when the trigger circuit γ is activated, and when the thyristor 8 CR is made conductive, it is charged in advance with the polarity shown in the figure. The charge of the capacitor C1o is the thyristor 5C)t, →
Diode D2 → Resistor R1 → Gate of thyristor SCR → Thyristor SCR.

The cathode of the thyristor 5 is discharged through the path of the resistor R86, and as a result, the thyristor 5CR2 is given a trigger pulse to its gate and becomes conductive. When the thyristor SCR,2 becomes conductive, it discharges and emits flash light.

A commutation circuit for making the thyristor 5CR2 non-conductive is connected to the line L1. A diode D3.L2 connected between the diodes D3. A series circuit consisting of resistor R21, thyristor 8 CR3 and diode D4, and thyristor SC
A commutation capacitor C11 connected between the anode of R2 and the anode of the thyristor 5CR3, a resistor R1° connected between the anode of the thyristor 5CIt2 and the line Ij1, and the thyristor 8CR.

and a resistor R2o connected between the gate of the line L1 and the line L1. The capacitor C7° of this commutation circuit is
The thyristor SCR is charged in advance to the polarity shown in the figure, and when the dimmer circuit described later operates and the thyristor SCR becomes conductive, the charged voltage is applied to the series circuit of the thyristor 5CR2 and the diode D3 with the opposite polarity, and the thyristor SCIt2 is turned off.

The dimming circuit 8 that triggers the thyristor SCR is already well known and is connected between the lines L1 and R2, and one line drawn out from the circuit is connected to the cathode of the thyristor 5CR8. has been done. This light control circuit 8 operates when the photometry light receiving element PT1 of the flashlight unit connected to the circuit receives a specified amount of light, or when the camera understands and a light control signal is applied.
Resistor R2o → gate of thyristor 5CR3 → thyristor SCR.

The thyristor SCR is triggered through the cathode of the thyristor SCR.

As described above, the charging voltage detection circuit for a flashlight emitter of the present invention is configured.

Next, the operation of this charging voltage detection circuit will be explained.

First, when the main switch SW of the flashlight emitter is turned on, the power source E1 is connected to the DC-DC converter 1, and the converter 1 starts voltage boosting operation.

Therefore, an operating voltage is supplied between the operating voltage supply lines L, , L, and charging of the main capacitor C1 to the commutating capacitor CI+ starts with the polarity shown.

Further, a constant voltage circuit formed by the Zener diode ZD□ operates, and an operating voltage +VDD is supplied to each IC element such as the inverter IN in the electric circuit of FIG. 1, so that each element becomes in an operating state. At this time, since the neon tube Ne is not lit, one transistor is off, the output power of the inverter IN is at the "L" level, the output power of the inverter N2 is at the "H" level, and the gate of the AND circuit AD2 is opened. The oscillation output of the oscillation circuit including inverters IN, -IN7, etc. is applied to the binary counter 5 as a clock pulse.

Therefore, the binary counter 5 starts counting, but the latch circuit 6 does not latch the contents of the counter 5 because the output of the NAND circuit ND is at the IT'' level.

As charging of the main capacitor C1 progresses and the charging voltage of the capacitor C2 reaches the lighting voltage of the neon tube Ne, the neon tube Nc lights up and the transistor Tr
, turns on and shows K in Fig. 4(a).

The output of the inverter IN becomes "H" level, the output of the inverter N2 becomes "L" level, the gate of the AND circuit AD2 is closed, and the 50 count of the pie counter is stopped.Also, at the same time, , 4th
As shown in Figure (b), a NAND circuit ND.

A 'L' level latch signal with a time width of time constant t determined by resistor R4 and capacitor C4 is generated at the output terminal of , and based on this, the latch circuit 6 outputs the contents of the counter 50 output. Then, further resistor R
6. When the second time t2 determined by the capacitor 〇 has elapsed,
As shown in FIG. 4C, at 6, a reset signal of nHn level is generated at the output terminal of the AND circuit AD, and the count contents of the binary counter 5 are reset.

When the neon tube Ne is turned on, the charge in the capacitor 02 is discharged, and the charging voltage of the capacitor 02 becomes equal to or lower than the extinguishing voltage of the neon tube Ne, and the neon tube Ne is turned off again. Then, the transistor Tr1 is turned off, and as shown in FIG.
” level, the input of the clock pulse to the counter 5 is resumed, and a new count of the counter 5 is started. Furthermore, the neon tube Ne is turned off, and charging of the capacitor C2 is restarted, which causes the clock pulse to be input again to the counter 5. When the charging voltage of the capacitor C2 reaches the lighting voltage of the neon tube Ne, the neon tube Ne lights up. Therefore, the transistor Tr+ is turned on and the output of the inverter IN1 goes to the II'' level as shown in FIG. 4(a). So, binary-
At the same time as the counter 50 count is stopped, the state shown in Fig. 4 (
As shown in bl, at the output end of the NAND circuit N
A latch signal of l and 11 levels is generated, and the latch circuit 6 latches the new count contents of the counter 5.

In this way, the latch circuit 6
The count of clock pulses corresponding to the light-off time is always maintained. As already mentioned, the extinguishing time of the neon tube Ne becomes shorter as the charging voltage of the main capacitor C1 increases, as shown in FIG.
has a unique functional relationship with the charging voltage. Therefore,
The contents latched by the latch circuit 6 represent the charging voltage of the main capacitor C1.

The latest main capacitor C is installed in such a latch circuit 6.
From the state where the charging voltage of I is maintained, the flash discharge tube F
In order to memorize the charging voltage of the main capacitor C3 at the time of flash emission, first press the memory command switch SW2.
Close manually. Then, the other input terminal of the NAND circuit ND2 becomes H'' level, and the NAND circuit ND2 inverts the drain potential of the field effect transistor FET applied to one input terminal of the NAND circuit ND2. The current is applied to the other input terminal of ND.

Next, when the light emission command switch SW is closed, the thyristor 5crt is
becomes conductive, and a high voltage is applied to the trigger electrode FT due to the discharge of the charge in the capacitor 〇, and at the same time, the main thyristor 5CR is activated due to the discharge of the charge in the capacitor CIO.
2 is ignited, and the main capacitor C is connected to the flash discharge tube F.
When a charge of 1 is charged, a flow discharge is started. At this time, the charge in the capacitor C7 is also discharged through the flash discharge tube F, thereby reverse biasing the base of the field effect transistor FET. For this reason, the resistance between the drain and source of the transistor FET becomes high, and as a result, one input terminal of the NAND circuit ND2 becomes the "H" level, and the other input terminal of the NAND circuit ND becomes the "LIT level". .

Therefore, NAND circuit ND3. The RSS flip-flop circuit consisting of NAND circuit ND is set to the "11" level at the output terminal of the NAND circuit ND, the latch signal input terminal of latch circuit 7 becomes "H" level, and latch circuit 7 becomes a latch circuit. Transfer and save the count contents held in 6.

hold

On the other hand, in the camera's TTL photometry circuit, the flash discharge tube F
It receives the light emitted from the camera and reflected by the subject, and issues a dimming signal when the appropriate scene is received on the film surface. Further, the time up to the time when this dimming signal is obtained is stored as the dimming time. The dimming signal is transmitted to the flashlight emitter through a transmission terminal (not shown), and is applied to the dimming circuit 8 as an external dimming signal. For this reason, thyristor S
([3 is triggered, the same thyristor S CR3 becomes conductive, and the main thyristor ~ S CR2 is reverse biased by the charge of the commutation capacitor C1t. Therefore, the thyristor 5CR2 becomes non-conductive, and the flash discharge tube F
The discharge is stopped and the flash light emission ends.

Next, when the charging voltage of the main capacitor C4, which has decreased due to the flash emission of the flash discharge tube F, rises again due to the step-up operation of the DC-DC converter 1, the charging voltage of the capacitor Cρ also increases, and finally the charging voltage of the neon tube Ne increases. Reach lighting voltage. As a result, the neon tube Ne starts blinking again, and the counter 5 counts clock pulses corresponding to the extinguishing time of the neon tube Ne, and the clock pulses are latched into the latch circuit 6. And the previous flash discharge tube F
When the charging voltage of the main capacitor 0 increases to the charging voltage of the main capacitor 01 at the time of flash emission, the contents of the latch circuit 6 come to match the contents of the latch circuit 7. When the contents of both latch circuits 6 and 7 match, exclusive OR circuits EAR, ~gOR,
All the outputs of the NOR circuit NR become 'L' level, and the output of NOR circuit NR is inverted to 'II' level. Therefore, the output of the AND circuit AD3 changes to the "II" level, and a signal of the "1]" level is input to the control signal input terminal of the DC-DC converter 1, and the DC-DC converter 1 stops the boost operation. Then, when the charging voltage of the main capacitor C1 decreases again due to lighting of the neon tube Ne or natural discharge, etc., the content latched in the latch circuit 6 becomes different from the content held in the latch circuit 7, and the exclusive OR At least one of the outputs of circuit 1:OR, 1 to f':011.4 is at the "use" level, and the NOR circuit N1? ,,
The output returns to "L" level. As a result, the output of the AND circuit AD3 becomes "L" level, and I) C-1
) (: Converter 1 connects "11" to the control signal input terminal.
''' The application of the level signal is removed and the boost operation starts again. Therefore, in this way, the charging voltage of the main capacitors C and Y is equal to the charging voltage at the previous flash emission of the flash B detonator F. 1. Therefore, if the light emission command switch SW4 is closed from this state, the flash discharge tube F starts emitting flash light under almost the same conditions as the previous flash light emission. This flash discharge tube F
is stopped from discharging by an external dimming signal applied to the dimming circuit 8 when the previous discharging time stored in the camera's TTL photometry circuit has elapsed. Therefore, the flash discharge tube F has the same main capacitor c as the previous flash.
Under a charging voltage of 1, intermittent light is emitted for the same discharge time as in the previous flash, so the flash will eventually be emitted with the same amount of light as the previous flash. This state in which the flash discharge tube F emits a flash with the same amount of light as the previous time continues even during the burnout unless the memory release switch SW is closed.

In order to release the stored state of the charging voltage of the main capacitor 〇, it is sufficient to close the storage release switch sw. (Then, one input terminal of the NAND circuit ND3 becomes L"
The RSS consists of Lemill and a NAND circuit ND3°Nn.
Flip Flora circuit sets the output terminal of NAND circuit ND to L”
is reset to the level state, the latch state of the latch circuit 7 is released, and the gate of the AND circuit AD3 is closed. If the voltage is equal to or higher than the light emission starting voltage, the flashlight emitter returns to a state in which the discharge tube F can emit flash light at any charging voltage level.

As mentioned above, according to the present invention, the charging voltage of the main capacitor is detected using an oscillation circuit including a neon tube that flashes at a frequency corresponding to the same voltage.
To provide a charging voltage detection circuit for a flashlight emitter, which is extremely convenient in use and can detect the charging voltage of a main capacitor by converting it into digital information without using an ordinary A-D conversion circuit. , can be done.

In the above embodiment, the clock pulses are counted during the period when the neon tubes are turned off, but it is of course possible to count the clock pulses during the periods when the neon tubes are turned on.

Further, although the number of bits of the counter for counting clock pulses was set to 4 bits, it goes without saying that the precision can be further improved by increasing the frequency of the clock pulses and increasing the number of bits of the counter.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram of a charging voltage detection circuit for a flashlight emitter, showing an embodiment of the present invention. FIG. 2 is a voltage-frequency conversion circuit in the charging voltage detection circuit shown in FIG. 1 above. FIG. 3 is a diagram showing the relationship between the charging voltage of the main capacitor and the blinking cycle of the neon tube in the voltage-frequency conversion circuit shown in FIG. 2, and FIG. (a) to (C) are
2 is a time chart showing the relationship between clock pulse counting and latch timing, and count reset timing in the charging voltage detection circuit shown in FIG. 1 above. C3... Remain capacitor C2... Capacitor (oscillation circuit) Ne...
Neon tube (oscillation circuit) Itt...Resistance (oscillation circuit) Trs...-Transistor (C) ADI m-19

Claims (1)

[Claims] An oscillation circuit that oscillates by the flashing operation of a neon tube is connected to the main capacitor, and the oscillation cycle or oscillation frequency of the oscillation circuit, which changes as the charging voltage of the main capacitor increases, is detected, and the main capacitor is charged. A charging voltage detection circuit for a flashlight emitter, characterized in that it detects voltage.