JPS5859677A - Picture signal processing circuit - Google Patents

Abstract

PURPOSE:To efficiently execute reduction, expansion, etc. of a picture by a field memory of small capacity, by controlling a writable field memory by a write and read-out timing signal of a field memory controlling circuit. CONSTITUTION:In accordance with a horizontal synchronizing signal HSSYNC of a sub-picture, a frequency divider 2803 obtains a pulse of phiSO=440fHS (fHS is frequency of the signal HS). In accordance with this signal phiSO, a signal for controlling luminance of a sub-picture signal, and a field memory of a color signal is generated from counters 2815, 2816, a field memory control signal generating circuit 2817, and a 1/2 reduction timing generating circuit 2818. As a result, a prescribed data of a 1H period portion of the sub-picture can be written in a 1H period of the sub-picture, and a data of a 2H period portion of the sub- picture written within a 1H period of a main picture can be read out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an i11 signal processing circuit that performs image signal processing on a plurality of input image signals. Perform multiple functions (=suitable 9 iii *
Related to signal processing circuits.

Input 1 as a general processing signal and a pair of special processing.
Processing to enlarge or reduce the social signal to an arbitrary thickness of 62, and display it.
Typical examples include rotation and static processing of projected images. FIG. 1 shows an example of 1-line processing in which the image data is reduced from the projected image size 4; main 1i1111 and data compression-2, and a sub-picture rkJ2 is displayed in synchronization with the main screen. In this case, 1 displays the rigid surface in synchronization with the main screen;
For sub-screen exposure, processing is required to reduce the image data density of the corresponding input signal. Furthermore, data interpolation processing is required when the sub-screen 2 is enlarged and displayed.

FIG. 2 shows a conventional image signal processing circuit for generating a compressed signal of input image signal data for ml iir no. 42. M z Figure 6=, sampling frequency 47go (/mo: color 1II Wi transmission frequency 3.58
ζ28-bit acid sampled at MHz):
The quantized one-screen digital signal 3 is sent to an input switching circuit 4
This input switching circuit 4 supplies two sub-picture digital signals per field via signal paths 5.6 to each field terminal 7.8 and the data of these field terminals 7.8. Day! via signal path 9.10! The processing circuit 111 is supplied with data and performs arithmetic processing on the data required to be displayed on one screen. Further, the data processing circuit 11 generates a switching signal 12 that switches the input switching circuit 4 for each field, so that when the L field memory 7 is in the write mode, the other L field memory 8 is in the read mode. The data for each field is stored in the field memory 7.8, and this data is used to obtain data 13 for sub-screen display. Using multiple memories - My signal processing WII (2) can store 1 field (2 memories) and can perform data correlation calculations between fields; however, by using multiple field memories, address When the circuit configuration of @ path becomes multiple a', the arithmetic operation circuit becomes complicated.At9 has the disadvantage that only a single correlation operation can be performed.

Fig. 3 shows how the circuit shown in Fig. 2-2 is used to solve the problem of having multiple 1-field peaks. Y, B-Y (two converted, these signals 14
is passed through the multiplexer 15 to Φ converter 166;
be guided. At this ζ, the output of the multiplexer tS is A/
D:! The signal 17 is sampled at a sampling frequency of approximately @4Mklz (2, 6 bit quantized signal 17 is obtained. From this signal 17, a signal corresponding to the reduction ratio of 62 is sampled and calculated. circuit 18
0 thus extracted by the contraction -/IS! !
Indication 1=Only the necessary data is supplied to field memory 204 via signal path 19. field memory 20
g::The written data is read out from a predetermined timing block and guided to the buffer circuit 72 via the signal path 21t, where it is stored in memory. This buffer circuit 224: The nine data stored in the memory are stored on the main screen (=signal path 2 in synchronized predetermined timing).
3, and sends it to the D/A 5 parter 24.
4; Therefore, it is converted into an analog signal and pre-emptively displayed on the screen 1; The necessary signal is obtained from the signal path 25 (:). In this way, 1U Figure 3 C:
In the conventional image signal processing circuit shown in FIG. 9, although the field memory circuit can be reduced, the related calculations depend only on the extracted calculation circuit 18I; Function - Bi-constrained. Therefore, the reduction ratio of the 62 sub-screens that can be outputted is determined by an arithmetic circuit, and the degree of freedom in setting the sub-ratio is restricted (2). The circuit shown in the figure (: Therefore, the function of enlarging and displaying the image on the sub-screen cannot be achieved.

Also, the image signal processing circuit shown in Figure 3: similar circuits are rljAu, Vol C1-25, TIeb, '
79 Michi.

Masuda etal 11i1ully Digmouth a1iged I'etura tnPicture@
Although Te1evision 8y@t@m J 6= is written, it still has the above-mentioned problems.

The present invention has been made in view of the above two points, and is capable of performing multi-mode image data processing such as image reduction, enlargement, and stilling for the main screen and 62 sub-screens with a small field capacity. The purpose is to provide an image signal processing circuit.

(Summary of the present invention) The present invention provides a predetermined horizontal, -
By sampling signals in direct cycles, performing a single correlation calculation on these signals, writing this result to the field meter, and performing a second correlation calculation to control the gun protrusion data of this field meter. One of the points is to control the size of the projected image. That is, by selectively controlling the combination of the first correlation calculation and the second correlation calculation, the size of the displayed image can be adjusted horizontally, and the image can be reduced or enlarged using a small field memory. In addition, in the present invention, the above-mentioned correlation calculation is performed between adjacent picture elements for the video signal, and correlation calculation 1; Make it one.

(Embodiments of the Invention) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The image signal processing circuit according to the present invention can compress and expand sampled data by performing a first correlation calculation and then a second correlation calculation on an input video signal. This is one of its characteristics. In this way, by performing correlation calculation multiple times on the input image signal via the field memory, it is possible to reduce or enlarge the projected image by controlling the data compression ratio or data expansion ratio. means to do so. Furthermore, if writing to the field memory I is stopped and reading is continued, a static AIII memory is obtained, but in this case, by using a new circuit configuration for the address access means for the field memory I It makes it possible to obtain one person that is stationary over two periods.

That is, the present invention performs multi-mode image display by efficiently performing correlation calculations and field memory (two data accesses) by sampling the input nine data signals, and performing data indexing and interpolation for two nine data sections. I can do it.

Figure 4 shows the display positional relationship of the image signal processing circuit of this embodiment, which is processed and displayed. It is assumed that there are two types of video signals, and the image corresponding to the main signal-2 is called main 1Iii@, and the image corresponding to the sub-signal-2 is called sub-1iIivIJ. In the same figure, the main screen is normally displayed on the entire surface of the display device CRT, which is attractive;
A subscreen is inserted and displayed. This inserted sub-screen is usually located at P to P4 in the figure (two displays are made,
The display is performed at the full screen size based on the size of the lii screen.
It can also be set at the center position of one screen (two-line small size can be enlarged and displayed).As will be described later, the display image can be set at the center position of one screen. , by continuing to display images one after another, it is possible to stop the displayed image on either the main screen or the sub-screen.

Such reduction and enlargement display of the input video signal is performed by the first and second correlation calculation circuits. In this case, a $1 correlation operation is performed on the input side of the field memory,
Performing the second correlation calculation on the output side has the effect of increasing the degree of freedom in reduction or expansion. In other words, the size of the display screen is determined by the calculation content of the first correlation calculation and the calculation content 6 of the correlation calculation #I2; the size of the display screen is controlled by controlling the calculation contents of both. . The calculation means for the first correlation calculation and the second correlation calculation are as follows:
explain. The first correlation calculation and the second correlation calculation are performed on both the luminance signal 9 processing number.
This circuit shows a first luminance signal calculation circuit that performs a first correlation calculation performed on a luminance signal on the input side of a field memory. The first correlation calculation for two luminance signals performed on the input side of the field memory 134 is performed using two in the horizontal and vertical directions ◎Second correlation calculation described later It is better to think of it as a representative value generation circuit with a linear circuit and a gain of 1, rather than as an instantaneous data companding circuit. This will be explained using a figure. In the figure, the part surrounded by a broken line is a #11 brightness signal calculation circuit 1300 that performs a first correlation calculation for two brightness signals 6. This first brightness signal calculation circuit 1300 is , converts the analog/4G luminance signal into sampling pulse φ01142 ~ Φ conversion ~ Converter 1
0004: Therefore, a quantized good signal is input. This sampling pulse is typically 3/so * 4/so
(/so=3.58MHz) etc. are used, but in this embodiment, 440/m (/+=1&75kHz)l: is used to simplify the circuit configuration of the line memory and field memory control system.

The output of the above converter 1000 is the latch four-way 37
0, a weight of /8 is applied via the latch circuit 371, and the adder ΣYi*t: is supplied. First IH memory 26o.

Second 18-meter cage 261. Adder ΣYl is weighted by i1/8 through latch circuit 38o1 and latch circuit 381.
sl2 is supplied @ and the above IH memory 260
The outputs are weighted and supplied to the adder ΣYig via latch circuits 374, 378, and 378, and are also weighted by 12 and 1/8 and supplied to the adder ΣYit42. Further, the output of the latch circuit 374 is supplied to the adder ΣYi*4 with a weight of 178, and is also supplied to the adder ΣYi with a weight of 178. Then, the output of the latch circuit 316 is added to the adder IY! s, xYjm
, and three-state circuit 405 (:, supplied.

Further, three-state circuits 406 #407 each receive the outputs of adders χYi and ΣYis as their inputs. A correlation calculation result of 1 is obtained from the output of the three-state circuit 405, 406, 407, and this result is written into the field memory 1344.

Here, i is performed on the input side of the field memory.
The correlation calculation of ll will be described. The first correlation calculation is performed based on the data sampled by the ψ converter 1000g, but it depends on which data is used to perform the correlation calculation. In the correlation operation, the sampling data to be subjected to the calculation is determined depending on the image processing mode C2, and the correlation calculation formula corresponds to each one.
051406゜4071mMode signal ml+ supplied
m;, ml+m8mm+bow6=Thus, it is determined. The first correlation calculation is performed according to the mode C2 determined in this way, and this correlation calculation essentially consists of 6
Since 2 is a representative value setting rectangle, sampling data having different sampling times are subjected to calculation in the calculation process 62.

In FIG. 5, latch circuits 370, 374, and 380 function simply as latch circuits for latching sampling data, but latch circuits 371, 382, 376, and
8 functions as a delay circuit that delays data in the horizontal scanning direction (by two hours T).
0, the second IH memory 261 has a period of l line 1//w
In Figure 5, the signal delayed by 22 inches with respect to the current line is shown as T, the signal delayed by 1 line is shown as M, and the current line signal B. Signal (= +1. Signal wax = delayed by time T with respect to the current signal = -1 is added to the signal delayed by T with respect to the o11 signal ◎ In this way, it is defined as 12, and 9 Based on the signal, the first correlation operation C2 is performed by mode C2 and the following C2 will be described.The first correlation calculation 6:
The reduction factor is Hdl in the horizontal direction and Vd in the vertical direction.
Suppose that i.

[-mode]

First, the main and sub-surfaces are moving images based on normal analog signals.
The sub-screen (a mode that displays images reduced by digital processing) will be described.

In this mode, Hdl is .
- Song - (1) In the mode ◎ obtained by the correlation calculation, that is, -, no reduction is performed in the vertical direction C:. In addition, in the horizontal direction, by braking the latch circuit group and the IH mechanism 1.2, as shown in Fig. 6 (a).
) As shown in FIG. = % weighting is not applied, and the data obtained by adding 9 data with 2H weighting is obtained as interpolated data.The vertical reduction coefficient Vid=l is shown in Fig. 6. In the horizontal direction (;, data is discarded every time τ(;), but in the vertical direction, data is not discarded.

[m■mode]

Next, let's look at two modes, m and l, where the main screen is a moving image based on a normal analog signal, and the sub screen is a digitally processed zoom-up image in which the size of the image can be reduced.

At this - peak node, the data obtained by the ~Φ converter i2 is extracted and this data is obtained as the output of the adder ΣYu.

Then, this data is stored in the field memory 134 without being discarded.

Therefore, in this mode the reduction factor at the input side of the field memory 134 is Hdl, . Vd1-1
becomes.

In the above two modes, the main screen processes normal analog signals, but in the next mode, the main screen signal is switched to the sub screen and the digitally processed signal is processed.
Image signals are displayed ◎ (m, mode) In mode m, the main image to be digitized is the diagonal area corresponding to the circle of all signals on the display screen shown in Figure 7. and display all iki 1m H. In this case, the hatched part of the display l1iIi[i in FIG.
l: Corresponding data is sampled as a pigeon, extracted by the adder ΣYes, and decompressed and stored in the field memory 134. Then, this first correlation calculation and the second correlation calculation described in conjunction with 4: Therefore, the shaded area in FIG. 7 (the two-phase data is zoomed up and displayed on the entire screen. In this mode m, the data in the t! portion is not rejected, and the reduction coefficient becomes kid l = 1.Vdj-t.As will be described later, the rounding second correlation calculation that zooms up the shaded portion of 1lI7kA by 4 times is performed. (:yo> Data interpolation is performed.

[mr mode]

Isei 2, mode ms is the above-mentioned 9 mode ml (a mode that freezes the zoomed-up main screen in 2 and guides the sub-screen signal again later on, making it possible to insert a sub-screen.) In this mode, Since the corresponding image signal is displayed in a reduced size on the sub-screen (2), a first correlation calculation is performed to reject and reduce the data on the input side of the field memory.This is the target of the first correlation calculation in this m: mode. The data is shown in Figure 6 (
b) 4: As shown ~ Converter 1000 to T,
Three lines of data as M and B are used. A first correlation calculation is performed on these data to obtain a reduction coefficient H
dizl/8 is obtained, and the situation is shown in Figure 6 (b), where two l is added. That is, 'r,,M-,.

``a * M+I * B@l2 Based on 5 types of data corresponding to mouth 1/2 pigeon + 1/8 (T・+""+1 +
Data is reduced by rejecting predetermined data among the data obtained by performing the correlation calculation (M-, )...(2).

[Shrine mode]

Next Kameji, the ship based on the digitally processed signal; oi
There are 4 bow modes that display a still image with the motion of +* stopped on the entire screen. The size of the image displayed with this shade is different from that when displaying a normal analog signal and when displaying a normal analog signal.
They are equal in terms of aspects. Therefore, the reduction coefficient on the input side of the field memory 134 is set to idl-4Vd1=1. Since such a reduction coefficient is similar to the case of the above-mentioned mode, the above equation (1) shown in Fig. 6(a) t:
The first correlation calculation 4 = Therefore, the reduction calculation in the - mode is obtained. This is a mode for inserting a reduced sub-screen. In this case, in order to reduce the sub-screen to be inserted, the reduction coefficient on the input side of the field memory 134 is set to "' WK t Vd1=V.

This reduction calculation is obtained by performing the same correlation calculation as the above-mentioned - mode of (T・+B・+M+, +M, ) on the data shown in FIG. 6(c). The mode of correlation calculation on the input side of the field memory 134 is as described above.

ml, m, , ml, ml) corresponding to these modes, the luminance signal calculation circuit 1300 of nine stripes 1 shown in FIG. .The first luminance signal calculation circuit 13
00 is an isometric 6 for the data 6 of the 0 converter 100G above if the correlation operation is an operation that interpolates data.
Functions as a bypass filter. In addition, if the correlation calculation is a calculation that discards data, the first luminance signal calculation circuit 1300 performs the ~Φ conversion 'a
It functions as a low pass filter for 1000 data. Note that the switching of the correlation calculation of Ml for each mode (two pairs) is performed by controlling the latch circuit group and the first and second IH memories by the three-state circuit ε; Slight = do more.

For the purpose of data interpolation or data rejection, the correlation calculation in #9 #11 is performed on the luminance signal -2 by the first luminance signal calculation circuit 1300 (2) and the field memory 1
34. The field memory and varnished luminance signal data are read out and subjected to correlation calculation processing by a second luminance signal calculation circuit, which will be described later. Second
The brightness signal calculation circuit 1 is the first brightness signal calculation circuit 1.
3oO Same as above, data interpolation or correlation calculation 2 is performed on the read data C2 of the field memory 134, or the data is known. This second correlation operation functions as a bypass filter or a low-pass filter for the data. Therefore, the output of the A/D conversion stooo has the same filter effect as the first correlation operation. It will be subjected to a filtering effect by the second correlation calculation. Like this-21. to/〈0 converter 1000C
The two sampled and quantized luminance signal data are digitally processed by first and second correlation operations to obtain appropriate data depending on the reduction or enlargement mode of the movie image size.

Here, a second luminance signal calculation circuit (two luminance signal calculation circuits) that perform the second correlation calculation will be explained.

In FIG. 8, the broken line portion is the luminance signal calculation circuit tso of #I2.
Indicates o. Similarly to the first brightness signal calculation circuit 1300, the second brightness signal calculation circuit 1500 of Jin is configured in the -direction 4 direction.
: Regarding the current 2-in signal B1, this 12, the 2-line delayed good signal Tel, and the line-delayed signal -lIM, are the objects of the correlation calculation. In addition, when there are 6 horizontal signals and the data sampling period is τ (=current signal, current signal 6;
On the other hand, three signals delayed by time τ and 2τ are subjected to calculation in the horizontal direction. Here, the current signal C2 is +11, the signal delayed by the time τ with respect to the current signal C2 is 0, and the signal 62 delayed by the time 2τ is suffixed with -l.
brightness (the mode of calculation performed by No. 1 calculation circuit 1500 is
Since the number of adders for adding weighted data is ΣY,1 to ΣY,-, the number of adders is large compared to that of the luminance signal calculation circuit.
The main circuit difference from the first luminance signal calculation circuit is that it has many three-state circuits that switch and control data such as 61 to ΣY, e, etc. However, this difference is due to the fact that the second luminance signal calculation circuit has a large number of correlation calculation modes.
2. A latch circuit that latches the operation result,
Regarding the circuit configuration of the part that generates the data to be computed for the correlation computation, which is comprised of the first I memory 802 and the second IH memory 804, there is no difference between the two. Further, the weighting numbers for the data added by the adders ΣY@1 to ΣY, . . . are -2 in FIG. The latch circuit group receives the clock pulse of φ0-, and the I of Jll, 2.
The H memories 802 and 804 are driven by a 440 fm clock pulse. In addition, three-state circuit 840.842
is driven by φG-4 pulses, and is a three-state circuit 84o.

842 is driven by a clock pulse of 2φ0−.

The #I2 luminance signal calculation circuit 1500 performs a second correlation calculation based on the data from the field memory 134 in which the correlation calculation result performed by the first brightness signal calculation circuit 1300 is stored, From this 62, the reduction coefficient Hdo, V on the output side of the field memory 134
do is calculated. Reduction coefficients on the input/output side of the field memory 134, Hdi, Hdo.

Once Vdi and Vdo are calculated, the screen size of the display screen is determined. The reduction coefficient according to the second correlation calculation 1 is performed corresponding to the mode 2 of the first correlation calculation described above. Next 62 Mode m on the input side of the field memory 134 described above, 1 mo @ ml @ ffJ g
The respective modes of ff11 g 1 mH (the two output side modes will be explained), and the second correlation calculation in this case will be explained next.

(Mode gils mode) - mode is a mode in which a sub-screen that is digitally processed sub-screen signals is inserted into the main screen that is displayed using normal analog signals. In this mode, the sub-screen to be inserted is Depending on the size, $716 7-do m that displays the sub-screen at the screen size M-mo that displays the sub-screen on the entire screen,
There are 3 modes to choose from.

m1 mode In this mode, the sub screen is inserted into the main screen 4: 1/16 screen 62 This is the screen code for reducing and inserting the screen. , the reduction factor on the output side is Hdo = 34, V
By setting do=tail, 1/16 screen (two-line small display is displayed. In this case, the reduction coefficient 4= is the data read out from the field memory 134 and two pixel data in the horizontal direction is P). This can be obtained by generating one piece of interpolated data. Similarly, the reduction coefficient Vdo==% is obtained by generating one interpolation data from 6; four picture element data in the vertical direction. This is shown in Figure 9 (a). Note that the data to be subjected to the second correlation calculation to obtain this interpolated data is four-pixel data of Mgos*' and *M+t+B. +548 for these four data
・Perform the operation 10i("+t+M-1)...(3) Obtain the interpolated data of the adder ΣY□(-1, mode) from Kashiji.

' mow So1 In this mode, the sub-screen which digitally processed the sub-screen signal is reduced to the i-screen and inserted into the main screen as in the above mode. Input side reduction coefficient H = strange, Vdi = 1
(: On the other hand, the reduction coefficient on the output side is Hd.

==l, Vd□=% and %(=obtain a reduced secondary function.

As shown in FIG. 9(b), the target data for the second correlation calculation is the three pixel data of pigeon I're l BG.
The second correlation calculation at this time is Ibato+%(T*+Bs)
...It is shown in (4).

'mo1 mode To the above two modes 1. In ``--'', we inserted 2 chapters into main-2, but in this mode C2, the size of the sub-screen to be inserted is set to full-screen display.O In other words, the sub-screen is displayed on the entire screen. The reduction ratio of the sub-screen is l. However, the reduction factor on the input side is Hdi = %, Vdi = 1
Therefore, on the output side, the reduction coefficient is H in the horizontal direction.
It is necessary to perform an operation to set di=2. In other words, on the input side, Hdi = %, and the pixel data density becomes % (2), so on the output side, the horizontal pixel data is interpolated and the resulting horizontal pixel data density is (2) In this mode, a correlation calculation that doubles the data density is performed on the data read out from the field memory 134 in this mode.
Horizontal direction: This means that new data is generated from the data read from the field memory 134. FIG. 9(C) shows this mode (2).
Horizontal area: Represented by a square mark, indicating that new picture data is generated and the horizontal picture element data density is doubled. As can be seen from the same figure, (2) vertical direction (2 is no interpolation of pixel data, so the reduction coefficient Vdo on the output side is Vdo = l. Then, the above-mentioned horizontal picture data density is doubled. The reduction coefficient on the rounding output side is Hd
The operation for o = 21- is obtained by calculating the - prime data pigeon, M+, as the operation object. The calculation in this case is %(M
e+M+t)...It is represented by (5). In this way, this mode set the reduction factor on the output side as Hdo =
2. By setting Vdo x l, the sub-screen can be displayed on the entire display screen using the horizontal direction (= interpolated data).

(Mode for mode m mini) In this mode m, the image data corresponding to the sub-screen signal in Figure 7 (the diagonal shaded part C2 which is added) is reduced and enlarged, and the main screen is inserted into the line. It is a decoding code.

In mode-C2, three modes are set depending on the size of the sub-screen to be inserted: mode-3 for '/16 screen display, mode moms for phone screen display, mode m for full-screen display, and. In the 0 mode −, the reduction factor on the input side is Hd
Since lw 1 and Vd1-1, the above -, m, t
.

The size of the insertion plane is determined by the reduction coefficient 62 on the output side of the three modes of m1o.

Ofn61 mode In this mode, the reduction coefficients Hdo and Vdo are calculated using the second luminance signal calculation for the second image data of the sub-screen.
Hdox %, Vdo -3pi toll mode. In order to extract the sub-screen data, the image data has a reduction coefficient of
-1, and Vd1=1, it should be noted that it is compressed by %1; equivalent ζ2.

This means that the reduction ratio of the screen is % on the input side, but the reduction ratio of the image data is l. Therefore, the reduction coefficient on the output side is Hd.

""K+Vdo-%, so the display is 1 kan, the size of the whole screen (%XHXX).

, the content of the displayed image is 34 (1xlx3(X
No.). In this mode, the objects of the @2 correlation calculation are 7', , B, , as shown in FIG. 9(d)I;
M-1, Mo.

This is data of five picture elements of M+I. Then, the second correlation calculation by the second luminance signal calculation circuit using this data is performed in 3 dots (T, +B, +M+1+M-t)...
(6) ◎mo snow mode performed according to 42 This mode is a mode in which the reduction coefficient on the output side by the second correlation calculation is set to ld□-1 and Vdo to 1. As mentioned above, on the input side, there are 8 reduction coefficients) ldi: 1
, Vdi = 1 Tea4no1! No data compression is performed on image data. However, on the input side, as shown in the shaded area in FIG. 7, only the electric current of the entire double image data of the second sub-plane is extracted. For this reason, in this mode, as a result of the correlation calculation, the good image data extracted in Figure 7 is displayed on the % screen (2) Therefore, the good image data extracted by converter 00 in Figure 5 is the data It is used for image gIA display without interpolation or rejection.

◆ ml mode In this mode, the second correlation calculation is performed, and the reduction calculation coefficient on the output side is set to Hdo=2. Let Vdo=2.

As a result, as shown in FIG. 9(e), the field memory 34 extracts data from the four points marked with circles. The image will be enlarged 4 times and displayed on the full screen. The above data to be interpolated is % for data 'all'+1.
Data obtained by performing the calculation of (Mo+'+t), data obtained by performing the calculation of H(Bo+B+t) on data IB*ta+, data B,,B+,,T・e'
For r+1! 4(B・10B+,-)T・+T+1)・
...The data on which the calculation of (7) was performed, data T,
,B.

Data obtained by performing 3f(TO+Be) calculation on
Similarly, for data 'r+, e 13+1, i(
These are 5 data out of 9 data for performing the calculation T+t+B4-1).

And to this, data M1. t M+, l B@l
A display picture is obtained by adding 4 data of Bat to 9 data.

(Mode for mode ml) For mode m, where the reduction coefficient on the input side of E is Hdi-1, Vd1 = 1, the reduction coefficient on the output side is) Ido
m, where =2*vdo=2. mode is supported.

In this case, the main screen is enlarged 14 times and nine moving images are displayed on the entire screen. Note that the reduction coefficient Hdo"2m"'=2
In order to obtain this, data interpolation is performed as shown in FIG.

(Mode for mode m:) Mode ml is a mode for inserting a sub-screen into the digitally processed main screen image. On the output side, the reduction coefficient is set to Hdo=2° and Vdo=2 to correspond to the φ mode ml for this manual mode. The reduction coefficient on the input side is Hdi- to -Vdi = %, so 1/1 of the entire screen
A sub-screen of size 6 is inserted into the main screen displaying digitally processed signals. The calculation for determining the reduction coefficient on the output side in this mode is the same calculation as in the mode m1o described above.

(Mode for mode m) In this mode, the main screen signal is digitally processed and displayed in a static state on the entire screen. For this mode m:, the calculation mode for calculating the reduction coefficient on the output side is the reduction coefficient Hdo=g2. Corresponding to the mode fnfi where VdQ=xl, in this case, the reduction coefficient on the input side is Hdi-% and Vdi-%, so the main 1lii screen image is displayed in full screen. Note that data interpolation on the output side is performed using the mode mo for the mode m41 described above.
An operation similar to the second correlation operation performed in the crow: 2 yoshi obtains 0 (
For mode ml, the reduction coefficient on the input side is 1 (for mode m, which inserts a sub screen into a static main screen image with di=%, Vd1=%, the reduction coefficient on the output side) ldo = 2 , Vdo
= 1 and corresponds to the mode m4°. In a mode with such a correspondence relationship, a sub-screen image of a moving image is inserted and displayed in a still main-screen image. The second correlation calculation performed in this case is obtained by the same calculation as the calculation performed in the mode mm described above.

As described above, various modes of screen display are possible by combining the modes of the first calculation performed on the input side of the field memory 1340 and the mode of calculation performed on the output side. In addition, the displayed screen itself is a quiet image,
This is possible by controlling the storage state of image data in the field memory 134 for both moving pictures.

In other words, the first luminance signal calculation circuit shown in FIG. The calculation is performed by the second brightness signal calculation circuit shown in FIG. 8 to obtain nine still pictures.The correspondence of the combinations of calculation modes on the input/output side of the field memory 134 described above is shown in the following table.

(ゝ人壬体0) As mentioned above, in this embodiment, image signals are processed in a wide variety of modes. The problem is whether to perform well, and whether multimode correlation calculations can be performed with a small memory capacity.These problems can be solved by means described in detail below.

FIG. 10 shows a system block diagram of an example of an image signal processing circuit according to the present invention that performs image signal processing according to the mode shown in the table above. is performed by the circuit within the broken line in the figure.

In the picture signal processing circuit shown in Figure 1 O, the remote control transmitter 50 selects the video signal to be displayed on the screen 42, as well as its display mode signal, main screen and sub screen channel selection signals, A signal that defines the strength of the voice, etc., which will be described later, is optically transmitted. The seven-point control receiving circuit 51 that receives this transmission signal is composed of a photoelectric conversion circuit that receives the signal from the light receiving element, and outputs a signal corresponding to the transmission signal to the decoder circuit 53. An i microcomputer is used to decode input data 52 and perform various switching controls 41g No. 1 B4.
゜55.56. Channel selection signal 57sJS8*Operating mode control signal 59. The audio control signal section is output to each predetermined circuit. Nine, the RF signal obtained from the antenna 60 is
Tuner At6tζ; is guided and selects the channel determined by the channel selection signal 58 of the decoder circuit 53. The output 62 of this tuner 61 is the IP detection circuit 63:;
The IP detection circuit 63 receives the audio IF signal 64. At the 0th comm which outputs the video signal 65, the audio IP scratch signal 4 is
The audio output 67 is guided to the audio circuit 66 and the audio output 67 is guided to one input end of the audio switching circuit 68.◎Audio switching circuit 68
The output cuff 0 of the audio selection circuit 69 is supplied to the other input terminal of the audio selection circuit 69 . Then, according to the audio switching signal 54 of the decoder circuit 53, the audio output 11. The output cuff 1 of the audio switching circuit 68 from which '12 is obtained is led to the main surface sub-cuff 3, and the other output cuff 2 is led to the earphone 74. 〇Video signal 65 obtained by the IP detection circuit 63 is input to the video signal switching circuit (9) 75, to which the video signal from the video signal switching circuit 87 is also supplied. The video signal No. 46 switching circuit 75 selectively outputs a video signal 77 for the main screen and a video signal 78 for the sub screen.

9. From the l'LP signal obtained by tuner B 79, the resonating channel is selected according to the channel selection signal 57. The selected signal 80 is sent to the rr detection circuit 8
1, and its detection output 82 is supplied to an audio circuit 83 as an audio IP signal.

The audio signal 84 is then guided to the audio switching circuit 74.

In the figure, the other input of the audio selection circuit 69 is an external audio input 85.
It is.

In this case, the video signal selection circuit 87C;
The video signal is selected according to the selection signal 56I, and the video signal, signal 76, is obtained like this (:, in the system shown in the figure, the tuner.

61 or tuner B, 79; it is also possible to handle input signals 85.88 from external inputs, such as VTRs, video discs, etc.

Next, talking about the processing of the video signal, the video signal 77 of the main screen is led to the main screen brightness signal geographical circuit 89 and the main screen color signal processing circuit 90, and the main screen brightness signal signal is sent to each output terminal. A color difference output B-Y961R-Y93 is obtained.

The main screen control circuit 94 sends a control signal 9L96 for controlling the display picture mode to the main screen brightness signal escape circuit 89. The signal is supplied to the main screen color signal processing circuit 9G to perform control operations. Also,
Regarding the synchronization system C, the main screen synchronization signal extraction circuit 97 extracts the horizontal synchronization signal HM8YNC98 from the input video signal 77.
e Ii Separate the direct synchronization signal VM 8YNC99.

The sub-screen luminance signal 78 is then supplied to a sub-screen luminance signal processing circuit 100 , a sub-screen color signal processing circuit 101 , and a synchronization signal extraction circuit 102 .

The sub-screen video signal 78 is processed by sub-screen luminance signal processing path 10.
0 & sub-screen color signal processing circuit 101 are supplied to the m synchronization signal extraction circuit 102, and the narrow surface control circuit 103 is connected to the luminance signal processing circuit 100 and the color signal processing circuit 101.
t-generates controlling signals 104,105. Luminance signal 106 which is the output of the sub-screen luminance signal processing circuit 100
is converted into a digital signal by the luminance signal to Φ converter 10GG. On the other hand, the R-Y signal 1079 and the B-Y signal 108, which are the outputs of the sub-screen color signal processing circuit 101, are multiplexed at a predetermined timing by a multiplexer 110G, and the signal 109 is guided to the color signal to Φ converter. ~Φ converter 100G, 1
200 is the input signal sampling frequency φm=880
/us (/as: sub-screen input horizontal frequency) is quantized to 6 bits. Above ~ Output 1 of Φ converter 1000
11 is the first one by the brightness signal calculation circuit 1300 of Ml
Correlation calculations are performed as soon as possible. The result of this first correlation calculation is stored in the luminance signal field memory 1400. The data in the field memory 1400 is controlled by the signal 113 of the address generation control circuit 3100, and the read data is subjected to correlation calculation #I2 by a second luminance signal calculation circuit on the output side of the field memory 1400. This calculation result 115 is stored in the buffer memory 16
Guided by 00.

In this way, on the input/output side of field memory 1400, two
By performing nine correlation calculations in stages, it is possible to set the display state of the multi-mode video as shown in the table above. The buffer memory 1600 is read out at a predetermined main screen cycle. The buffer memory output 116 is connected to D/
Further, the luminance signal 117 converted into an analog signal is amplified by a buffer amplifier 1800 and output to a luminance signal switching circuit 1900.

On the other hand, the multiplexer 11001: Therefore, the R-Y and B-Y digital signals of the multiplexed nine color signals are converted into digital signals in the ~Φ converter 1200, 0 is converted to digital, 0 is converted to digital, and good signal 1 is converted to digital.
10, a first color signal calculation circuit 2400 performs a correlation calculation of the first color, and the data is stored in a field memory 2500. A second correlation calculation is performed using the data ζ read from the field memory 2500, and the calculation result is sent to the R-Y/A controller 2000 via the rough ameri 2700. B-
The B-Y signal 119 is guided to the V converter 210 for Y and the output 120.12 of each D/A converter.
1 is led to the output circuit 3100 via the sofa amplifiers 2100 and 2200 and the color signal switching circuit 2300.

Note that the sub-screen horizontal synchronization extraction signal 88YN0122 and the vertical synchronization extraction signal V8YNC123 are the sub-screen tiling generation circuit 280 that generates various tying signals for the sub-screen.
I am guided by 0. The various timing signal outputs 124 of this sub-screen timing generation circuit 2800 are supplied to the digitally processed portion of the luminance signal.

Further, a control signal for controlling the sub-screen display is generated by the mode signal generation circuit 2900 based on the output 59 of the decoder circuit 53.
Various mode signals 125 are generated at 42.

On the other hand, the main screen horizontal synchronization signal 1M8YN098 and the vertical synchronization signal VM8YNC99 are supplied to the main screen timing generation circuit 300 which generates each main screen timing signal.
It leads to 0. This main screen tie-up occurrence enclosure 3000
The various timing signal outputs 126 generated in the above are respectively supplied to the digital processing circuit portion of the luminance signal 1 output signal. The field memory address generation circuit 3100 has outputs 1131 and slave fields 140G, 250.
0 is controlled by the sub-screen timing signal 127 and the main-screen timing signal 128H.

Output signal DG12 of main screen timing generation circuit 3000
Reference numeral 9 denotes a switching signal for switching between the main screen signal and the sub-screen signal, each of which is led to a luminance signal switching path 1900*color signal switching circuit 2300. The above switching signal:: Therefore, the switched luminance signal output 1302 color signal output is -
Y signal output 131 t BY signal output 132 is supplied to cathode ray tube 134 via output circuit 3200 . In addition, the horizontal synchronous reproduction signal f 135° obtained from the main screen timing generation circuit 3000 and the vertical synchronous reproduction signal /VD
Both reproduction synchronization signals of M are guided to a synchronization output circuit 3300,
This synchronization output circuit 3300 outputs a horizontal deflection signal 137*fi
Direct deflection signal 138 is output to the deflection system circuit 0 As described above, in the embodiment of the image signal processing circuit according to the present invention shown in FIG. 10, image data is processed. The image signal processing circuit according to the present invention processes image data according to modes corresponding to multi-mode image display formats. Processing of image data according to a wide variety of modes is possible by performing the first correlation calculation and the second correlation calculation on the input and output sides of the field memories 1400 and 2500, respectively. In this way, multiple correlation calculations are performed on image data, and image display in multiple modes is performed, as shown in Table 4 (9) above. This means that multi-mode screen display can be performed without increasing the memory capacity of the field memory 1400 or 2500, depending on the type. In this case, in this embodiment, when processing the data of the luminance signal No. 7, a circuit means is provided that provides similarity in the control means for controlling the addresses for both signals so that the circuit configuration of the address generation circuit is not complicated. . Note that the above-mentioned correlation calculation is also performed on the image data of the horizontal direction and the cuboid direction, but in the horizontal direction, it is necessary to write and read data in one water period. This is necessary for rounding to extract data to be subjected to correlation calculation when performing horizontal correlation calculation, but in this embodiment, one horizontal period I:2
The data for the line is set out. The address generation control for accessing the image data in the horizontal direction also has a circuit configuration that can follow multiple modes of image display. These features will become clearer by explaining the blocks corresponding to the blocks shown in FIG. 10, which shows an embodiment of the image signal processing circuit according to the present invention, particularly the circuit blocks within the broken line area.

FIG. 11 is a block diagram showing in detail the inside of the circuit blocks of the nine sub-screen timing signal generation circuit 2800 shown in FIG.
is the sub-screen horizontal synchronization signal H,8YNC123,1iA obtained by the sub-screen synchronization signal extraction circuit 102 in FIG.
Displaying the sub-screen in response to the direct synchronization signal 4t Vs 8YNC and the signal Vs, i which determines whether the video signal supplied as the sub-screen has a signal that can be synchronized with the output of a predetermined counter. Generates the various timing signals needed. Then, the sub-screen display (=required timing signals are a timing signal for controlling a control circuit for generating address signals for field memories 1400, 2500, etc., and a line for storing horizontal image data. They are broadly divided into memory address and write control signals, clock signals for horizontal data processing when processing sub-screen image data, and clock signals for processing vertical data.

First, if we look at the reference clock when processing horizontal image data, the horizontal synchronization signal Hm 8Y
The synchronizing signal H, 8YNC, which is input with NC and a comparison signal is supplied to the other end and whose phase is compared, is sent to the oscillator 28021:
It functions as a synchronization signal for the The oscillator 2802 generates a clock pulse φm=8 that defines horizontal timing.
807as is generated. This signal φS is applied to the frequency divider 2803
The frequency is divided by 2. Here, the output of the frequency divider 2803 is inverted and becomes the signal 5-. This signal φ0- is input to the counter CT.
It is supplied as a clock pulse to RI 2804, and the output of counter CT&(1) 2804 is applied to horizontal tiling signal generation circuit 28o5. The horizontal timing signal generation circuit 2805 generates signals H and ■r that determine the horizontal phase of the sub-screen as one of its outputs, and this signal is applied to the phase comparator 28o1 as a phase comparison reference signal for the position comparison. . Above counter CTJI) 28
04 is composed of a nine-stage branch circuit, and receives the above signals φ,
The frequency is divided by 440 in synchronization with the rising edge of 0. Therefore, the final output stage of the counter CTR (1) has a horizontal frequency, and the 8Rth output has a frequency of 2/srs.

The signal with the horizontal frequency /as is sent to a counter CTR that functions as a vertical counter for determining the vertical phase of the sub-screen.
(7) 2806, and the horizontal frequency 27W- signal is added to the counter era (612807) of a circuit that synchronizes the vertical phase by a so-called countdown operation. In addition to the signal Half that determines the horizontal phase of the counter CTR (1), the counter CTR (2) that controls the line memory address generation circuit 280B that generates the line memory address in the display mode for zooming up the 2804s sub-screen is reset. and a timing signal H1 (81% mHy*) for controlling the line memory and loading the sub-screen data into the field memories 1400 to 2500 in accordance with the sub-screen mode.

Note that the line memory address generation circuit 2808 is
Counter CTR (1) 2 depending on the supplied mode signal
804 or an address signal ADo for the line memory by counting the pulses of the counter (2) 2809.

06 which generates AD, , , ADo, and signals H1, which are generated by the horizontal timing signal generation circuit 2805.
The line memory control signal generation circuit 2810 is composed of flip-flops that operate in response to vertical reference signals.
The signals W and a, which control data writing and reading, are squared.

Next, in FIG. 11, if there are two vertical ties, the vertical synchronization signal V, 8YNC of the sub screen is supplied to the synchronization signal width detection circuit 28114. 9 vertical synchronization signal V, 8Y
During the pulse width of NC, the counter CTR (1) 28
The pulses from 04 are counted, and based on this force, it is determined whether the signal can be regarded as a synchronizing signal or not.
1:, Supply. This phase comparison circuit 2812 inputs the comparison pulse generated by the phase comparison pulse generation circuit 2813 based on the output of the counter CT & (6), performs a phase comparison with the reference phase, and compares the phase of this with the reference phase.
J6) Generate a reset pulse for 2807. This reset pulse (from second, horizontal synchronization signal 27M1
The frequency is divided by 25 and nine pulses are obtained as the output of the phase comparator circuit 2812. In this case, the phase comparison circuit 2812
The signal V applied to the phase comparison pulse generation circuit 2813 is the synchronization signal V, 8YNC applied to the synchronization signal width detection circuit 2811, which is frequency-divided by 525 and generated by the phase comparison pulse generation circuit 2813. This is a signal that indicates whether or not there is a capacitance error range (2) when the pulse and phase are compared.
Reset 7. In other words, V is the signal that defines the mode of whether the synchronization signal is an unstable synchronization signal seen in video games or the like. In this way, the vertical reference signal obtained is transmitted to the vertical counter CTR(7) 28.
06 as a reset signal, and is also supplied to the line control signal generation circuit 281O. The vertical counter CTR(7) 2806 is supplied to a vertical timing signal generation circuit 2814. This vertical timing signal generation circuit 2814Fi and field memory 1400.2500 reset signal V! of the 4 address generation counter including tk! and the signal vt used for presetting
generate o. That is, above &! The vertical tiling signal generation circuit 2814 generates a pulse for taking in the vertical direction image data of sub i & iTh.

1jiji tie scolding signal generation circuit 2 shown in FIG.
800 is an address signal ADgll*Al)os@AD for the above line memory, a signal related to the line measurement, and a pulse v? for taking in data in the vertical direction of the sub-screen. sV? The signal H! functions as a horizontal data acquisition pulse for the O field memory.・In addition to the φM address, the pulse signal that drives the control circuit for controlling the field memory address and the Id of the sub-screen in serial form! Generates an 8/P conversion signal for converting IgI data into parallel format data.

That is, based on the horizontal synchronization signal H, 8YNC of the sub-screen, a pulse of φ=4407as is obtained in the frequency divided 1ft 2803, and based on this signal φ−〇, 1;Field memo January 4
The control signal that controls the field memory of 00.2500 is sent to counter "R (3) 28ts, counter (4) 2
816. Field memory control signal generation circuit 281
7. 4 reduction ting generation circuit 2818. The timer signal t7 when transmitting and receiving data by time-divisioning the field memory 1400.25004 data in units of 7 bits is generated by the counter CTR(3) 2815 in the -1 screen normal mode. These signals include a signal that determines whether the column address or row address is (upper bit or lower bit), a signal that controls the address of the field memory 1400s 2500 according to the slippage, and a lien enable signal WB'. On the other hand, the counter CTR (4) 2816 generates a timing control signal for time-sharing image data for a mode in which the sub-screen data acquisition mode is half of the normal mode in the horizontal direction. belongs to. Here, in the data compression mode of 2%, the control signal for transmitting and receiving data by time-sharing the 1 meter data on the sub-screen is generated as a field memory control signal via the h data reduction timing generation circuit 2817 t-. Provided to circuit 2818. The field memory axis control signal generation circuit 2818 generates a control signal for compressing the normal mode and image data by 34+= and transmitting the data to the field memories 1400 and 2500 in a time-division manner into upper bits and lower bits. do.

Furthermore, in order to store the image data in the field memories 1400 and 2500, it is necessary to convert it into serial data. The control signal for this data format conversion is
In an image display mode in which the main screen is an analog signal display and a sub-screen is inserted therein, the output of the upper symbol data type/minimum timing generation circuit 2817 is obtained by the 28/P conversion timing signal generation circuit 2819. Here, in the mode table mentioned above, in the mode m, ', rrJ, m-, which inserts a sub screen with a static image displayed on the main screen,
Please note that the image data is compressed to 1/8 in the horizontal direction.

When converting image data from serial format to parallel format after compressing image data to 1/8 in the horizontal direction;
A 1/
A data conversion control signal is obtained through an 8-data fine timing signal generation (b) path 2821. This control signal is the above 8β
As a result, the Sρ voice change timing signal generation circuit 819 is supplied to the conversion timing signal generation circuit 2819.
At its output, in any of the modes listed in the table above, a timing control signal for converting the image data from serial form to parallel form I1 is obtained. The image signal includes both the luminance signal 1 output signal, and the output of the φ conversion timing signal generation circuit includes the conversion timing signal 4IIC and 8 /P signals are obtained.

As described above, in the sub-screen tie-setting signal generation circuit 2800 shown in FIG. 11, the rounded address signal AD (11@AD , , , ADo, and at the same time the field memory 1400.250 is generated.
Various control signals are generated for generating the address of 0, and these signal generating means (two and one) will be described in detail.

Figure 1 = Sub-screen timing signal generation circuit 28 shown
00 generates an address signal for the line memory, controls the control system for the field mesori 1400.25004, and synchronizes with the reference clock signal based on the sub-screen horizontal synchronization signal H, 8YNC, @ direct synchronization signal V, 8YNC. Perform system control. In this case, - Counter CTR (6) which is a circuit related to serial synchronization pull-in 2807° Synchronization signal width detection circuit 2811 * Phase comparison circuit 28121 Phase comparison The details of the phase comparison circuit 2813 are shown in Figure 12. , the synchronization signal width detection circuit 2811 counts the count pulse of the counter CTR (1) 2804 shown in FIG. Otherwise, a pulse vp is generated at its output. Also, phase comparison circuit 2812° phase comparison pulse generation circuit 28
13 is a so-to-signal V according to the stability of the series synchronization signal;
It operates according to the following.

In this case, the phase comparison pulse generation circuit 2813 supplies a phase comparison pulse to the phase comparison circuit 2812, which resets the counter CTJ6) 2807 that counts down the signal 2/1111 and at the same time generates a vertical synchronization signal. The output of the signal VllF to be used is also generated.Next, the above side 1IiiiI [+Tie-up signal generation circuit 28
The line memory address generation circuit 2808 of 00 generates an address for the line memory "@l m ADI! e
Mu D6. occurs, but the luminance signal calculation circuit 1 in FIG.
Figure 13 shows the line memory configuration included in 30G. In FIG. 13, a line memory Ll t Lm @ Lm l which varnishes the luminance signal data of the sub-screen in the horizontal direction ζ
L& essentially functions as a slow-burning element with a period of one hour each. Then, the address signal AD・ generated by the line memory address generation circuit 2808 shown in FIG.
s * AD6 exposure gA D, later address signal AD
, 1 addresses line memory L1, address signal ADo addresses line memory L, and address signal AD, , addresses line memory L4. Each line memory L, to L4 is a RAM (Random Access Memory) having a capacity of 440 words and 6 bits of FX.
y) It has a structure. The above line memory L1. L,
The common output terminal signal of 0 and the line memory L, .
L-th common input signal: is the above-mentioned memory L, , L,
A signal delayed by two horizontal periods with respect to the common input signal is obtained. These line memories L, . Data necessary for performing a correlation calculation of ill of the 2-line delayed good signal T, the 1-line delayed good signal M, and the visual line signal B can be obtained. In addition, each 2-in memory L, -L4 in the t3 #A
The writing control signal W-reading control signal 8 generated by the line metering control signal generating circuit 2810 in FIG. 11 is applied to control the data exchange. In this way, the address signals AD (Ht AD6* *Mu Da) for the line memories L, -L are obtained by the line memory address generation circuit 2808, and these address signals are To explain this using Fig. 14,
The figure shows line memory address generation circuit 2808 in Figure 5.
*Details of the line memory control signal generation circuit 281O are shown.

The line memory control signal generation circuit 2810 is composed of flip-flops FF and line memories L, to L4.
It generates signals W and R that control the transfer of data to and from the terminal. On the other hand, line memory address generation circuit 2808
is the 440 fvtm t-clock pulse shown in FIG. 11, and the counter CTJI) 2804 uses the output of the horizontal timing signal generation circuit 2805 as the reset pulse.
The above-mentioned line memory address generation circuit 2808 has a function of switching the output of the counter CTR (2) 2809 according to the mode in the mode table indicating the image display mode.
is the counter CTR (which is supplied as a signal defined as an address signal according to the input mode signal)
1) 2804. The count value of counter CTR(2) 2809 is calculated by three test circuits TBl to T8. Selectively output. As a result, the address signal ADo1. of the line memory corresponding to the image display mode &: is generated. ADo Goose, A
Do, get. Address signal ADO according to this mode
I? The need to generate hD, 1* ADos depends on the line memory L1 to
This is due to the difference in the amount of image data written to L&.

That is, in the case of the normal 1-screen display mode, image data corresponding to the entire screen is loaded into line memories L1 to L, 2, but in the zoom-up mode, as shown in FIG. Only the image data corresponding to the above line memory rims 1 to L (the image data at the center of the nine screens indicated by the diagonal)
Don't take turns. In this way, the amount of image data written to the line memory differs between the normal image display mode and the zoom-up mode, and between the two modes, data is written to the line memories L, to L4, which function as two lines M for one horizontal period. The problem due to the difference in the writing time of this data is that the above line memory address generation circuit 2808 (:The above address AD6. @ A
DH* ADllm in both modes, three-state circuit T8. ~T8. This can be resolved by controlling the

The values of the above addresses ADol, ADo, Mu D Hatake are stored in the counter CTR (1) 2804 shown in FIG.
* Counter CTiL(2) 2809 count value is transferred to the three-state path T8. - It differs depending on the control by T84.

Writing and reading of the line memories L@ to L are controlled so that when LllLl is in the data write mode, the line memory (SlJ*t11a is in the data read mode. During this process, line memory L reads the data l water period ago, and after one horizontal period, the data of line memory L is written to line memory L. After this l horizontal period, line memory L4 By reading out the data, the operation target data T, M, and B, which are the operation targets of the second correlation operation, are obtained.In this case, the address AD01 # ADH is the counter CTR (1) 2.
804, counter CTR(2) 2809 has different preset values, so the line memories L, ,
In Ll, the writing time and the reading time of image data are different depending on the writing mode and the reading mode. However, a common address signal AD is used for the line memories L, L, which send and receive the current data (image data delayed by two horizontal periods). The counter that defines the above is the counter CTR (1) 2804, and the counter CTR (132804 is a color that defines the address for the normal screen display mode. This address counter (!) functions as the address 9 counter. Ta(1) 280
The three-state circuit T8.4 specifies the reading address of the line memory L, . ~T8. works. In this way, the read addresses of the line memories L to L4 are determined by the counter CTJI 2804, which performs address counting operations in accordance with the normal image display mode, regardless of the write mode. The line memory control signal generation circuit 2
Since the flip-flop FF constituting 81O uses the pulse HR8 every horizontal period as a clock signal, the line memory Ls-La continues to write data and start the offset every horizontal period. As a result, the image display mode ζ
Regardless, the line memories L, ~L4 operate as a delay line for one water period, but in this case, the data read timing is determined by the counter CTJI) 2804
depends on the counter value.

For this reason, as shown in Figure #17 above, even if the Aya* display mode is used to write the 1iIi* data for the issue screen in the zoom up mode, the data for the plan page is read out when starting the data. Read at the right time. Therefore,
When writing to line memories L, ~L4 in zoom up mode, i41 of T, M, and B obtained by extracting the data.
The data density of the correlation calculation and the target data is % at the time of data writing.

In this way, the line memory compensates for differences in data writing due to differences in image display modes when data is read out (secondly, it functions as a data processing speed converter that reads data at a constant speed).

This is because the preset values of the counter CTR (1) 2804 and the counter CTR (2) 2809 are different. It is a time chart showing. The horizontal timing system divides the output of the oscillator 2802, which oscillates at 8807V, into two to generate various timing signals based on k440/M=φ−〇. Horizontal tying signal generation circuit 2805
The signal HR8 generated at the counter c'ra(i) 2804 is used as a reset pulse for the counter address (2) 2809 at every horizontal period. 2810.% data reduction timing generation circuit 2817 t Field memory control signal generation circuit 2818 * K data small timing signal generation - path 2821 Control for E i41
Used as a signal. Also, the signal HiLhi? , 2
f■-1f■ is an operating voltage for determining the vertical reference phase. The signal ays t ) (?! is a pulse that determines the horizontal image data shift timing. This is a signal that determines the timing of writing image data in mode.

When writing image data to the above-mentioned line memories L1 to L, L, the 7 lip-flop r of the line memory control signal generation circuit 2810 controls writing to the write memory.
This is the output signal of r1. And line memory Ll-,
, L, counter c'ra(i) 2804 e Counter CT 几(
2) The count value of 2809 is shown in the figure. As can be seen in the figure, the initial count value of counter CTR (2) 2809 is 1 with respect to the initial value of counter CT (1) 2804.
It is 15 base. Also counter CTR (2) 280
The clock frequency of G is the same as that of counter CTJI) 2804. Note that the above signal H! 1 is the normal Isso processing mode, and H1 is the image signal processing ζ in the zoom-up mode. Here, the horizontal sub-screen image data capture pulse H! depends on the modes classified in the mode table mentioned above, p, 1 (t=HT.

(m, +n(+m, +ml) + HT, (m:+
m, ) = - (8) 〇Similarly, regarding the import of image data in the vertical direction, the timing of writing vertical data is determined between the normal image display mode and the zoom-up display mode. This timing relationship is shown in FIG. 16. In the figure, the signal V indicates the vertical image data capture timing in the normal mode, and the signal v! shows that in zoom-up display mode. That is, at this time, the vertical image data capture timing pulses VT, , VT and the clock signal /[11
s 0 indicating the relationship with the counter address of counter (7) 2806 In this case, vertical data capture pulse V
T is v, == v'r corresponding to mode table (J) mode
, (m, +m: + rn: +m field) + VT intention (mt
+m*)......Even when the image display mode is reduced mode, the timing of data acquisition in the vertical direction is regulated by the circular hole shown in the creation. Ru. However, regarding the acquisition of image data in the horizontal direction, in the reduction mode, the image data in the horizontal direction is acquired discretely according to the reduction ratio. In the reduction mode, which is expressed in ml in the mode table mentioned above, it is necessary to reduce the image data in the horizontal direction. There is a need to.

Furthermore, when image data is extracted in the horizontal direction at a ratio of 300 nm compared to the normal mode, the timing pulse for taking in the data in the horizontal direction needs to be 54/■.

Reduction mode of these display images . is expressed by the following formula using the reduction mode shown in the mode table: 0 Vy6=eVyl (347ws・ms+/sss
・m:) --Q
-Timing pulse 34/simple in reduction mode of 54,
The timing pulse in the reduction mode of /us and U
The relationship between counter CTR (7) and the count value of the counter 2806 is shown.

In this way, ~Φ is extracted depending on the display image mode.
The converted data is input into the field memories 1400 and 2500 at the timing described above.

The color signal of the image data of the sub-screen is processed by time-division multiplexing of two signals, the &-Y and B-Y signals, on the input side of the color signal calculation circuit 2400, which is a pre-processing of the color signal filter 2500. In this case, the multiplexer 1100 multiplexes the color signal in a time-division manner,
I'L-Y, B-Y, R-Y, B-Y, . Fig. 18 shows the timing of conversion into the luminance signal in relation to the luminance signal.In Fig. 18,
φ0- is the horizontal tie signal generation circuit 2 of the sub-screen tie signal generation circuit 2800 that samples the luminance signal.
This is a signal generated at 805.

A signal φ0. which samples this luminance signal. Against Te,
The timing for multiplexing the color signals as described above is performed according to the timing shown in the JIIB diagram.

(Field memory 140012500) Next, field memory 1400. which stores the first correlation calculation result.
Let's talk about 2500.

FIG. 19 shows a field memory 140G that stores correlation calculation results for luminance signals and a field memory 2500 that stores correlation calculation results for color signals.

In the luminance signal field memory 1400, the luminance signal follows the control signal generated by the ψ conversion timing signal generation circuit 2819, and the image data is converted into parallel form by the 8/P conversion circuit 141O and stored in the luminance signal field memory 1j 142G. be done. Also, at this time, the memory address is determined by the field memory address generation circuit 14 controlled by the field memory control circuit 1430.
Occurs on 4G. and luminance field memory 1420
When starting the data, P/B conversion of the data is performed by the φ conversion circuit 1460 in response to the tie signal from the φ tie generation circuit 145G during rounding for performing the second correlation calculation. Further, the field memory 250G that stores the correlation-calculated color signal shown in FIG.
10, the φ-converted data is stored in the color signal field memory 2520. The read data is then converted into serial data by the φ conversion circuit 2530.

For field memories 1400 and 1500, in addition to the timing signal for converting its own data from parallel form to serial form as described above, there are control signals for controlling the upper address and lower address, and this address control signal. A control signal, a write enable signal W, is required to control the field memory itself in accordance with this.

FIG. 20 shows the 11th section which controls the field memory.
Field memory control signal generation circuit 2818 shown in the figure
and details of the data reduction timing generation circuit 2817. In FIG. 20, a counter CTR (4) 2816 is a counter that generates a timing pulse for replacing the image data for the luminance signal from the serial format to the parallel format in the normal display mode, and the horizontal timing generation circuit 2805 A reset is applied by the output signal H1ll of , and is synchronized with the signal Ha1g. Pulse groups 8P, , 8P, which convert data from serial form to parallel form by this counter CTB(4) 2816
, 8P, , 8F, .

Obtain 8F4. Note that this h reduction timing generation circuit 2
817 counter CT R (4) 2816 has luminance 1
The above-mentioned ψ conversion timing pulse is generated to reduce the horizontal direction data to H in the normal picture height display mode. The above field memory control signal generation circuit 2818
receives the signal 8807M1-440km (D signal) and generates a signal to control the field memory based on the output of the counter CT R' (3) 2815.The field memory uses DRAM in this embodiment, and this control Column address strobe signal to control the address CAG, o-7 Address strobe signal RA8. Power to control the address signal CAG Row address signal RAG and write address signal RAG and write address signal A signal is obtained from the field memory control signal generation circuit 2818.

The counter CT R (3) 2815 described above in FIG.
.

This figure shows the timing relationship between the pulses of 2816 and the data sampling control signal system for the luminance signal field memory 1420. In this figure, the data sampling intervals shown at 8F and -8F are shown. is 14mo, and after sampling x data, sampling of period data of lφ10 is stopped before sampling the next data★. P/ data
8 conversion and a time interval of 1 cycle of the signal φ-o1 for data sampling + 1 sampling can be said to be a buffering effect for the processing speed of the field memory. This is a tie pulse that reduces the image data of .

We have looked at the ψ conversion of the data for Tweed Memo January in the normal image display mode, but next we will discuss the ψ conversion of the data when the image display is in the reduced mode.

In the normal image display mode, data is reduced to % in the horizontal direction of rounded image data, which effectively uses the storage capacity of the field memory. In the present invention, the display screen can be reduced in multiple modes in the nine cases shown in the table above. To reduce the thickness of the display screen, reduce the image data to the size before storing the data in the above-mentioned field memory (see the table above (2) and mode m: , m,)
. A timing signal for ψ conversion of data in this case is obtained by the circuit shown in FIG. FIG. 22 shows a reduced mode of the display screen of the data reduction timing generation circuit 2821, 8/P timing signal generation circuit 2819.

Circuit part related to the code, counter CT IL (5) 2
820 is shown. In FIG. 22, counter CTR (5) 28
Reference numeral 20 denotes a clock/counter, which uses m01 as a clock pulse and extracts five pieces of data during this time, so the data is reduced to . Then, a signal HAl having the horizontal frequency of the sub-screen
is the reset signal, and this counter CT R (
5) 2820 output is reduced to tie voltage generation circuit 282
gated at 1 and the display mode is m: in the table above.

m5 (D%-0 which generates the ψ conversion timing control signal of the 1iii data of
,'.

8P; , 8P: W8T' is generated in the data reduction timing signal generation circuit 2821. A time chart of these timing signals is shown in FIG.

In addition, in FIG. 23, 8 of the above timing signals
P: and 8P; are omitted.

Timing signals 8P;, 8P,'-,, 11P generated by the above-mentioned data reduction timing signal generation circuit 2821:
, W8T" is the 8β timing signal generation circuit 2819
The three-state circuit T8. and the mode signal m:+
Controlled by mj. Here, the three-state circuit T
8. , the timing signals 8P, , 8P, , 8F, , 8Ps, when the mode of the above-mentioned display image is normally i-)°.
8F,, W8'r is led, and the above three-state circuit 8T,,lii? , the image body motion white applied to =
Accordingly, an A-reduced and A-reduced 8/P' conversion timing signal is obtained at the output of the ψ conversion timing signal generation circuit 2819. In this way, 87 of the 11ii high data for the luminance signal
Obtain a P-converted signal.

On the other hand, the 87P conversion timing signal for the color signal data is the aforementioned conversion signal 8F, 8P, in FIG.

BP, BP, 8P: and the output Q of flip-flop FFo.

Q is made by υ. The above flip-flop vv.

inputs the inverted signal of the writing enable signal WET of the picture quality data of the luminance signal to the field memory 1420, and the output of this FFo, which is reset by the signal H■, is output from the three-state circuit T8. ．． This is a control signal for T84. The color signal is sent to the multiplexer 110 mentioned above.
Since the R-Y and B-Y signals are alternately serialized by 0, the timing of conversion of ψ is 8/? with the timing of adjacent data as in the case of the luminance signal.
It cannot be converted. That is, the color signals are serially R-Y and B-Y.

From the data group RY, . . . , it is necessary to extract every other signal only the RY signal or only the BY signal. Whether one of the Y signal and the BY signal is extracted and the data is reduced in accordance with the mode depends on the mode signal in Figure 22.

When this mode signal is 11 in the mode classification of the display image, the color signal data is reduced by hζ2. However, to reduce the data to H, as can be seen from the timing chart of the luminance signal data shown in FIG.
It is advisable to sample each data corresponding to l by l. Even when the color signal data shown in FIG. 24 is reduced to
If one each of the B and Y signals is extracted, the signal is reduced to a color signal data signal.

In the same figure, the color signal data corresponding to 8P and C' is an example ζ
2, time A of lO clock period of clock φ0-
Since the R-Y signal data is sampled in
PIC', 8P, C'... The nine color signal data corresponding to 8P and C' are reduced to the respective numbers. In this case, the timing signal 8 P, C~8P, C'ζ; corresponds, and the data are [(RY) e (B-Y), (R-Y),
8/P conversion is performed to parallel data in the order of (B-Y) @ (RY) (B-
Y) # (RY), CB-Y) # (B-Y
)]. ψ transformed (R-Y) and (B-Y)
The signal data sets are alternately replaced. In Fig. 24, R-Y (No. 1) is sampled at time, and B-Y is sampled at time B, 1φ01 clock later, so R-Y , 0 that can suppress the phase error between B and Y
The time difference between the sampling times of the 8-Y signal and the BY@ signal is at most 2φ01 clock periods between times E and P. In this way, the φ conversion timing signal generation circuit shown in FIG. 22 reduces the data and extracts the data at discrete times. This suppresses the occurrence of B-Y and R-Y signal phase errors.
: Or, if the mode signal applied to #I22 is m
This figure shows a timing chart when the color signal data is reduced by 2 in the case of s'+tn@.

(First Correlation Calculation) The correlation calculation regarding the horizontal and vertical data in the input information of the feed memory 140G for the luminance signal has already been explained using FIGS. 5 and 8. In FIG. 26, the first correlation calculation for both signals of the first luminance signal will be comprehensively explained.

In FIG. 26, latch circuits L111 to L12 of the luminance signal calculation circuit 1300 and the color signal calculation circuit 2400 each have a latch function of latching data. However, the latch circuits Lat20 to Let31 function as geometrical delay elements having a delay time τ corresponding to 10 clocks of the clock signal φso applied as the clock φ.

First, to describe the first correlation calculation for the luminance signal, each of the latch circuits Lat1 to Lat3 has (n-1
) line diagram ii data Tten line diagram data M
y, (n+1) line diagram data BY are respectively derived◎
Here, if the output of the latch circuit Lat21 is taken as a reference time, the input data of the latch circuit Lat21 advances by a time T, and the output data of the two-way circuit Lat22 lags by a time 2τ. Here, −l, for a delay of time τ,
If we define a subscript of +1 for the advance of τ from 09 hours to the current time, the calculation target of the first correlation calculation is Bmv*M+y*M
*Ma9M-Goose! -T.! It is expressed by five pieces of data.

The relationship between these five pieces of data is made to correspond to the image data on the display screen, and the sample positional relationship of the data is shown in FIG. In the 26th-middle luminance signal calculation circuit 1300, K1 to 4 are multiplication circuits having a function of weighting data with the coefficients shown in the figure. Also, 8. ~8.
is an addition (to) that adds data that has been given a predetermined weight. The output of the adder 84 is led to a latch circuit Let2, and the output of the adder S is led to a latch circuit Let9. Image data Mat is led to the latch circuit Lat7. The above latch circuit Lat7~
9 constitutes a three-state circuit. The three-state states of the latch circuits Lat7 to Lat9 in this case are determined by the mode signal, clock signal φ01, and the like. A signal obtained by wire-ORing the outputs of these latch circuits Lat 7 to Lat 9 is data YMI of the first correlation calculation result for the luminance signal. This calculation result data YMI can be expressed by the following logical equation according to the mode classification using the above-mentioned code table.

Yyt=(M++14)liio+M:)((α25
(M+IY+M-I?)+α5M@Y)+ ('s+M
m) (a 12 (M+ty +M-,, 10B,!+
On the other hand, looking at the color signal calculation list 1400, in the color signal, the R-Y@ signal and the B-Y signal are extracted and calculated. It is necessary to do it. In color signal calculation, time-sharing calculations are performed on either of the R-Y signal and B-Y signal, which are transmitted every time τ. Regarding this rounded horizontal data, the data at the reference time is (Moo) - Signal 27 behind this (M-1 (1) - Signal 2T ahead (M+,,)
is the calculation target. The first correlation calculation result C for color signal data is used to obtain a wired oasis from the outputs of the latch circuits t10 to t12. The first correlation calculation result for this color signal C! is expressed by the following equation.

Het = (Mt + pigeon) M@ma + (hato 10 edition) (0,25 (M
+lY +M-I? )+uMad+(Mt+Ma
) (0,125(M+sy+M-tv+B@y+%y
)+0.5May) ・”-...(12) Furthermore,
@ In Figure 26, the weighting coefficient for data applied to the multiplication circuit is α5.0.25. α125 is set, but in order to configure this, it is sufficient to use a one-way configuration in which a predetermined coefficient is determined by an adder using the bit shift method.In addition, the data as the calculation result is rounded to 6 bits and sanded. , the final output data YMfsCizl is 6-bit data.

In this way, the first correlation calculation of the image data shown in creations (8) and (9) does not equivalently apply a filter effect having the well-known comb filter characteristics to the image data.

(Generation of tie-building signal during data conversion of 8/P, 8/i") The result of the correlation calculation obtained by processing the data in this way is that the luminance signal data is field The color signal data is stored in the field memory 2 in the memory 140G.
It is stored after being ψ-converted to 500. Then, rounding to perform the second correlation operation, these field memories 1
After reading out the 9 data stored in 400.2500, the data is subjected to φ conversion. This has already been explained using Fig. 19, but Fig. 428 shows data 87P, P
The details of the circuit that performs /S conversion are shown below. In FIG. 28 1, the luminance signal data to be subjected to ψ conversion is led to 6-bit latch circuits Lat1411-1415 (2).

Each of these latch circuits 12 receives a conversion timing pulse 8P generated by a conversion timing signal generation circuit 2819.
・~8F4 is led, and the latch circuit Lat1411
The output of ~1415 is a latch circuit La consisting of 30 bits.
t 14164 knee supplied. This latch circuit 1
As the clock signal 416, a signal W8TY generated in the upper 118/P conversion tying circuit 2819 is given. The 30-bit output of this latch circuit Lat141G d2 Obtains ψ-converted image data ◎ This ψ-converted signal data rate is compared to the data rate before ψ conversion, and the image display mode is indicated by 111. When in mode, it is Zo, and in -10m island mode, it is “Ao”.
becomes. This means that in the mode table mentioned above, when the display mode is H, M, -, the data rate in the horizontal direction is H.
When d1=% and the display mode is m:, ml, Hd
It corresponds to l- and nine.

Also, φ conversion 1 for 2 color signal data = approximately the same circuit configuration as 1 path of P/8 conversion for luminance signals ◎ 8β conversion timing signal for chrominance signal data is a three-state circuit T8 can be controlled by the image display mode.

In other words, if the image display mode is ml + m, "@
Y~8P4! is used as the 8/P conversion timing pulse, and the mode is (m, + ms) (display mode is ml@m).

If the image display mode is tn
, +-, it is also used as a ψ conversion timing signal for color signal data ◎ Signal data of color signal 1 degree □ with respect to luminance signal is h. Although the B/P conversion tie < y tag is different, the luminance signal In order to reduce the number of single-path elements by using the ψ conversion timing signal for the chrominance signal data as a timing signal to convert the color signal data to 8/P4, this embodiment uses a ψ timing generation circuit that seals the luminance signal system and the chrominance signal system. In this way, the φ conversion timing signal 1gl path for the luminance signal system and chrominance signal system can be shared according to the display mode I, which reduces the number of circuit elements and allows the luminance signal 1; A combination of required data reduction coefficients and color signal reduction coefficients can be easily satisfied without complicating the circuit configuration, and many image display modes can be set. Note that the field memory 1420. which sends and receives data to and from the ψ-converted II1 data.
In this embodiment, 2520 has the same bit configuration as 211 and 2, respectively.

As mentioned above, there are two data sampling circuits ζ when performing the first correlation calculation on the field memories 1420 and 2520 and converting the image data into 8/P. Readout Pμ
The case of conversion will be described next.

The data stored in the field memories 1420 and 2520 are transferred to a luminance signal data conversion circuit 1460 and a color signal data conversion circuit 2 to perform a second correlation calculation.
At 530, φ conversion of the data is performed. And the above φ
Tie control for φ conversion of data in the conversion circuits 1460 and 2530 occurs in the P/8 ting generation (b) path 1450.

FIG. 29 shows details of the φ tie generation circuit 145°. P/8 tie pulse generation circuit 1450 Qualitatively consists of a shift register, and the 8/P pulse generated by the ψ conversion timing signal generation circuit explained in FIG. 20 above.
The conversion timing signal 8F and the signal φ0- are input, and the output data 8. ．． 8□...81. is generated. ◎The tie chart is shown in Fig. 30.

(Generation of field memory control signal and field memory address open address generation) Earlier, we talked about the ψ conversion and 8/P conversion of data when sending and receiving image data to and from the field memory. , Next, a circuit that controls the address of the field memory and generates an address signal, and the field memory lock control shown in FIG.
Regarding the field memory address generation circuit 144G, particularly regarding how the address is controlled for each display image mode, refer to Figure MB2 showing details of the field memory address generation circuit 1430 and the field memory address generation circuit 1440. The shift register S- of the field memory control circuit 1430 in FIG. 31 uses the output φt of the horizontal counter CTR(1) 2804 shown in FIG. The signal VT expressed as is input. The outputs (e, D) of this shift register 8B.

g) and the mode signal (mt + m, ) for selecting the mode in which Hdi = in the mode table described above, a preset data import signal P + G and a data preset signal PG are obtained. In addition, it is a signal that defines the tie ζ puffer for twin data extraction, and is a signal V expressed by the first G formula.
T is input to the shift register 8R, and the output B of the shift register 8B is used to obtain the preset signal PG' of the write address counter c'ra(w) of the field memory. In addition, Fig. 32 shows the upper 1ki
Faith 4φ1. VT, PTG, KG, VT,, PG' (
A DI timing chart is shown.

Field memory ζ: When loading stored data (=Factors for determining the address include whether the displayed image is in zoom-up mode or not, and whether the displayed image is frozen.

FIG. 33 is a diagram showing the address area of the field memory in relation to the display drawing. (indicating F-in). In this case, the reduced data of the sub-screen is stored in the address area of the shaded area.
Figure Φ) shows the address area of the field screen when the display mode is m:, and in this case, the small data of the four sub-screens are stored at the address of the shaded area. Third
As you can see by comparing (1) and (b) in Figure 3,
The sum of the two areas has a smaller area of 1108 minutes. This is because in m: mode, the amount of image data is small because the image data is incorporated into the cropped portion of the entire screen as shown in Figure 17. In this case, in order to zoom up and obtain a good image, Data interpolation is performed on the output side of field measurement. The reason why the capacity of the field memory is small is that the correlation calculation is performed twice on the input/output side of the field memory.

1 m1 as shown by the slope in Figure 33 (ri*tb)
Image data in direction ii is written by writing the image data to the main screen and then skipping the addresses other than the sloped area. In this way, the image data of the main screen is written. ◎By reading out the data written to the field memory in this way using addressing in the normal mode, a sub-screen is inserted into the main screen and a good image is displayed. To explain about skipping the address mentioned above,
[The good signal shown in FIG. 32 is related to the address control of the j sub-screen.

In the field memory control circuit 1430p field memory address generation circuit 1440 in the JIE 31 diagram, the signal KG is guided to the reset terminal of a field memory write address generation counter CTR (W) consisting of a 13-stage frequency dividing circuit. In addition, the preset data acquisition signal P-
) G is the control terminal of the buffer T81441 (: both led and 4 negative) 1442m1443 and latch circuit Ll
Reset terminal 4 of t1444: led.

The output of 1442 is led to the control 1 terminal of the buffer 1445, which leads preset data PR8 to address 2, AD, 1.0 This preset data determines the start address where the image data of the sub-screen is stored. In this embodiment, it is set to +23569I. Furthermore, the output of the gate 1443 is transferred to the buffer T8144.
6 and leads the start address (+4692) to the address lines AD, . Signal PT shown in Figure 32
In the region where G is rOJ, address 2 in AD town is connected to address lines AD, . Address 2 in ADI1
1 is led to the addition -81447. To write one screen of image data, as shown in FIG. 33: Start address data +24 for skipping an address is led to a 4-Ni latch circuit 1444 for skipping an address by +24. The output of this latch circuit Lat 1444 is led to an adder 81447, and the output of this adder is led to a preset terminal of the counter CTR(W). The preset and gate signals of this color/reference CTB (W) are obtained by the signal PG' and the PG logical sum PG'+PG shown in FIG. 9, the input signal of address counter CTR(W) is (VT(m,'+ml)+VT,) HT
-Logic operation 1 of W8TY; supplied from the output of the gate circuit 1431.

On the other hand, the read address AD& of the field memory is selectively outputted by the signal wg' via the buffer T8144g. This switching makes it possible to write data for IH and read data for 2H within 18 periods. The reason why data for H2H is read out during the IH period other than storing data for IH is that when performing the second correlation calculation described later, data for three lines (
T.

M, B). In other words, IH
By controlling the address that apparently writes 2H worth of data within the period, it is possible to perform two correlation calculations on the input and output side of the field meter. A wide variety of image modes can be set.

Note that the field memory address is buffer 8T (L
), 19T(1-1). in this case,
The address of the upper bit is outputted via 8T(H), and the address of the lower bit is outputted via 8T(L), and this switching control is performed by the ψ conversion tie construction control signal generation circuit 2818 shown in FIG. Controlled by signals CAG, KA().

Furthermore, when a control signal for a mode for freezing the image is input to the input of the shift register 8B in FIG. 31, the gate circuit 1
432 is closed. As a result, the signal Wl! which is a write permission signal for the field memory 礪! is shut off @As a result, writing of image data to the field memory is stopped.

In this case, in order to prevent data writing from being stopped in the middle of the II1 direct screen image data, the signal Vaa, which is the reference signal for the vertical period, is used to reset the data. With the writing of new image data stopped in this way, the reading of the iii data (main screen timing signal generation) is then performed. Details of generation circuit 3000 will be explained using FIG. 34.

In Fig. 34, the main screen horizontal synchronization signal H, 8YNC
is guided to a phase comparator 3001, and a horizontal flyback signal HFB is applied to this phase comparator 3001. The output of the phase comparator 3001 is led to an oscillator 3002, and control is performed in the phase comparison b aoot so that the phase difference between the horizontal synchronizing signals H, 8YNC and the horizontal flyback signal 1 (FB) becomes zero.

The oscillation frequency φm of the oscillator 3002 is φ(n-880
7ww (/MM main screen horizontal frequency), this signal is led to the h frequency divider circuit 3003. And this frequency dividing circuit 3
The output φ- of 003 is led to the main screen horizontal counter CT RQI3004, which is a nine-stage frequency dividing stage, and the output of this counter c'raH is led to the main screen horizontal timing circuit 300.
54; led to zero, the above counter c'ralJ
I is a counter CTR (2) 3006 for each of the signals /HM*2/MM, and a vertical counter C for synchronous reproduction.
It is led to the output of TR(7)3007. Furthermore, the output of the counter CT RQ13004 is also led to the vertical synchronization detection circuit 3008 of the main screen. The counter CTR 3006 is a counter consisting of a frequency division stage of 9WN, and the output of a predetermined stage is outputted to the main screen tie generation circuit 3006.
is guided by.

Then, the vertical synchronization signal v18YNC is subjected to vertical synchronization detection by the above-mentioned - series synchronization signal detection circuit 3008, and the detection signal V? The output of the counter CT RO13007 is led to a self-reset pulse generation circuit 31009, which is controlled by a mode signal V, and sends the self-reset signal and comparison pulse to a screen synchronization pull-in circuit 3010. Output to. The screen synchronization pull-in circuit 3010 is controlled by the mode signal vM to generate a vertical reset signal VRM, and also supplies a vertical drive signal fvDM to the synchronization output circuit 3300.

In addition, the color/color main screen horizontal counter CTIIQ13
The output of 004 is led to a horizontal drive signal generation circuit 3011, which generates a horizontal drive signal fHDM, and this signal is supplied to the synchronization output circuit 3300.

The outputs of the main screen horizontal timing signal 3005 and the vertical screen timing signal 3012 are outputted by an output buffer address generation circuit 3013, a display effect signal generation circuit 3o15 that gives special effects to the display of the sub screen, and an analog signal switching signal DG at the output stage. Analog switching control circuit 3014 that occurs
is supplied to.

In the main screen timing generation circuit 3000 shown in FIG. 34, the phase comparator 3001 is supplied with the display mode mH+m to the screen synchronization detection circuit 3008. At this time, the phase comparator circuit 3011 is set to the non-moving state 6. In this display mode, the oscillation a 3002 freely oscillates at the center frequency. When the display image is displayed in a static state, the above-mentioned oscillation! 3002 is caused to freely oscillate and a synchronization signal is generated in the internal circuit.

That is, when displaying a screen in a stationary state, synchronization is performed using the output signal C2 of the oscillator 2000 in a continuous free-run state, and the displayed image ( ; Prevent the influence from spreading.

In addition, - series synchronization pull-in circuit 3010 (:, mode signal to be applied) handles synchronization signal
A signal that determines whether or not it is within the pull-in range "e")
vm-Of) J-When force f) y/CT
The so-called countdown operation (a two-up synchronization system signal is generated) is performed by the RQ130G7s vertical synchronization pull-in circuit 3010 and the self-reset pulse generation circuit 3009.The above mode signal V is the same as the above mode signal m@@+m.
,, The synchronization system is given priority to external synchronization ◇In other words, when the display 1 is in stop mode and the applied synchronization signal is outside the pull-in range of the vertical synchronization pull-in circuit, the countdown operation causes internal synchronization. Generates a synchronization signal. #
Figure I35 shows a timing chart of signals related to the □ countdown operation for obtaining the synchronization signal for the ζ2 main image direction according to the four internal rules. The output, To-, indicates the comparison pulse. As can be seen from the figure, the driver hull width of the direct drive signal/vmw is 11.5T (T: main 1- synchronization signal system signal is determined as described above, but the horizontal output circuit of the display device is : In addition, the phase difference TI between the horizontal drive pulse /gai< and the above counter C'rR (output /WM of 113004) and the pulse width TVs vertical synchronization pull-in circuit 3010
It can be made variable by configuring the m-horizontal drive signal generation circuit as shown in FIG. By controlling the capacitance value of the capacitor 03EsCW that determines the time constant of the monostaple multivibrator MM of the horizontal drive signal generation circuit 3011 having the circuit configuration shown in FIG. 35, the above-mentioned phase difference T1 pulse width T is controlled. Ru. This signal/IIM
The relationship between the phase difference "Xs" and the horizontal drive signal fvzrrw and the signal /MDM whose pulse width is controlled is shown in Figure N37.

(Horizontal and 1-direction Display Position Definition of Display Screen) Next, the main screen timing generation circuit 3000 generates a signal for defining the position of the display screen in the horizontal and vertical directions, and this will be explained.

# first! As described in FIG. 4, the display position of the sub-screen is set to the position indicated by Pl-wP in the same figure.

Now, for example, to display the screen at the right corner positionkPs
” t, and other positions P1−
P4 shall be defined in the same way.0 and N
The main screen horizontal timing circuit 3005 in Figure 34 is the 38th
As shown in the figure, based on the horizontal direction reset signal HMR, signals TRIM to Tll4M are generated according to the timing chart of FIG. 38, which defines the horizontal display position according to the display position regulation shown in FIG. Then, signals G,,' are generated that define horizontal display as shown by the following logical equation.

G MH'w= Ts@IM (Pl + P4)m
o+ + %H1(Pl +P@)111111 +
T'liaM (P@+P4)Ill(11+Tl1
4M (P1+P1)mm+T-y (mn+rrsu
)......(Is) On the other hand, regarding the vertical position regulation, the -direct direction timing circuit 3012 uses the signals TVIMs to TV4M according to the timing chart of Fig. 3-9. A signal (f
, v.

GMl=sTyIM (Pm+i'a)a*t+Tv*
u(1't+Pt)+"sn+'r,,(Pm+
P4 ) mH+ TiI4 (PH+ E'@) m
(1! + Ty4g (m@@ + rnlB6)
...I The display area is determined by

(Display effect, switching with analog signal) FIG. 40 shows the output buffer address generation circuit 3013, the analog switching signal generation circuit 3015. and details of the display effect signal generation circuit 3015. The gate circuit AND of the output buffer address generation circuit 3013 performs a logical product operation of the signal GMII' for specifying the display position in the horizontal direction and the signal GMII' for specifying the display position in the vertical direction. Outputs a signal GMII that defines the display position. This signal GMII is the shift register 81L31
The output of this shift register 8R31 is input to the 0 counter CTR@ which is added to the counter CTRClυ.
1 is a nine-stage counter, which uses the result of the A-B output logic operation of the shift register as a reset signal, and generates at its output a start-up address signal for the output panzer memory, which will be described later.

9. Output buffer address generation circuit 301B of output buffer address generation circuit 301B receives 1IiiiI of the signals generated in mode signal generation circuit 2900 in FIG.
The gate circuit AND is closed in response to a selection signal Mll indicating whether the t1 display is to be performed as an analog display or the Ii image display that is obtained by digitally processing the image data. This gate circuit AN
The logical value of D is used as a control signal DG to determine whether to control the period in which analog signals are displayed and the period in which digital signals are displayed in one horizontal period. Also, shift register 8
The output pin of a32 generates signals G and M' which are delayed in phase by one horizontal period with respect to the signals G and M described above. This signal company 0'
When displaying the ii collapse display, it takes time to calculate data during approximately the IH period, so the actual image display actually takes 2
It is used as a control signal to perform the H delay.

(Display Effect) As a display effect, in this embodiment, the display on the sub-screen is not displayed instantaneously, but the door gradually opens.The display effect signal generation circuit 3015 uses the display effect as a time reference signal for performing the display effect. uses a signal VRM having a pulse width of 111 periods on the main screen. The output for the second stage and the output for the third stage of the counter CT R3QQ to which this signal VRM is input are selectively switched by an external control signal from the switch 8W. Now, if the switch 8W is connected to the power supply side, the output signal CPNW of the gate circuit OR becomes a 1 second clock signal. Also, when the switch SW is set to the ground side, a clock pulse of seconds is obtained. The above signal CI
'NY becomes a clock pulse for the shift register 8130G when the display effect command signal M, o for performing the display effect is applied to the shift register 8R300. When the above command signal becomes "1", the shift register 8
A signal Prd obtained by performing the calculation A-B on the outputs A and H of 1'L30G is obtained as the output of the gate circuit AND2. This signal Prd is a down-counting counter consisting of seven stages.
riDCTRI.

Up-count counter UCTRI to DATAI*2
(In this embodiment, it is set to 40.).

The preset data at this time defines the position on the screen from which the door effect for display 1 is started. The clock signal for the counter DCTE%1°UCTR2 is the signal CPH.

A good signal OP that performs logical product on the output indicated by C of the shift register 8R300 and the output of the gate circuit NANDI.
, using MaG. The up counter 0CTRI counts up this clock signal, and the down counter DCTRI counts down this clock signal.

Then, the up counter 0CTR1 is 80 (Ql”Q
? 1), the clock signal is blocked by the output of the gate circuit NANDI (CP)+va=1).

Furthermore, the 7-bit output of down counter DCTa1 is supplied to converter CPAI. Similarly, up counter U
The 7-bit output of CTRI is also supplied to comparator CF2. On the other hand, the signal obtained by inverting the output I of the shift register aa310 is used as the reset number, and the output l and the signal φ
The 7-bit output of the counter CTR301, which uses the AND with the tumor ◎ (4407W) as a clock signal, is the comparator CP.
A1.2 is supplied. The coincidence output CMP*s of the comparator CPAI=scoincidence output CMP of the comparator CPA2 is led to gate circuits NAND2 and 3, respectively. The outputs of the gate circuit NAND2.3 are set terminal B and reset terminal R of flip-flop FF300, respectively.
At the output of the FF 30, the display screen generates a signal indicating that the door is full due to the door effect here. In order to perform the door effect in which both sides of the display are gradually opened without disturbing the image in the initial stage, the display effect operation is performed after the counters UCTRI and DCTRI are preset. Figure $41 is a timing chart showing that the display effect is performed after the counter is preset. As shown in the figure, after a signal MDo for performing a display effect is generated, preset data is generated to generate preset data for counters UCTRI and DCTRI, and then these counters;
; 91A is generated as a clock signal CP-ma*.

Further, FIG. 42 shows a timing chart for explaining display effects. In the figure, clock signals CP, matk,
The relationship between the counter address of the down counter, the counter address of the up counter, and the matching output of the comparator CPA1.2 is shown. As can be seen from the figure, the counter addresses are all based on 40 and count up and count down to 0. This means that the image display corresponding to counter address 40 is expanded horizontally. As the display screen is enlarged, the display image surface of the sub-screen is enlarged as the pulse width of the output signal of the flip-flop Fi'3Q is enlarged as shown in FIG. Performing a logical OR operation with the output of FF3Q From C2, this is performed according to the size of the sub-screen determined for each display mode.〇 (Field memory data reading control) Field memory also; Stored image data It is necessary to read the data in order to perform the second correlation performance.In this case, the timing of the sub-screen to perform the field measurement The stored image data of the sub-screen is synchronized with the timing of the main screen.
= Must be replaced and read out. A control circuit for this purpose is a field memory read address generation circuit 3100 shown in FIG. The block circuit configuration of this field memory read address generation circuit 3100 is shown in FIG. 43. In FIG. A field memory read timing circuit 3020 generates various field memory read timing signals by inputting G, MAI, and GMII.

This field memory read timing generation circuit 30
In response to the timing signal 671 generated at 20, it is determined whether to read data for one line period (ITll1) of the sub screen from the field memory during one line period (ITNM) of the main screen or to read data for two lines. The display image mode is determined by the field memory data read monitor circuit 30214. One output of the field memory data read monitor circuit 3021 controls the line memory address generation circuit 3022 and generates the line memory address 697 in the twin memory 4 address generation circuit 3022.

In addition, the field memory readout circuit 3021
The other output 677 and the sub-screen timing signal 672 are led to the field memory read quad occurrence times @3G214 which generates the field memory read clock. The output 682 of the field memory read clock generation circuit 3023 is used as a clock signal for the field memory read address generation counter 3024. Further, the skip timing generation circuit 3025
In the case of data indexing when performing the second correlation calculation, a timing signal for skipping the read address of the field memory is generated in accordance with the number of lines for which data is indexed.

The skip data generation circuit 3026 is a circuit for generating a timing signal for skipping the read address of the field memory according to the image display mode.

This skip data generation circuit 3026 has a read address generation circuit 3 that contains skip data and fields to determine how many read addresses are to be skipped.
The count value of 024 is added by an adder 3027.

The output of the adder 3027 is then preset to the value of the counter 3024 by the output 680 of the skip timing generation circuit 3025. As a result, the value of the field memory read address generation counter is skipped, and the read address of the field memory is skipped.O By skipping the field memory address in this way, the required number of lines of the image data of the field memory is skipped. Read the data.

In addition, the buffer memory write clock control circuit 3028 in FIG. 43 controls the image display mode by controlling the write clock for the buffer memory of the luminance signal output buffer circuit 160G and the color signal output buffer circuit 2700 shown in FIG. ; Occurs accordingly. The clock signal generated by the buffer memory write clock control circuit 3028 is led to a buffer memory write address generation circuit 3029 (::), which generates the address 694 of the buffer memory in response to the image display mode signal 6906.

In this way (=, the field memory read address generation circuit 3100 performs the correlation calculation of #I2 from the field memory. FIG. 44 has the function of
, 3025.

In FIG. 44, the main screen timing signal GMT 605
@GM Ma'618. ~ Cao 607 are each shift register 8
It is led to R700°8B701.8LL704. The clock signal φ of these shift registers S8 is a timing signal 8F for converting the data of the sub-screen shown in FIG. 3121 by 8/P.

Use.

5ay for the timing signal 8P when converting the output of the shift register 8R700 and rigid image direction data into ψ
oo*-aa7ooN-8P4) theorymflll[&
Row 5-ry output 674 of toggle door 03 resets field memory read address counter 3024. On the other hand, shift register 8fL704) output (8
The output cuff 45 of the AND gate circuit 706 of the R704A-8R704B-8F4) is used as a reset signal for a one-stage RIH counter 733 and a line memory address signal 711 to be described later.

Here, the output B# 7 of shift register 8fL704
32 is defined as CkH.

Figure @45 shows the S/P conversion timing signal BP* 321 @8Pa 323 of the sub-screen data, and the main screen timing signal GM Maro 05. Output 674 of gate 703. Ih
A time chart of the output signal OH732 of the output cuff 45 of the No. G (m601 game) 706 and the shift register 8R704 is shown. To explain Figure @44 with reference to this Figure 45, the output signal Gi of the shift register 704 synchronized with the clock signal "5321 (732 is the RIH
It is used as a clock signal for the counter 733. When the signal GH732 rises, the output Q7 of all(j'F)
34 rises ◇At this time, the output of the gate circuit 725 (or game) 705 (81% + SF3) signal 726 is obtained. In addition, IH data monitor counter 72
The above signal 726 is added to the clock of 7 (8F, +
Count the clocks represented by 8P, ). When the output 28 of address 32 Q of the counter 727 becomes "L" and the signals 8F and 319 are input, the AND logic of the gate circuit 729 is established and the output of the gate circuit 731;
1) (FF 733 is reset, i.e. R114
The output RIB signal 734 of the 1i'F 733 has a period of "32 clocks with the clock of sp+8F4" for reading the data of IHMIlkl of the field memory.
1”. The RIH signal 734 is guided to a shift register 8R746, and in synchronization with the falling edge of the signal RIH (8R746A-8R746B.8P4), the AND operation obtains a reset signal 711 for the line memory address counter. Furthermore, the output of the gate circuit 707 is ANDed with a mode signal (ml@) 741 and an output Q739 of FF3, which will be described later, to obtain a field memory preset signal 68G. Output B of shift register 8 R746 is inverted by inverter 715 and sent to counter 718.
(referred to as fL2HFF). counter 7
18 is mode signal (men+”to) 71L mH
- When mH713 is each "0", the operation is performed so that the lH data read period becomes "1" similarly to the above RIHFF. Now, the image display mode signal 73alS[1jt
7) time, aznrr 718 (7) Q output 82) 1
720 is directed to 81L736. (me-mo+)
' Generate field memory preset signal 743 from logical product of 8R736A and 5R736B-8P4. Note that the gate circuit 702 generates a signal that defines the field memory refresh period of the DRAM configuration, and the result of the AND operation of this signal with (8P, +8P4) is added to the OR gate 710.

FIG. 46 shows a time chart of the main signals among the signals treated in FIG. 44 above.

Fig. 46 Ship = GH732's in-cycle signal RIH
734.

R2) 172G occurs. That is, the figure shows that it is possible to read data for 2 to of sub-screens from the field memory during the ITMM period of the main screen.

Note that determining whether to read IH worth of data or 2F worth of data from the signal GH cycle period field memory is performed by the second correlation calculation on the field memory output side according to the mode in the image display mode table described above. It depends on how the reduction and expansion operations are performed.

(Address counter for field memory data readout) FIG. 47 shows the field memory readout address generation counter 302 of the field memory readout address generation/operation control path 3100 shown in FIG. 43.
4, adder 3027 e bus data generation circuit 3026 + line memory address generation circuit 3022
, buffer memory write clock control circuit 302B, and buffer memory write address generation circuit 3029. The output 682 of the field memory read clock generation circuit 3023 is a field memory read address counter 750 consisting of a counter 13R.
The reset signal for this counter 750 is the reset pulse 674.

The field memory preset signal 680 generated by the skip timing generation circuit 3025 in the ms, m, . . . -1 mode in the image display mode table is connected to the preset terminal of the carantuff 50.

The counter is preset to a preset value 689 at the timing of the rise of the signal 680. Maku, counter 7
50 output 684 is addition! The other input terminal E of the adder 751 is led to one input terminal of the adder 751.
It is 87. This skip data is +64 addresses (even if the field memory address is advanced by 64) 752 and -32
Address (delay field memory address by 32) 7
53 types of 211 were prepared. This skip data is controlled by the mode signal 685 indicated by the image display mode -〇m+Iz, and when the mode is -ff1ol, data 752 with a value of +64 is skipped, and when the mode is ff1ol, data 753 with a value of -32 is skipped Adder 3027 (line memory addressing) Line memory address generation circuit 302 is added as data (
fLl)I+R2fi) 11472B Hashi7)
v-) Sufi 8B75&1; Guide boyfriend P/8 /(mi/
(See Figure 3129) No. 81 (No. 21 757) is synchronized. The A output cuff 59 of the shift register 8R758 is ANDed with the clock signal 4-.
60) Serves as a clock input for the line address counter 762. Also, line memory address color/re7
62 generates a line memory address for storing data read from the field memory in the line memory.

The reset signal of the counter 762 is the line memory address generation counter reset signal 711 (Rli (+R2H) 723 or FF3763).
It is used as a clock signal for FF3763 (7)
The outputs FF3Q, LmiLFF3Q e LmW are line memory write and read signals.

One-way communication 1) (R11() 734. (R2)1)
720 are shift registers 8R766, 8 & 765 respectively
1. It is synchronized with the above-mentioned good signal 8 snow 757. Maku, shift register 8R766 output cuff 67 and 8R7
65 output cuffs 68 are each led to 8R76L 8R789 and a clock signal φ,. It is delayed by two clocks. Now, the B output of the shift register 8R767 is set to JH'
, the B output of 8R789 will be called approximately 2H'. OR gate circuit 770ζ; company signal RIH' and signal 76
7 is input and its output is a NOR gate circuit? 71 output counter 72 to buffer memory write address counter 77
Pick up 9 dragons of 4. 9, the signal &2H' is led to the NOR gate 771 via the OR gate circuit 773.

That is, the counter 774E reset signal is obtained before the rise of the signal all(', R2H').The gate circuit 7 provides a clock signal to the counter 774.
78, 779, 780. Further, the clock rate of the clock signal of the counter 774 differs depending on the horizontal data reduction/enlargement coefficient ζ on the field memory output side in each display image mode. When the clock signal of the counter 774 is written as a logical expression, it is as follows.

m,,・R2H'・CT&8Q1・・・・・・・・・・
...9-bit output 694-1 of grudge 1 counter 774
is 0 guided to the buffer memory (buffer memory writing and alignment timing)
The flip-flop (v24) 693 controls the writing and reading of data to and from the buffer memo.
This is a one-stage counter that operates every time the signal GMH607 mentioned above rises. This (FF4) 639 reset is the field memory read address generation circuit 3020 counter reset signal 674.

In this manner, in the image signal geographic circuit shown in FIG. 10, the field memory read address generation and arithmetic control circuit 310G generates the field memory read address (signal 684 in figure j1143).

2-in memory address (signal 697 in FIG. 43) of arithmetic circuits 1500 and 2600, and a write address (signal 697 in FIG. 43) of output buffer memories 1600 and 2700.
A signal 694) in the figure is obtained.

(Second 4@Data complementation and indexing during function calculation) We will discuss the data reduction and expansion calculation circuits 1500 and 2600 according to each mode signal in the display mode table listed above. To understand the expansion operation, the stripe diagram 48 (
a) to (6) will be explained using time charts. Note that the upper timing in the figure is the field memory read timing RIH734, R2H720° and the field memory read address counter preset signal 6.
80. Operation period RIH' 790 or R2H' 7
48 (Jl) shows a time chart when the image display mode is in the mode indicated by -.in@t. According to this figure, 2H worth of digitally processed image data is read from the field memory during one period of Gvw 607, which is one horizontal scanning period of the main screen. The reduction calculation in this mode is performed in the R21 ('791 period), and the calculation results of this period are read into the buffer memory I (described later).The data read into the buffer memory is read out and displayed in the oG167 period. To be done 1
;Become. Further, at the rising edge of the preset signal 680, the field memory read address is skipped by 2H of the sub-screen in this mode. As a result, data for 29 inches, which is necessary for performing the second correlation calculation in this mode, is read out in a period corresponding to 1 line of the main screen.

@48 Figure (b) shows a time chart in the --- electric mode and the --- mode. In this mode as well, 29 ins of T and H are subject to calculation, just like the addition of two straight modes, so it is necessary to read data over two lines.

Figure 48 (C) is an im chart in mo1o-mode.
The data written in the buffer during the IH' period is
Horizontal direction 1; double the data weight; wIA1%&1
The calculation is performed and displayed in the next DG period.

FIG. 48(d) shows a time chart of the ffl, %t mode. Since Hdo=l and Vd6=l, in this mode, it is only necessary to process data on the same line, and the field memory data is processed in one cycle of GMII. Only IH data is read from the field memory and displayed.

Stripe 48 (e) is a time chart in the case of m1o mode, in which a preset signal for the field memory read address counter is generated by the flip-flop Fr3 output of the field memory address generation circuit 322 shown in FIG. The field memory address is pulled back by 32 addresses. Therefore, the data for IH in the field memory will be read out twice.

As shown in FIGS. 48(a) to (e), the data in the field memory in each mode is read out, and the read data is subjected to reduction and enlargement operations in the IRH' or 2RH' period. and stored in buffer memory.

(Second Correlation Calculation) The second correlation calculation using Fig. 9 has already been described, but regarding data interpolation and rejection 1= when performing reduction and expansion calculations using Fig. 49. I will explain further.

Figure 49 shows interpolation 1 collection of data related only to modes in which characteristic calculations are performed among the modes in this embodiment.

Figure 49 (8): Horizontal reduction coefficient in mode Hdo = %, vertical reduction coefficient Vdo =
It is an explanatory diagram when performing a calculation of %. In the figure, O marks indicate data lined up for each data line extracted from the field memory. ) The same applies to the following description.

In the -moI mode shown in Figure (a), for example, n lie/data and n+1 2-in data are extracted from the field memory and used with the data indicated by arrows and the own data. to reduce the size. The O mark in the figure is data that has been interpolated in the horizontal direction, and is displayed in succession on the main screen. In this case, data obtained from two lines of data n+4° and n+5 is displayed on the m+1 line of the main screen. That is, in the vertical direction, three lines of data of the sub l1thl are discarded.

-) in the same figure shows the operation in man mode ◎ That is, Hd
New data is interpolated into the part marked Δ in the figure by the calculation such that o w 2 , Vdo==1. This interpolated data is l
Create only from lines.

FIG. 6(C) shows calculations in mlo mode.

That is, the case of the calculation Hdo=2+"o=" is shown.

In line m in the figure, interpolation calculations are performed using data on both sides. For the m+1 line, data is interpolated by performing upper and lower interpolation and interpolation calculations using four points on the diagonal.

In this case, to generate interpolated data for l line, T (n) + M (n + 1) * B (
m + 2) data for three lines is required.

In the block diagram of the GTO diagram, the arithmetic circuit that performs the above calculation is the field memory output inertia luminance signal arithmetic circuit 150.
0 *Field memory output side color signal calculation circuit 2600
It is. Both of the calculation circuits 150G and 2600 have the same circuit configuration except for a part.

FIG. 50 shows details of the luminance signal calculation circuit 150G.

The luminance signal calculation circuit 1500 is connected to the line memory 802 *
soa.

It is composed of a mesori circuit consisting of 804 and 805, and an arithmetic circuit 8α1 that performs a reduction or enlargement operation according to each mode. Field memory P/8 conversion output data Y@1
35 are led to line memories 802 and 803. The address of the line memory is supplied from the output 697 of the line memory address generation circuit 3022.

In addition, the control signal d for writing and reading each line memory is
is the line memory address generation circuit 3 shown in FIG.
022 7 lip-flops FF3Q and Fr3ζ are supplied.

The luminance signal Y0135. IH play signal 8G6.2H
The play signals 807 are supplied to latch circuits each consisting of 6 bits. Each latch circuit output follows the definition in the Jl127 diagram, and the calculation target signal is B+l YI 6 n, y,
eM□Y0. M, Y, , M-, Y, , T smell
, t 'r, y01 T-t y, s T@ Yl
#I&0 is shown in the diagram using the symbol l. In the figure, each signal 801, 808, 809, 810, 811
, 812, and 813 are led to an arithmetic circuit consisting of a multiplication circuit and an adder similar to the correlation arithmetic circuit of jll shown in FIG. Below, I will explain the creation by listing the calculation formulas for each mode with reference to the directions below. 〇 Figure 50 The output of the latch circuit is -・fno*mode time reef:
is 0.5BJOY (1+ 0.258.Y, +0.12
5 (M-KameY, +M◆OtoriYa) is obtained. The clock of the latch circuit 815 will be described in detail later using FIG. 45. ), and a signal 817 is applied to the T terminal. Also, −・−
The calculation of the screen is 0,5MoY@+α25(B,Y,+
ToYe)DeJ) s Operation result y f circuit 81
Guided by 8. The clock of the latch circuit 81g is φ-ti
The e'r terminal has -・-! is added. In addition, in the calculation of m-line and - mode, which performs the expansion calculation of horizontal direction Hdo = It is understood that the line operations are common. That is, in the ml mode, the signal that determines the m line and m+2 lie y fathom is the 4th signal.
Figure 4 PF4784 (7) Signal, m, -FF4Q
The signal subjected to the AND operation and the result of the logical operation in the -1 mode are the same. In addition, in the arithmetic circuit cylinder 50 diagram ζ:, the M and Y signals are led to the latch circuit 834.
The latch circuit 834 has 0-5 (MoYs4'M+s
The calculation result of Ys) is derived. This latch 834
*The clock φ of 831 becomes the φ10 signal. on the other hand,
φS is connected to the T terminal of the latch circuit 831, φ10 is applied to the T terminal of the latch circuit 83447), and the outputs of the latch circuits 831 and 834 are wired ORed and applied to the latch circuit 843. The clock of the latch circuit 843 is φ-=2φ-6, and the T terminal ζ= is mrh, +
mi, -FP4Q f344 is added. When the image display mode is -ml)1, no calculation is performed, so the Y signal is directly led to the latch circuit 837. The clock of the latch circuit 837 is φ-, and the T terminal has m, -8
It is 38. Then, the operation in −・−1 mode is 05”o
Ytr+ O-125('+IYo+MB%
+BeYa+ToY・), the calculation result 820 is led to the latch circuit 821.
is φm, and a signal m,·m·, is applied to the T terminal. In addition, in #I49 (C) in the ml mode, two types of calculations are used to obtain the calculation results for the m+1 line. In this case, the latch circuit 824 is is the result of interpolation calculation 0.5 (B11Y@+T, Y,) using the data of the upper and lower 2 lines 820
is being guided. On the other hand, the latch circuit 827ζ; is 0.2
5 (B, Y, + T, Y, +B+, Y, + T+, Y
, ) is derived, and the latch circuit 824 ,
The clock and T terminal of 827 are connected to the latch circuit 831.827.
834. That is, φan is led to the clock terminal of the launch circuit 824, the T terminal 825, and the clock terminal of the latch circuit 827. A φ1o signal is applied to the T terminal 829 of the latch circuit 827. Then, the clock of the final stage latch circuit 840 becomes φ,
The m, oe h'V4Q signals are applied to the T terminal 841.

Data 1 in which each latch circuit output above is wired-ORed
37 is written to the buffer memory.

(Correlation Calculation for Color Signals) The second correlation calculation for luminance signals has been explained using FIG.

This applies to brightness signal calculations except for reduction calculations in I mode.

FIG. 51 shows an In, l mode reduction arithmetic circuit. Drinking・
Calculation result of color signal in mode, (0,5"oC
o + 0.25 BoCo + 0.125 (M+
ICo+M-Ico)) 890 is latch circuit 8
Guided by 91. Note that the above MIIC・, B10.・・・
Symbols such as ・ etc. are attached according to the symbols in FIG. 50.

φ-. The output L of the latch circuit 891 with the clock signal
■893. and Lh 890 are led to a 6-bit data selector 894. This data selector 894 has a control X terminal 895, and when the X terminal is "1",
The signal LA 890- is routed to the output 896 and the X terminal power [o
When J, it operates to direct the signal Lm 893 to the output 896 t knee.

Now, the CTR81Q* signal is led to the X terminal, and φL(φ& =CTR81Q+ '
φ10) and a --.-2 signal to the T terminal 899, a reduced signal in the --.-. mode is obtained at the output of the latch circuit. FIG. 52 shows a time chart of data during correlation calculation for the color signal shown in FIG. 51.

In this FIG. 52, the calculation ice synchronized with the clock φ-0, that is, the data of 890 points are, for example, R-Y, B-Y, R.
-Y, . . . are flowing in this order. This data flow is controlled by the multiplex signal CTR81Qm port, and φ
By latching with the program signal, the latch circuit 897
Output 126 has 几-Y', B-Y', R,-Y',
hI indicated by . . .; reduced color signal data is obtained.

In FIG. 51, which shows a correlation calculation circuit for color signals, m, ・m
In the et mode as well, the sign reduction operation is performed using the same circuit configuration as in the -fnot mode. The color calculation output 126 obtained according to each mode is written into a buffer memory (2).

(Writing data to output buffer memory) FIG. 53 shows a specific circuit diagram of the luminance signal output buffer 1600 and the color signal output buffer 2700.

In FIG. 53, buffer memory write address 694-1.
Write/read control signal (Fig. 47 PP4 output) 694
-2, 694-3 and buffer memory read address 566 are switching buffer circuit 85L 857.8
Guided to 5L859. The switching buffer circuit is controlled by the control # signal 6.
94-2 e writes to data buffer line memories 850, 851, 853, and 854 according to 694-3, and supplies the exposed addresses 8, 60, and 861.

Now, when the control signal 694-3 is "1", the line memories 851 and 854 are in the write mode, the write address 694-1 is led to the address 861, and data is written. At this time, the control signal 694-2
is "0", and the line memories 850 and 853
reads data according to the start address 860. The buffer line memory luminance signal output 852 is directed to a launch 862 for phasing with the chrominance signal. Further, the output of the latch 862 is further led to two stages of latches 863 and 864 to obtain a 6-bit luminance signal output Yout 139. The color signal buffer memory output 855 has different R-Y and B-Y signal trains depending on the mode.

FIG. 54 shows a signal train in m, . . . +- mode.

FIG. 55 shows a signal train in the m,0+''Os mode.

To further explain the circuit of FIG. 53 with reference to FIGS. 54 and 55, the latch circuit 865 in FIG. It is a circuit. In each latch circuit, B-Y,
The fL-Y signal is detected by controlling the clocks φm-v 881 and φa-y 822 guided to the respective latch circuits. Also, counter FF5870
The input is the inverse φ of 614 (see FIG. 40). Crow 867
is input. The input of the counter FF6871 is derived from the Q and output of i'F5870. Kara y again
Reset terminal of fi 870, 871: Reset F signal 61 of buffer memory read address counter
6 (see Figure 40) is derived. As a result, the latch clock φm-v881-φ1-Y822 is obtained by the following logical formula.

Ih-y-([11m+msoo)"φ5m5n ・"6
Q Taki””am””1・;dBgB・FF5(+Shin1
−(14・φa−y−(mom”1llo*)・φ, −
* FF@Q1+fll@m”Ql @I’m ””
"""" Gate circuits 874, 875, 876, 8
77 and 879.880 are gate circuits that realize the logic of the above two formulas. FIGS. 54 and 55 show these tie charts in the F-view mode and the H-, D-, D-mode.

As you can see from the timing chart (:, φm-y88
By providing Lφa-v 882, the latch 86
The output of latch 866 provides the B-Yout 129 signal, and the output of latch 866 provides the R-Yout 128 signal. Also, in Figure 53, Yout 139, B -Y
out 129, R-Yout 128 and radius a
m 867 inverted signal D/A converter clock φD
883 are each led to a D/A converter circuit.

In the block diagram 1 of FIG. 10 mentioned above, Yout1
39 is guided to a D/A converter 1700 and Y-DAC 140 and converted into an analog signal. Similarly, R-Yout
128 is led to B-yDAC 2000 and converted to an analog signal, and B-Yout 129 is led to B-YDAC 21
00E and converted to an analog signal. The converted analog signals are sent to buffer amplifier circuits 1800.2100.
2200E, the DC level adjustment, gain adjustment, and analog converted luminance signal is sent to the luminance signal switching circuit 19004.The 0 sudden signal is sent to the chrominance signal switching circuit 2.
Guided by 300.

The analog switching signal DG mentioned above has both switching circuits 1900°2
300, and the output circuit 3200 (second lead,
When DG167 is "O", the main screen signal Y, E4. ,
-Y, B-Y power switching circuit output (; led 1301
131 and 132 are led to an output circuit 3220, and an output circuit output 133 drives a CRT 134.

(Effects of the Present Invention) As is clear from the above description, according to the present invention, when inserting a sub screen into the main screen and projecting it, the first screen is inserted through the field memory. Since the @2 correlation calculation is performed, many types of correlation calculations can be set for image data, and the image display format can be set in multiple modes. The degree of freedom in selecting the image mode is not limited to the size of the display screen, but also applies to the selection of whether to display a moving image or a still image, and the selection of the mode of whether or not to display a zoomed-in image.

First, the image data when inserting a sub screen on both main sides is
Within one horizontal period of the main screen; the image data for one horizontal period of the digitally processed sub-screen is written to the field memory, and 4 = multiple horizontal periods of the sub-screen (two horizontal periods in this example). Since image data is read out, the line correlation correlation calculation can be performed on multiple lines of data. This means that even when performing correlation calculations in the horizontal direction, not only the current line but also the lligI& data of other lines are subjected to the correlation calculations, so that an image with good resolution can be obtained.

Also, regarding the synchronization system, when inserting a sub-screen into the main screen, synchronization of the sub-screen is performed using the synchronization system of the main screen (image processing is performed in turn, so no synchronization disturbances of the inserted image occur. .Furthermore, regarding the synchronization of the main screen or sub-screen itself,
It is determined whether the supplied synchronization signal is within the internal synchronization pull-in range.

If it is within the pull-in range, it is synchronized by internal synchronization, and if it is outside the pull-in range, it is reset by the synchronization signal supplied to the internal synchronization system, and then shifts to internal synchronization thread. can be kept stable.

In history, the correlation operation @1. Since it is performed separately into the correlation calculation of @2, when performing the correlation calculation with a single calculation (the second case requires a large field memory capacity,
In the present invention, the capacity of the field memory required for correlation calculation is relatively small. This means that if you reduce the display area of the sub-screen to be inserted, the image data will be rejected, but this data will be rejected multiple times on the input/output side of the field memory, so the amount of field memory will be reduced. This is understandable because it can be done easily. Also, the luminance signal and the color signal: Il! of the field memory for the two! Since the 11IPN configuration is substantially the same, the address (b) path can also be configured substantially the same, so the image signal processing circuit according to the present invention also has an effect suitable for integration.

[Brief explanation of the drawing]

FIG. 1 is a general explanatory diagram showing the insertion of a sub-screen into the main screen, FIGS. 2 and 3 are block circuit diagrams showing conventional image signal processing circuits, and FIG. 4 is a diagram according to the present invention 1; An explanatory diagram illustrating the image display position displayed by the image signal processing circuit, FIG. #I5 is the first diagram of the image signal processing circuit according to the present invention.
6 and 347 are circuit diagrams showing the correlation calculation circuit of
FIG. 8 is a circuit diagram showing the correlation calculation circuit for stripe 2 of the image signal processing circuit according to the present invention, FIG. 9 is an explanatory diagram of its operation, and FIG. A circuit block diagram showing the entire image signal processing circuit, FIG. 11 is a circuit block diagram of the 11 screen timing signal generation circuit in FIG. 10, and FIG. 12 is a circuit block diagram of the vertical synchronization detection circuit in FIG. 13 is a circuit block diagram showing a field memory input line memory, FIG. 14 is a circuit block diagram showing a line memory address generation circuit, and FIG. 15 is a circuit block diagram showing a field memory input line memory.
Timing chart of the circuit in Figure 4, Figures 16 and 17
The figure is a timing chart for explaining the vertical timing of the sub screen, FIG. 18 is a timing chart for explaining the color signal multiplex timing, and FIG. 19 is a timing chart for explaining the color signal multiplex timing.
FIG. 20 is a circuit block diagram showing the luminance signal and chrominance signal field memory in the figure. Figure 22 is a detailed circuit diagram of the circuit in Figure 11, Figure 21, $
Figures 23, 24, and 25 are the rounding ties/gutyard of the explanation, Figure 26 is the first correlation calculation circuit diagram, and the second
Figure 7 is an explanatory diagram, and Figure 28 is 87 pages of image data.
, a circuit diagram for explaining a circuit that performs P/8 conversion, Figure 29 is a circuit diagram showing a circuit that generates a timing signal for Yes conversion, Figure 30 is its timing chart, and Figure 31 is a field memory address generation circuit. 32 is a tiling chart for explaining the circuit diagram.
The figure is an explanatory diagram for explaining address skipping, 83
Figure 4 is a circuit diagram showing the main screen timing generation circuit.
Figure 6 is the ninth tie chart explaining vertical synchronization playback), Figure 36 is a circuit diagram explaining the horizontal and fi direct drive signal generation circuit, Figure 37 is a timing chart for explaining it, and Figure 38. Figure 39 is a rounded timing chart explaining the vertical timing of the main screen, Figure 40 is a circuit that performs a door display effect,
FIG. 41 and FIG. 42 are diagrams for explaining the same), FIG. 943 is a circuit diagram showing a field memotive gun protrusion address generation circuit, #[alaFill, a detailed circuit diagram of FIG. 4a, and FIG. 945. Figure $46 is a tie (Y Guchiyad, 4th
Fig. 7 is a detailed circuit diagram of Fig. 38, Fig. 48 is a time chart explaining address skip when reading the field memory, Fig. 49 is an explanatory diagram of correlation calculation, and HSO diagram is a circuit diagram for performing the second correlation calculation. , FIG. 51 is a diagram showing a circuit that performs correlation calculations on color signals, FIG. 52 is a timing chart for explaining the same, FIG. 53 is a circuit diagram showing a circuit that performs data read speed conversion, and FIG. 155 is a timing chart for explaining the above equation. l 1420... Luminance signal field memory 1430...
- Field memory control circuit 1440... Field memory address generation circuit 160G... Luminance signal output buffer circuit 270G... Color signal output buffer circuit 25
20...Color signal field memory 2806...Horizontal timing generation circuit 2808...Line memory address generation circuit 2800
...Sub-screen timing generation circuit 2811...Synchronization signal width detection circuit 2812...Phase comparison circuit 2813...Phase comparison pulse generation circuit 2814...Vertical timing signal generation circuit 2817...
...Percent data reduction timing generation circuit 2818...Field memory control signal generation circuit 2821...Identity reduction tie building signal generation circuit 2900...Product signal generation circuit 3000...Main iii side timing generation circuit 3025
...Skip timing occurrence IgIwI3026...
・Skip data generation - path 3028... Buffer memory write cooking system Hill! l path 3100... Engraving of field memory address generation circuit diagram (no changes in content) Figure 3? ;・ 4 'l 7th
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c) M+Mort" No. 50 1,4 Special aperture 858-59 (i';'7 Gamma 9); (Method) I, Indication of the case Patent application 1983-158221, Title image of the invention (No. II Escaped circuit 3, Relationship with the person making the amendment case) Patent applicant (307) Tokyo Shibaura Electric Co., Ltd. 4, Agent Address: Tokyo Shibaura Electric Co., Ltd. Tokyo Office, 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo 100, Japan February 23, 1981 (shipment date) 6 pages to 136 true)
engraving. (No change in 6 valleys) (2) 4 knee attachment - 1 plaster. (No change in content) Above

Claims (1)

[Scope of Claims] A mode generation circuit that generates a mode signal for selecting a single display mode; a converter that converts a video signal into a digital signal; a converter that converts a video signal into a digital signal; an oscillator that oscillates, and a sub-screen timing No. 111 generation that is controlled by the one-screen synchronization signal and a predetermined mode signal and generates a plurality of horizontal and vertical timer signals of the sub-screen using the output of the oscillator as a reference signal. circuit;
a first tie signal that generates a plurality of tie signals in relation to a write tie signal of the field memory according to a predetermined mode in which the arithmetic 1g circuit and the I11 oscillator output and the screen timing signal are interrogated; a generation circuit; a reduction circuit that performs a data compression/h operation on the data output from the first arithmetic circuit according to the output of the first tie-signal generation circuit 1; and the first timing generation circuit whose output is the reduction circuit. A yield memory is controlled by a predetermined output and an address signal to enable writing and continuous output, and a main screen synchronization signal is derived.11 A main screen timing signal is controlled by a mode signal and generates a plurality of tie-setting signals. a second tying signal generating circuit to which the main screen tinging signal and a predetermined output of the first tying signal generating circuit are guided; a predetermined output of the first tying signal generating circuit and the t
A predetermined output of the tie writing code generation circuit of jIL2 is led to the address generation circuit of the field memory, and a signal output from the field memory is led to the mode signal and the eighth tie code number generation circuit. a second arithmetic circuit which is activated by a predetermined signal of the signal generating circuit and capable of performing reduction and enlargement calculations using at least a line memory; a buffer 7 circuit in which arithmetic circuit output data can be written and which can be removed in accordance with the main timing signal; converting the buffer output into an analog signal; In the image signal processing circuit comprised of a converter, the first tie code generation circuit uses the oscillator output as a reference clock, and uses the oscillator output as a reference clock and at least the output field memory timing signal and the write tie code. A field memory control 411g1 path that can generate a field memory read timing signal with a length more than twice the length of the signal, and one reduction timing 1! from among a plurality of small timing signals switched by a predetermined mode signal. ! The reduction timing deviation generated by selecting the signal, the output of the control circuit, the output of the control circuit, the selected signal, and the signal #1lIII.
a field memory write address generation circuit to which a field tying signal is guided and generates a field memory write address; From the timing signal related to the field memory read timing signal and the main screen timing signal, the timing signal related to the 1IIJ picture rki display is used to detect the overflow of data for one horizontal line of the sub screen from the field memory according to the mode. 1st. a field memory output timing generation circuit capable of generating at least a second detection pulse; a second detection pulse and an address generation circuit that generates a field memory read address from a predetermined output of the first timing generation circuit; A second detection pulse (therefore, a line memory address generation circuit that generates a control signal for the line memory of the second circuit). Therefore, the field memory which has a panzer memory write address generation circuit which generates a write signal to the buffer circuit described above and which is capable of continuous writing is at least controlled by the write and a* output timings of the field memory control circuit. Controlled by a signal, it is possible to write 10 cycles of predetermined data in 1 horizontal cycle of the main screen, and 2 horizontal cycles of #l1djcki written within 1 horizontal cycle of the main screen. The image signal processing J1-path is characterized in that the data has been made such that it is possible to output the data.