JPS5858629A - Bus switching system - Google Patents

Abstract

PURPOSE:To simplify switching processing, to remarkably shorten the time required for securing synchronization of a stand-by system bus, and to eliminate a halt of service, by controlling a bus concentrically by a bus controlling subsystem, and also instructing to switch the bus. CONSTITUTION:In case when a bus fault such as bus frame step-out, etc. has occurred in the course of transmitting data by use of a ''0'' system bus 100, a management subsystem (MNS) 102 switches the connection to a ''1'' system bus 101 by its own subsystem, instructs to switch a bus, to a terminal information subsystem (TIS) 103 by a logical communication link 108, and the TIS 103 switches the bus 101. Between the MNS 102 and a TIS 104, too, switching to the bus 101 is executed by a link 110. As a result, when the bus 101 of all systems is set, the MNS 102 confirms that bus frame synchronization has been secured, and after that, transmits data again to the TISs 103, 104.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus switching method, particularly a bus switching method in a distributed processing system. Processors of a plurality of subsystems mutually send and receive information via a bus, and each constituent subsystem can communicate with the entire system. In so-called distributed processing systems, in which functional processing is divided and distributed, the buses are multiplexed to provide a redundant configuration in order to improve the reliability of the system. establishment, communication management table for requests such as calls from each constituent subsystem) is shared by the T-Bus management subsystem (management subsystem), and protocol management (for example, transmission control procedures, rules regarding user zip description) management, etc.) to other subsystems (terminal informatics subsystem)
We are sharing the work.

Conventionally, in the above-mentioned distributed processing system, when synchronization occurs due to a failure in the active bus among the multiplexed buses, and the system does not recover even after a specified number of tries between the constituent subsystems, the active bus is used as a backup. Switch to the system bus. In other words, this active bus Φ failure is detected by each of the front component subsystems, and if synchronization is not established even after the specified number of tries, the process of the subsystem that detected the failure automatically switches to the four blocks. The entire system is switched to the standby bus according to a procedure in which the system switches to the standby bus and issues a bus switch instruction to other subsystems. Therefore, the switching process is complicated, and the procedure takes a long time to establish synchronization of the standby bus (it may take more than 10 seconds), resulting in service interruption. 0 The purpose of the present invention is to provide a bus switching method that eliminates the above drawbacks by centrally managing the bus in the bus management subsystem and instructing bus switching so as not to affect other subsystems. Our goal is to provide the following.

The bus switching method according to the present invention provides a distributed processing system that includes a multiplexed bus that interconnects a plurality of processors, a bus management subsystem that manages the multiplexed bus, and at least one other subsystem. The present invention is characterized in that it instructs switching of the multiplexed buses. Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a distributed processing system to which the bus switching method of the present invention is applied, and FIG. 2 shows an example of a bus frame on the bus in FIG. 1. 1 is a configuration diagram. In FIG. 1, the bus is a 0-series bus 100.
211 on the 1st bus 101. The management subsystem (hereinafter referred to as MN8) 102, the terminal information processing system (hereinafter referred to as Tl5) AIQ3 and 'I'l5B 104 are respectively connected to the connection device Mt05.
．． m connection device A106 and connection device B107? Through,
The 0 system bus 100 and the 1 system/< bus 101 are connected to form a distributed processing system. Connection device M105. A106.
B107 is MN8102. Tl5A103. T
A processor (not shown) in the 18B104 is controlled by a designated bus (0
system bus 100 or 1 system bus 101).

108, 109 and 110 shown with broken lines are between MNS102 and Tl8A103, Tl8A103 and Tl8B104 (2D question and MN8102 and Tl8B), respectively.
104, the data communication connections logically established after the completion of the connection of the physical data transmission paths between the so-called logical communication links MA, AB and MB, specifically the calling and confirmation of the partner device, both In this state, the commands and confirmations necessary for actual data transfer, such as confirming the communicable state and operation mode of the device, have been performed. For example, between MNS 102 and 'I'l8A103, connecting device M105. Q series bus 100. After the connection of the physical data transmission path via the connection device A106 is completed, the logical communication link MA
108 is established, as well as other logical communication links AB.
I09, MBIIO is also established and MNS102. Tl5
AIQ3. Required signals are transmitted and received between the Tl8Bs 104.

Next, in FIG. 2, a bus frame 200 has a fixed length, and includes a frame pattern 201 indicating a signal for frame synchronization between the transmitting and receiving subsystems, and an accept flag 20 indicating acceptance of a request flag 203, which will be described later. Tl8A103 or Tl5B10 shown in Figure 1
4, a bus configuration flag 204 indicating which of the 0-system bus 100 and 1-thread bus 101 shown in FIG. 1 should be used, and high-level data link control. Protocol frame 213 indicating the procedure (HDLC procedure)
and a padding 7 lug 212 indicating an adjustment pad for adjusting the size of the bus frame 200 to the fixed length.
It consists of The protocol frame 213 also includes a framing pattern 205 indicating a synchronization pattern for a logical communication link, a destination address 206 indicating the address of the receiving subsystem, an origin address 207 indicating the address of the transmitting subsystem, and a An address part 208 that indicates the address within the subsystem, a command bar (209) that indicates the type of received data, and an in7omeshi! that indicates the information to be transferred.
7 frame check sequence 211 for checking the validity of the data in the protocol frame 213. configured.

Next, a bus switching operation using the bus switching method of the present invention will be explained. FIG. 3 is a sequence diagram showing the bus switching procedure in FIG. 1. The figure shows that a bus failure occurs during data transfer using the 0 series bus 100 (shown in Figure 1).
The sequence for switching to the 1-system bus 101 (shown in FIG. 1) will be explained by taking as an example the transmission and reception of signals by the logical communication link MA 108 between the MNS 102 and the Tl8A 103. Bus frame (1) 301~
Each of the bus frames (4) 304 has the bus frame configuration shown in FIG. First, a bus frame (1) from MNS 102 to logical communication link MA 108 3
01 calls Tl5A103e and instructs the use of the O system node 100. When Tl5A103 receives this bus frame (1) 301, it transmits bus frame [2) 3 by logical communication link MA108.
By sending 02, a response such as a communicable status is sent and returned.

If it is assumed that a bus failure 305 occurs in the 0-system bus 100 after that, the MN8102
Tl5A103 transmits data via bus frame (t) 301, but Tl5A103 cannot receive this data and cannot send back a response to the data reception, so it is in the state of bus frame out of synchronization 306. Become. In MN8102, this bus frame synchronization is lost 306
, and learns that a failure has occurred in the 0-system bus 100. Subsequently, the MN8102 changes the connection of the bus to the pre-located thread bus 101 in its own subsystem, and instructs the Tl8A103 to execute the bus switching by transmitting a bus frame (3) 303 via the logical communication link MA10g.

In Tl5AI03, according to this instruction, the 1st bus 101
Perform bus switching 308 to - (switching operation) 0 and MN
Logical communication link MB between 8102 and Tl5BI04
Transmission and reception of signals by the IIO is also performed in the same sequence as the switching operation described above. As a result, when the 1st line bus 101 of all systems is set, the MN8102 confirms the bus frame synchronization establishment 307t and then connects the 1st line bus 101
The data is sent again to Tl8A 103 by sending bus frame (4) 104 over t-. Since the above-mentioned bus switching time is short (for example, about α2 seconds), service interruption is unlikely.

In this embodiment, a duplex bus is shown as a redundant bus configuration, but a triple or higher multiplex bus may also be used. Further, although two subsystems are shown as the terminal informatics subsystem, it may be one or more subsystems as required. Furthermore, the bus frame configuration is not limited to that shown in FIG.

In the present invention, the processors of each component subsystem perform distributed processing via a multiplex bus, but it is clear that the above-described switching system distributed processing can also be applied to a distributed processing system that performs the distributed processing over a communication network.

As is clear from the above explanation, according to the bus switching method of the present invention, the seven systems that manage the bus centrally check for bus frame synchronization of the active bus in the distributed processing system, and the backup bus of all systems Instructs to switch to
Since bus switching is completed without making other subsystems aware of the impact of the bus switching operation, the switching process is simplified compared to conventional bus switching methods, and the time required to establish synchronization of the standby bus is significantly shortened. , #1 has the great effect of virtually eliminating service interruptions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a distributed processing system to which the bus switching method of the present invention is applied, and FIG.
FIG. 3 is a block diagram showing an example of a bus frame on the bus shown in FIG. 3, and FIG. 3 is a sequence diagram showing a bus switching procedure in FIG. 100...0 series bus, 101...1 series bus, 102...management subsystem, 1
03゜104 ・・・Terminal information system, 105, 106, 107 ・・・
・Connection device, '108.109.110...Logical communication link, 200...Bus frame, 2
13. Medium...Protocol 7 Ray 4% 301...
・Bus frame <1), 302... bus frame (
2), 303... Bus frame (3), 304
・・・・・・Bus frame (4), 305・old・・bus failure, 306・・・bus frame out of synchronization, 3o
7...Bus frame synchronization established, 308...
Bus switching. 1st bad jP121! ] Ward 3 224-

Claims (1)

[Claims] In a distributed processing system comprising a multiplex bus that interconnects a plurality of processors, a bus management subsystem that manages the multiplex bus, and at least one other subsystem, the bus management subsystem issues an instruction to switch the multiplex bus. The bus switching method is characterized by: