JPS5853801B2 - Pulse duty adjustment method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse duty adjustment method used in electronic channel selection devices of television receivers.

In an electronic tuning device, there is a method of tuning by applying a so-called tuning voltage to a town variable capacitive diode to vary the local oscillation output for tuning.

Furthermore, the tuning voltage is set to a different value for each cycle,
A digital method is also being considered in which stepwise voltage changes are obtained by changing the pulse duty of a constant period to generate this voltage.

Even in such a tuning device, AFC (automatic frequency adjustment) is used to receive television signals at the correct frequency.
circuit is required.

The frequency shift detection signal of this AFC circuit, the so-called AFT
In the case of the digital method, the signal is fed back as a signal that changes the pulse duty of the constant period.

Therefore, the larger the number of steps in the stepwise change in the tuning voltage, the finer the adjustment is possible.

For this purpose, the wider the variable step of the duty of the pulse, the better, so a counter circuit of ten or more bits is used as a means for generating a clock pulse for changing the duty.

This is to smoothly generate the necessary tuning voltage width of about 30V. For example, a 12-bit counter circuit can be adjusted in 212 = 4096 steps, and each step has about 75 V.
It can be varied by mV.

However, in order to perform adjustment according to the AFT signal, the counter circuit must be capable of up-counting and down-counting, which requires a very large number of circuit elements.

Furthermore, as mentioned earlier, the tuning voltage changes stepwise with pulses, so fine adjustment requires detailed steps, and to do this, the number of bits in the counter circuit further ahead must be increased. .

For example, if fine adjustment is to be performed at 2 mV per step, 30 V/2 mV=15,000 steps are required, and the counter circuit requires 14 bits (16,384 steps).

As the number of bits in the power/counter circuit increases, the number of elements increases, and the D
- The clock frequency must be increased due to constraints from the A converter, making design extremely difficult.

Furthermore, in general, in electronic tuners using varactor diodes, the curve of tuning voltage versus tuning frequency is
As shown in Figure 0, it becomes non-linear.

Therefore, when the tuning voltage becomes high, the frequency change tends to decrease.

Therefore, the frequency change per step becomes a very small value in a range where the tuning voltage is high.

Therefore, if a certain frequency range is to be complemented by the AFT signal, the number of bits in the counter circuit must be increased.

The present invention has been made in order to address the above-mentioned circumstances, and is capable of pulse duty adjustment that allows the rate of change in output voltage per step to be arbitrarily selected so as to reduce the number of bits of the counter circuit. The purpose is to provide a method.

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 10.

That is, in FIG. 1, 11 is an input terminal to which an AFT signal is applied, and 13 is a clock pulse generation circuit.

The output terminal of the clock pulse generation circuit 13 is connected to a high-speed fine adjustment counter circuit 14 as a first counter circuit;
It is connected to a low-speed fine adjustment counter circuit 16 as a second counter circuit, a high-speed coarse adjustment counter circuit 18 as a third counter circuit, and a low-speed coarse adjustment counter circuit 22 as a fourth counter circuit.

Further, the input terminal 11 is connected to an analog-to-digital conversion circuit 12.
The output terminal of this analog-to-digital conversion circuit 12 is connected to the control terminal of the low-speed fine speed adjustment counter circuit 16.

The output terminals of the high-speed fine adjustment counter circuit 14 and the low-speed fine adjustment counter circuit 16 for outputting data are connected to a comparison circuit 15.

The match pulse output terminal of this comparison circuit 15 is connected to a latch circuit 17.

The latch circuit 17 is also connected to an output terminal for a set signal obtained by gate-acting each output of the high-speed fine adjustment counter circuit 14.

A pulse output terminal of the latch circuit 17 is connected to a subtraction circuit 25.

On the other hand, the data output terminal of the low-speed coarse adjustment counter circuit 22 is connected to a memory circuit 21 which can store, read and write output data of this circuit.

The data output terminals of the memory circuit 21 and the high-speed rough adjustment counter circuit 18 are connected to a comparison circuit 19, and the coincidence pulse output terminal of the comparison circuit 19 is connected to the latch circuit 20.

The latch circuit 20 is also connected to an output terminal of a set signal which gates each data of the high-speed rough adjustment counter circuit 18.

The pulse output terminal of the latch circuit 20 is connected to the first low-pass filter circuit 2 via the pulse amplification circuit 23.
4, and the output terminal of this first low-pass filter circuit 24 is connected to the subtraction circuit 25.

The output terminal of this subtraction circuit 25 is connected to a second low-pass filter circuit 26, and the output terminal of this filter circuit 26 is led out as a duty pulse output terminal 27 and connected to a tuner circuit.

The clock pulses for the low-speed fine adjustment counter circuit 16 and the low-speed coarse adjustment counter circuit 22 are those obtained by dividing the output of the clock pulse generation circuit 13 by the frequency division 1513A, that is, the clock corresponding to C20 in FIG. is used.

The basic configuration of the pulse duty adjustment method of the present invention is as described above, and next, a specific example of the subtraction circuit 25 is shown in FIG.

That is, 252 is an input terminal to which the output of the low-pass filter circuit 24 is applied.

This input terminal 252 is led out via a resistor 29 as an output terminal 253 to the low-pass filter circuit 26, and is also connected via a resistor 30 to the collector serving as a controlled electrode of a transistor 31.

The emitter of this transistor 31 is grounded, and the base as a control electrode is connected to the latch circuit 17 via a resistor 32.
connected to.

Next, the basic configuration and operation including the coarse adjustment counter circuit 18 and the latch circuit 20 will be explained assuming that the output of the low-speed coarse adjustment counter circuit 22 is directly input to the comparison circuit 19 via the memory circuit 21. .

That is, in the example shown in FIG. 3, the resolution is 4 bits, and the flip-flop circuits (FFO to FF3) correspond to the coarse adjustment counter circuit 18, and the flip-flop circuits (FF10 to FF13) correspond to the low-speed adjustment counter circuit 18. It corresponds to the rough adjustment counter circuit 22.

This configuration is a flip-flop circuit (FFO~
FF3) as a master counter, flip-flop circuit (
FF10 to FF13) are used as sweep counters.

And output information Q of the flip-flop circuit (FFO to FF3).

-Q3 and the flip-flop circuit (FF10 to FF13
) The comparison circuit 19 compares the output information Qt O−Qt 3 of the image information Qt O−Qt 3 and when the image information matches, the comparison circuit 19 applies a coincidence pulse COR to the input terminal R of the latch circuit 20 .

Further, the initial state of the master counter is detected by the NOR circuit 33 to obtain a set signal SS, which is applied to the input terminal S of the latch circuit 20.

Therefore, when the clock pulse CP1 applied to the clock input terminal of the flip-flop circuit FFO' (7) is compared with the signals of each part, the result is shown in FIG.

Here, the output of the NOR circuit 33 serves as a set signal for the latch circuit 20, and the output of the comparison circuit 19 serves as a reset signal.

Therefore, the latch circuit 20 is set at the 0th clock pulse CP, and the latch circuit 20 is set at the 0th clock pulse CP, and the latch circuit 20 is set at the 9th pulse (Qo, Ql, Q2, Q3'').
'1'','O'','0'',''1''-Qto + Ql
lQ1□, Ql3).

(Has/L/ width t 1 in the illustrated example) Furthermore, if one more clock pulse CP2 is added to this, the latch circuit 20 receives the 0th (
Qo, Qt.

Q2. Q3=%% 0 /l, ゝ0//, ″077%
It will be sent at % 0 //) and reset at the 10th point from force).

(Pulse width t2 in the illustrated example) In this way, the latch circuit 2
The output RQ of 0 has a pulse width t1. As shown by t2, it can be freely varied by changing the output state of the sweep counter.

Furthermore, when using the lock pulse generation circuit in common, the clock pulse CP2 is added to the minus number of the clock pulses CP.
A branching device or the like is used to synchronize the signals.

The principle of digital-to-analog conversion is based on the following principle.

In other words, if we Fourier transform a square wave, we get However, ω.

=2π/TE; wave height value becomes.

Therefore, the square wave is passed through a suitable low-pass filter LPF1
) By removing the second term in 0 of the equation, the following DC voltage can be obtained.

As shown in equation (2), with T and E constant, t
If vT is varied from 0 to T, vT can be continuously varied, and the method of varying t, that is, the pulse width, is the example shown in FIG. 2 mentioned above.

The pulse duty adjustment method of the present invention is performed as described above, and the fine adjustment pulse generating means such as the comparison circuit 15, the counter circuit 14 for high speed fine adjustment, the counter circuit 16 for low speed fine adjustment, and the latch circuit 17 are also shown in FIG. It operates in the same way as the coarse adjustment pulse generating means described in .

In addition, if the AFT signal as a feedback signal is at a predetermined level, the analog-to-digital conversion circuit 12 etc. controls the gate circuit so that no clock pulse is introduced to the low-speed fine adjustment counter circuit 16, and if there is a synchronization shift, A Schmitt trigger circuit or the like is used to generate a control pulse, and the gate circuit is set so that the clock pulse can be applied to the counter circuit 16 for low-speed fine adjustment, and is used as a pulse adjustment means for fine adjustment.

Further, the subtraction circuit 25 is used as weight means for adding a fine adjustment pulse to the rough adjustment DC voltage.

Next, to explain the operation of each part in detail, the low-speed coarse adjustment counter circuit 22 can create an output data corresponding to a desired channel and write it into the memory circuit 21, which is stored on the user's side. It is adjusted in

In other words, when a certain channel is selected, the low-speed coarse adjustment counter circuit 22 and the high-speed coarse adjustment counter circuit 18 operate as explained in FIGS. 3 and 4, and the coarse adjustment The pulse is generated by a pulse amplification circuit 23, a low-pass filter circuit 24, a subtraction circuit 25, and a low-pass filter circuit 2.
6 and is applied to the tuner as a tuning voltage.

Then, the clock pulse CP2 is applied to the low-speed coarse adjustment counter circuit 22 until the tuning voltage reaches an appropriate value.

In this case, clock pulse CP2 is clock pulse CP
A frequency obtained by dividing 1 into several fractions of - is used.

When the receiving section is tuned, the input gate of the low-speed rough adjustment counter circuit 22 is closed at a predetermined level of the AFT signal.

If the output data of the counter circuit 22 at this time is stored in the memory circuit 21, the next channel can be received by simply reading the data.

Therefore, the memory circuit 21 is provided with storage sections corresponding to a plurality of channels.

Furthermore, in addition to the nonvolatile storage section corresponding to the channel, a temporary storage section is also provided.

During the above coarse adjustment, the low speed fine adjustment counter circuit 1
6 is synchronized with the set signal from the low-speed coarse adjustment counter circuit 22, and the fine adjustment pulse P2 obtained from the latch circuit 17 is the coarse adjustment pulse PI as shown in FIG. The duty is the same as in (a).

Since the coarse adjustment pulse P1 is converted into a direct current by the low-pass filter circuit 24, the fine adjustment pulse P2 is subtracted from it.

Then, it is further converted into a direct current by a low-pass filter circuit 26.

Now, if the synchronization is deviated for some reason, the level of the AFT signal will change.

As a result, the analog-to-digital conversion circuit 12 generates a predetermined control pulse, and the low-speed fine adjustment counter circuit 1
The input gate No. 6 is opened and set so that the clock pulse CP2 is applied.

Further, when the AFT signal is at a predetermined level, that is, the voltage at point A in the tuner calibration characteristics shown in FIG. 16 input gates are closed.

When a synchronization error occurs, the clock pulse CP2 is applied to the low-speed fine adjustment counter circuit 16, so that the fine adjustment pulse P2 whose duty has been adjusted is latched as shown in FIG. obtained from circuit 17.

That is, in the range shown by the dotted line in FIG. 6, the pulse P2
The pulse width of is adjusted.

On the other hand, the coarse adjustment pulse P1 is applied to the low-pass filter circuit 2.
4, the weight of the pulse P2, in this case, is subtracted from the DC voltage.

Therefore, if the pulse width of pulse P2 changes as shown by the broken point in FIG. 6, the subtraction circuit 2 changes as shown in FIG.
The output of No. 5 will also change as shown by the broken line.

Therefore, the duty of the pulse input to the low-pass filter circuit 26 is adjusted, and the tuning voltage is also varied.

Then, when the AFT signal reaches the voltage level at point A in FIG. 9, the analog-to-digital conversion circuit 12 closes the input gate of the low-speed fine adjustment counter circuit 16 using an output control signal using a Schmitt trigger circuit or the like.

The present invention is characterized by the operation during the above-mentioned fine adjustment, and the voltage drop due to the step change of the fine adjustment pulse can be changed in proportion to the output voltage.

That is, the circuit shown in FIG. 2 is used as the subtraction circuit 25, and the fine adjustment pulse causes the input terminal 25 to
The transistor 31 is turned on and off by the fine adjustment pulse applied to the transistor 1.

During the period when the transistor 31 is off, the input voltage applied to the input terminal 252 appears as it is at the output terminal 253.
When the transistor 31 is turned on, this transistor 31
However, the current flowing through is constant current 1. R2: Value of resistor 29.30 ■A: Becomes the output voltage that has passed through the first LPF 24.

Therefore, the current I flowing when the transistor 31 is on (during the duty of the fine adjustment pulse) is proportional to the output voltage A, and as a result, the voltage drops on the terminal chamber side of the resistor 30 and passes through the low-pass filter circuit 26. The change in the resulting DC tuning voltage due to one step of fine adjustment pulse also changes the output voltage.
It will change in proportion to A.

By selecting the value of the resistor 29,30, it is possible to select the rate at which the tuning voltage changes with respect to one step of the fine adjustment pulse.

As a result, as can be seen from the characteristic of tuning voltage versus tuning frequency shown in FIG. 10, in a range where the tuning voltage is high, if the rate of change of the tuning voltage is increased, the steps of the fine adjustment pulse can be reduced.

In other words, the number of bits of the counter circuit for generating fine adjustment pulses can be reduced, and the cycle frequency can also be lowered.

To select the rate at which the tuning voltage changes with respect to one step of the fine adjustment pulse as described above, the resistor 29 of the subtraction circuit 25
．． A value of 30 may be selected.

In the above embodiment, the subtraction circuit 25 is used as the main part of the present invention, but it can also be implemented with an addition circuit.

A specific example of this adder circuit is shown in FIG.

That is, the input terminal 252 is connected to the low-pass filter circuit 2.
DC voltage (for coarse adjustment) from input terminal 2 is applied, and
A fine adjustment pulse from the latch circuit 17 is applied to 51.

Input terminal 251 is connected to the base of transistor 31', and the emitter of transistor 31' is connected to power supply terminal 254.

The collector of the transistor 31' is connected to a resistor 30.
The input terminal 25° is also connected to the output terminal 253 via a resistor 29'.

Then, a coarse adjustment pulse P1 as shown in FIG. It is led out to the output terminal 253 without receiving any current.

Next, when the rough adjustment pulse P2 as shown in FIG. is derived and converted into a direct current by the low-pass filter circuit 26.

In this adder circuit as well, the current flowing through the transistor 31' is proportional to the output voltage, and the rate of change of the voltage is
'.

30'.

The broken line shown in FIG. 8 also indicates the pulse P as in the explanation of FIG.
It means the pulse width change situation when the pulse width of No. 2 is changed.

According to the pulse duty adjustment method of the present invention described above,
First, in order to obtain a change in the tuning voltage by changing the pulse duty, a coarse adjustment pulse generation means and a fine adjustment pulse generation means are provided, and a DC voltage (for coarse adjustment) and a fine adjustment pulse are obtained from both. It is designed to synthesize the following.

Therefore, there is no need for fine step changes in the coarse adjustment pulse, the number of bits of the counter circuit for generating this pulse is small, and there is no need to increase the clock pulse frequency, making it easy to integrate the circuit.

Further, the duty change of the fine adjustment pulse can be used in common with the coarse adjustment pulse for each channel, which can greatly contribute to reducing the number of bits of the counter circuit.

Furthermore, the method of using the addition or subtraction circuit, which is a feature of the present invention, is extremely advantageous in reducing the number of bits, that is, the number of elements, of the counter circuit, comparison circuit, etc. in the fine adjustment pulse generating means.

In other words, as is clear from the characteristic diagram of tuning frequency vs. tuning voltage in Figure 10, if the rate of change of tuning voltage is constant, in a high frequency range there will be more tuning voltage than in a low frequency range. A step change is required.

However, according to the present invention, as explained in FIGS. 2 and 7, it is possible to vary the rate of change in the output voltage for one step in the addition or subtraction circuit, so that step changes in the tuning voltage can be achieved even in a high frequency range. Less is enough.

Therefore, the number of bits of the counter circuit, comparison circuit, etc. in the fine adjustment pulse generation means can be further reduced.

Generally, in a tuner circuit that uses a percussion capacitance diode and applies a tuning voltage to it to vary the tuning capacitance and select the reception frequency, the characteristic of tuning voltage versus tuning frequency is nonlinear as shown in Figure 10. It is known that when the tuning voltage is high, the rate of change in the tuning frequency with respect to the change in the tuning voltage is small.

Therefore, the present invention is configured so that the rate of change in one step of the fine adjustment pulse and the tuning voltage can be made nonlinear, and as a result, the one step change in the fine adjustment pulse and the change in the tuning frequency are linear. It was designed so that

Furthermore, in the present invention, the coarse adjustment pulse generating means includes:
Even if a potentiometer is used to obtain a DC voltage corresponding to each channel and add it to the subtraction or addition circuit, the gist is the same as in the above embodiment.

Note that the low-speed fine adjustment counter circuit 16 uses a clock pulse C.
For example, if P2 is set to count up only in one direction, for example, and to count cycles in an appropriate frequency range (fine adjustment range of tuning voltage) around the tuning point of the calibration curve, this counter circuit 16
It is not necessary to provide an up/down counter function to the device, and the cost can be reduced.

As described above, the present invention can provide a pulse duty adjustment method in which the rate of change in output voltage per one step change in pulse width can be arbitrarily selected and the number of bits of a counter circuit can be reduced.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the pulse duty adjustment method of the present invention, FIG. 2 is a circuit diagram showing an example of a subtraction circuit which is the main part of the present invention, and FIG. FIG. 4 is an explanatory diagram of the basic configuration of the coarse adjustment pulse generating means, and FIG. 4 is an operation waveform diagram shown to explain the operation of the circuit in FIG. 3. FIGS. 5 a and b
1 Figure 6a. b + c are operation waveform diagrams shown to explain the operation of the main part of the present invention shown in Fig. 2, Fig. 7 is a circuit diagram showing another embodiment of the main part of the present invention, and Fig. 8 a . b and c are operation waveform diagrams shown to explain the operation of the circuit in Fig. 7, Fig. 9 is a diagram showing the calibration characteristics of the tuner section of a television receiver, and Fig. 10 is a diagram showing the calibration characteristics of the tuner section of the same. FIG. 3 is a characteristic diagram of tuning frequency versus tuning voltage. 12...Analog-digital conversion circuit, 13...
... Clock pulse conversion circuit, 14 ... Counter circuit for high-speed fine adjustment, 15.19 ... Comparison circuit, 16 ... Counter circuit for low-speed fine adjustment, 1
7, 20...Latch circuit, 18...Counter circuit for high-speed coarse adjustment, 22...Counter circuit for low-speed coarse adjustment, 23...Pulse amplifier circuit ,2
4.26...Low pass filter circuit, 25...
...Subtraction circuit.

Claims (1)

[Claims] 1. A tuner circuit including a variable capacitance diode as a tuning element, converting a pulse signal into a digital/analog converter to obtain a DC voltage, and changing the duty of the pulse signal to vary the DC voltage. , means for applying the DC voltage to the town capacitance diode to achieve desired tuning; and means for generating an AFT signal in accordance with a shift in the tuning frequency of the tuner circuit. The method includes a coarse adjustment pulse generation means, a means for converting the output of the coarse adjustment pulse generation means into DC to obtain a rough adjustment DC voltage, and a clock pulse that is different from each other by applying a clock pulse. Compare each output data of a first counter circuit and a second counter circuit that obtain output data in a period, and latch the matching pulse and a signal gated with the output data of the first counter circuit. fine adjustment pulse generation means for obtaining fine adjustment pulses in addition to the circuit; fine adjustment pulse adjustment means for controlling the clock pulse input gate of the second counter circuit using the AFT signal; and an input terminal. has an output terminal, the rough adjustment DC voltage is applied to the input terminal, a controlled electrode of a transistor is connected between the input terminal and the output terminal, and conduction of the transistor is controlled by the fine adjustment pulse. 1. A pulse duty adjustment method, comprising means for obtaining an output that is a combination of the rough adjustment DC voltage and the fine adjustment pulse from the output terminal.