JPS5853217A - Digital filter circuit - Google Patents

Abstract

PURPOSE:To execute a filter operation at a high speed, by converting a counter which serves as an address designating means of an RAM into an (n+1)-notation counter which counts the value that is larger than the prescribed number (n) of delaying stages just by 1. CONSTITUTION:An (n+1)-notation counter 7 serves as an address designating means for a register 5 and an RAM1 and counts the value larger than the prescribed number (n) of delaying stages just by 1. The contents of the counter 7 are cleared to zero. The contents which are designated by the counters 6 and 7 of a coefficient memory 2 containing n words and storing the coefficient of a digital filter and the RAM1 storing delay data are read out and multiplied by a multiplier 3. The result of this multiplication is added with the contents of the register 5 through an adder 4. The result of the addition is stored in the register 5. Then the count value is added by 1 for each of the counters 6 and 7. This operation is repeated by n times. Then an input signal 8 is stored in the address designated by the register 6 of the RAM1, and the count value of the counter 6 is increased by 1.

Description

[Detailed description of the invention] The present invention relates to a digital filter.

The basic configuration of a digital filter is a multiplier, an adder, a coefficient memory, and a unit time delay element.As a method of converting the unit time delay element into node hardware, a shift register may be used, but a RAM (Random Access Memory ) is a common method. For example, an n-stage acyclic digital filter as shown in FIG. 1 is implemented in hardware as shown in FIG.

In FIG. 2, 1 is a RAM consisting of n words representing a unit time delay element, 2 is a coefficient memory consisting of n words, 3 is a multiplier, 4 is an adder, and 5 is a register. are respectively accessed by counters 6.7.

In this configuration, in order to obtain an output signal for one input signal, it is necessary to perform the following operations. That is, (1) the values of register 5 and counter 6.7 are cleared to zero.

(2) Read the contents pointed to by counters 6 and 7 in RAM 1 and coefficient memory 2, multiply them by 3, add the result to the contents of register 5 by 4, and store the result in register 5. Store. Counters 6 and 7 are each incremented by 1.

(3) Repeat (2) above n times.

(4) Transfer the contents of address (i-1) of RAM 1 to address i. This operation is 1=n-1, n-2, -,
2. Do this for 1.

(5) Store input signal 8 in address 0 of RAM1.

That's all. The output signal value can be obtained in the register 5 through the series of operations described above. For example, (1) to (5)
) operation using a constant instruction cycle Xn5ec
Consider the processing time when trying to implement it with a microprocessor running on . Assuming that the processes (1) and (2) above and the operation of transferring the contents of address (i-1) of RAM 1 to address i can be realized in one instruction cycle, then (1) to (5) ) The time required for the operation is (1+n+n)X n5ec.

This time is the time required to obtain one output signal, and must be within the time required for the purpose. For example, when performing real-time processing on signals in the telephone voice band, the above-mentioned processes (1) to (5) must be completed within a time of 125 μsec.

An object of the present invention is to provide a digital filter that eliminates the need for the memory transfer process (4) and can execute the processes (1) to (5) in about half the time compared to the conventional example.

According to the invention, n
a coefficient storage means consisting of words, a LAM (for storing delay data), and an addressing means for the RAM (n+) for counting a value that is one more than a predetermined number of delay stages n.
A digital filter circuit characterized in that it has a linear counter is obtained.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of key points for realizing the n-tap acyclic filter shown in FIG. become.

The difference from the conventional technology in Fig. 2 is that 1 RAM is (n+1
) words, and the counter of 6 is in base (n+1). In this embodiment of the invention, the operations required to obtain one output signal are those of the prior art (1), (2), (3), (4).

In correspondence with (5), (1') the contents of the register 5 and counter 7 are cleared to zero. The contents of counter 6 are not cleared.

(2) Step 1 is also AM, read the contents of the address pointed to by counter 6゜7 in coefficient memory 2, and multiply by 3,
The result and the contents of register 5 are added by 4, and the result is stored in register 5.

Counters 6 and 7 are each incremented by 1.

(Three of the above (return the two operations n times υ.

(4 (unnecessary) (59) Store the input signal at the address pointed to by counter 6 of RAM Ml, and increment counter 6 by 1.

becomes.

The operations that differ from the conventional technology are (1) that the contents of the counter 6 are not cleared, (3) that data transfer within RAM 1 is unnecessary, and (5) that the address of AM1 where the input signal is stored is different. That's true. That is, data transfer processing within the RAMI, which was necessary in the prior art, is completely unnecessary. This is because the counter 6 that points to the address of R, AMI is in (J1+1) base.
At the first time, the data string in RAM, l, which is multiplied corresponding to the filter coefficients (aQ, al, a2.a3...jan-1), is (d(1+dl+d2+d3+"'+dn-1) ) was (dn#dO#dlPd21"'l"!1-2) at the third time (dn-11dnldO, all"'1dn-3), and the input signal at the first time is shifted by one. To d.
This is because the input signals at the second time are respectively stored in dn-1, so the same effect as if data were transferred appears. Therefore, there is no need for actual data transfer processing. As a result, compared to the prior art, the RAM 1 is increased by one word and the counter 6 is set to (n+1) base, which makes it possible to execute filter calculations at high speed with a slight increase in the amount of hardware.

In the above embodiment, an acyclic filter was shown, but it is clear that a cyclic filter can be easily achieved by extending the same configuration.

Further, it is clear that the counters 6 and 7 can be configured not only by amplifier counters but also by down counters and polynomial alkaline ranks.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an acyclic filter. Figure 2 shows
FIG. 1 is a block diagram of main parts when the filter of FIG. 1 is converted into software. 1... To H・A 4.2... Coefficient memory, 3... Multiplier, 4... Adder, 5...
...Register, 6,7...Counter, 8
...Input line, 9...Output line.

Claims (1)

[Claims] coefficient storage means consisting of n words for storing the coefficients of the digital filter; random access memory for storing delay data; and addressing means for the memory, wherein the predetermined number of delay stages n is equal to one more. count n+
1. A digital filter circuit comprising a 1-digit counter.