JPS5848130A - Bus priority controller - Google Patents

Abstract

PURPOSE:To shorten a bus priority decision time by dividing modules connected to a bus into plural blocks, and connecting modules in each block in series and those blocks in parallel. CONSTITUTION:When a signal REQ1 from a module 3a and a signal REQ3 from a block 3j are inputted as a bus request to a priority deciding circuit 3m, a signal ACK3 which corresponds to the signal REQ3 with higher priority is outputted to the terminal ACK of a module 3d. When modules 3e and 3f generate bus requests, the signal inputted to the terminal ACK of the module 3d is outputted, as it is, from the terminal OUT and inputted to the terminal ACK of the module 3e. Since the signal logical level at the terminal REQ of the module 3e is 1, the module 3e is connected to the bus and the signal at the terminal OUT of the module 3e has logic 0, inhibiting access from the module 3f to the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a path priority control device for preventing contention between modules when a plurality of modules use a common bus.

Figure 1 is a block diagram showing an example of a conventional device.
a ) e (1b) e (lc) * (td
) are each modules, and these modules use a common bus (not shown) and their priority is (la
)→(tb)→(1c)→(ld). Modules (la) to (ld) each have an input terminal IN and an output terminal OUT, and the terminals IN of each module (except for the terminal IN of module (1m)) are as follows.
It is connected to the terminal OUT of the module one level higher in priority (this connection is called a daisy chain type or serial type connection), and a status signal indicating whether or not a path request is being made is transmitted through this connection line. For convenience of explanation below, the signal indicating that a path request is in progress is logic "1".
Toshi, the signal indicating that a path request is not in progress is a logic "
0". For example, the terminal OUT of the module (lb)
If the signal logic from is rOJ, module (la),
Both (lb) indicate that a path request is not in progress, so the module (IC) is allowed to make a path request, and if the module (ie) makes a bus request, the logic rlJ signal is sent from the terminal OUT of (le). Output and prohibit module (ld) bus requests.

FIG. 2 is a block diagram showing another example of the conventional device.
2m), (2b), (2e), and (2d) are modules, respectively, and (2e) is a priority determination circuit. The modules (2a) to (2d) have a terminal η for outputting a signal indicating that a path request is in progress, and a terminal ACK for inputting a signal indicating whether a bus request is permitted. The module making the bus request sets the signal logic of the terminal η of the module to, for example, rlJ. This signal is input to the priority determining circuit (2e), and in the priority determining circuit (2e), the REQ of each module is
Of all the signals from the terminal, only the ACK signal corresponding to one signal among all the signals that are logic rlJ is logic r
IJ is input to the ACK terminal of the module.

The signal of the seven terminals and the signal of the ACK terminal are both logic r I
The JK module can access the path. The connection shown in FIG. 2 is called a parallel connection.

Since the conventional path priority control device is as described above, as the number of modules connected to a path increases, the delay time when information from the highest priority module is transmitted to the lowest priority module increases in the serial method. There is a limit to the total number of modules that can be connected serially. In addition, when the number of modules increases in the parallel system, the priority determination circuit becomes complicated, resulting in a disadvantage that the time required for determination increases.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above.The modules connected to the path are classified into a plurality of blocks, and the modules within each block are connected in a serial manner. It is an object of the present invention to provide a path priority control device that shortens path priority determination time when there are many modules by connecting blocks in parallel.

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 23 is a block diagram showing an embodiment of the present invention, in which (3m), (3b), (3c), (3d), (3e),
(3f)s (3g) are modules, (3h),
(3i) and (3j) are blocks, respectively, and the block (
3h) is composed of one module (3a), block (31) is composed of two modules (ab) and (ac), and block (3j) is composed of four modules (3
d), (3e), (3f), and (3g).

(ak), (aj) Id respectively or gate, (3m
) is a priority determination circuit.

In addition, the hard terminal provided in each module in Fig. 3,
The ACK terminal corresponds to the terminal with the same name in FIG. ) The output terminals ou'r provided in each module correspond to the terminals with the same names in FIG. 1. In a block having a plurality of modules, the outputs of all REQ terminals in the module are logically summed by an OR gate and input to a priority determining circuit (3m).

The priority determining circuit (3m) receives the path request signal for each block, determines the priority order according to a predetermined rule, and sends the signal ACK e to the block to be permitted. Within each block, the modules are connected in a serial manner according to the priority order of the modules, similar to the diagram F121. For example, the module (
The signal REQ 1 from the RE4 terminal of 3a) and the block (
The signal REQ 3 from the OR gate (3t) of 3j) is both input to the priority determining circuit (3m) as logic "1" (bus request in progress), and the priority determining circuit (3m) outputs the signal ACK corresponding to the signal REQ 3.
Consider the case where the signal ACK3 is input to the terminal ACK of the module (3d). block(
In 3j), it is assumed that both modules (3e) and (3f) are making bus requests with the signal logic on the terminal REQ set to rlJ.

In the module (3d), the signal logic on the terminal REQ is "0".
”, and the logic “L” signal input to the terminal ACK is output as is from the terminal OUT. The logic "l" signal output from the terminal OUT of the module (3d) enters the terminal ACK of the module (3e), and since the signal logic of the terminal REQ of the module (3.) is "l", the logic "l" signal is output from the module (3d).
e) is connected to the bus, and the signal at the terminal OUT of the module (3e) becomes logic "0", and the module (3f)
access to buses will be prohibited. Although a specific example has been described above, it is clear that in general the priority order between blocks is determined by the priority determination circuit (3m) and determined by each module within the block.

As described above, according to the present invention, when there are many modules requiring bus priority control, priority determination time can be shortened with a simple circuit, and highly efficient control can be performed with an inexpensive device. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional device, FIG. 2 is a block diagram showing another example of the conventional device, and FIG. 3 is a block diagram showing an embodiment of the present invention. (3a), (3b), (3c), (3d), (3e),
(3f), (3g) =-= module, (a
h), (at), (3j), song projiku, (3
k), (az)-...or gate, (3m), respectively
...Priority determination circuit. Agent Shin Kuzuno −

Claims (1)

[Claims] A plurality of modules that use a common bus are divided into a plurality of blocks, each block is assigned an electronic number or a plurality of modules, and each block is connected to all modules belonging to the block. Each block request signal output circuit outputs the logical sum of the request signals of the block request signal output circuit, and the output signal of each block request signal output circuit is input, and the blocks in the blocks that simultaneously send out block request signals according to a predetermined priority order are input. A priority determining circuit that selects one block and outputs a response signal only to the selected block; and a priority determining circuit that is provided in each of the blocks and outputs a response signal to the highest priority module according to the priority order of each module. Input the response signal to the other module.
Input the response signal from the module that is higher by l rank,
means for transmitting a response signal to a module lower in rank by l rank only when the response signal is input to each module except for the module in the lowest rank and the module is not outputting a 1j work signal. Bus priority control device.