JPS5846442A - Programmable controller - Google Patents

Abstract

PURPOSE:To shorten the execution cycle of a user program by inputting the output signal of a jump state flip-flop, reset when a jump instruction detection signal is outputted from a decoder, to a microprocessor as part of a user instruction, and interpreting and executing it. CONSTITUTION:A decoder 10 receives a timing signal from a CPU2 to perform decoding operation at prescribed timing. On the basis of the output of the accumulator ACC of the CPU2, a jump instruction is read out of a user program memory 1. At this time, whether the jump instruction meets execution requirements or not is stored in a jump state flip-flop 11 automatically without the intervention of the CPU2. Then, the CPU2 fetches the output Q of the flip-flop 11 through a gate 7 together with an instruction code from an instruction register 6. Then, only when the output Q is in a prescribed logical state, a normal instruction processing routine is executed. When the output Q is in the other state, jump processing is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interpreter-based program using a microphone "1 program 1" program, and in particular, to speed up digital processing. ti Naeru J, Concerning the technology of making sea urchins.

The conventional 6-type interpreter's 1-1 grammar pull, 21, and 1-0-ra are constructed as shown in FIG. The operation of sequentially reading, decoding and executing each instruction of the sequence control program stored in the J-gram memory 1 is performed by an interpreter method at J: -1 in the microb UJt (CP LJ). In other words, CPU2 is ROM
By executing the system program program (interpreter program) stored in the system program program 3, the program program that addresses the user program memory 1 is controlled while using the RAM 4 as a temporary storage area for variable data for control. , thereby reading instructions one by one from the user program memory 1 to the instruction register 6, and instruction 21 of the causer instructions read to the instruction register 6.
- Only the code is taken into -rcPU2 via Goo 1 to 7,
Decipher this. Further, the input/output address of the user instruction read into the instruction register 6 is applied to the input/output memory 8 for addressing. The input/output memory 8 is
An external output Bara-Noah memory in which an external human power is applied to the input/output circuit 9 and an output is output from the input/output horn circuit 9,
Each time the user program is executed once, the latest external input status is imported from the input/output circuit 9 to the input/output memory 8, and the output data in the input/output memo 8 updated by the execution of the 771-day graph is A so-called input/output update operation is performed in which the data is transferred to the input/output circuit 9 and used as an external output.

The CPU 2 decodes the instruction code taken in through the input/output memory 8 and performs logic 1! based on the input/output data read from the input/output memory 8. f! When performing an operation, the well-known program execution operation of loading the conclusion of the operation into the input/output memory 8 is carried out.

This creates a sequence control state defined by the user program in the relationship between the external input signal and the external output signal.

Next, this kind of conventional bottle ``1 grand pull'']-mouth-
The jump processing will be explained in detail. Figure 2 is an example of a part that is represented in the form of a ladder diagram and includes a user "program change" command. In this example, the jump command (JMP) and Jump end command LJ
If the timer instruction (TIM) and counter instruction (CNT) are interposed between the timer instruction (ME) and the input/output data S1 that has not yet arrived after the execution of the jump instruction is “0”, the timer The counter instruction is ignored (results in no operation), and when the input/output data S1 is input to the li 111, the timer instruction and counter instruction are executed normally. Conventionally, in order to execute this jump instruction (1), the system program executed by the CPU 2 was configured as shown in FIG. The instruction code is read and stored in the index register in the CPU 2. In the next step 101, the processing routine table of R0M3 is retrieved and read into the index register Iυ
Read the start address of the processing routine corresponding to the instruction code, and store this address in the index register. In the next step 102, the program jumps to the address stored in the index register and executes the processing routine. Step 103 is a processing routine for a jump instruction. First, the logic state of the accumulator in the CPU 2, which is the execution condition for the jump instruction (in the example of FIG. 2), is the input/output data S1. If the condition (same as the logical state of
1="O'"), the jump state flag JC set in the RAM 71 is set in step 105, and the program counter 5 is incremented in the next step 106, and the process returns to the first slurry block 100. Also, if the jump condition f'1 is not established in step 104, the jump condition flag JC is reset in step 115, and step 1 is reset.
Proceed to 06. Step 107 is a jump end instruction processing routine. This instruction processing starts with 5--1-1 jump status flag JC in step 108;
In the next step 109, the program counter 5 is incremented and the process returns to the first step 100. Processing loops for other various sequence instructions are shown as step 110.

When processing a sequence command, the jump condition flag JC is read in the first step 111, and in the next step 111 it is determined whether the flag is set or Z1-1. If it is set, the step is executed. At step 113, the program counter 5 is incremented and the process returns to the first step 100. In other words, if a jump is in progress, the process for that instruction is not performed and the process proceeds to the next instruction. Only when it is detected in step 112 that a jump is not in progress, each instruction is processed in step 114 (including updating the program counter 5 after execution is completed).
. Then, the process returns to the first step 100.

As mentioned above, in conventional block diagrams, jump instructions and jump end instructions are also analyzed by the CPU2. When processing, the process of first checking the jump status flag (steps 111 and 112 above) is performed when all instructions are analyzed, regardless of whether the error is an instruction related to a dithump instruction or not. Therefore, the analysis execution time of the tj instruction becomes unnecessarily large, and this is a disadvantageous factor in shortening the execution time of the Kneezab 1-cogram. .

This invention was made in view of the above-mentioned conventional problems, and the first purpose is to provide an implementation that minimizes the time required to process jump instructions, thereby shortening the execution cycle of the user. An object of the present invention is to provide a 91996-style P[1 Grand Pull Controller.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 4 is a block diagram showing an embodiment of the programmable controller according to the present invention. Parts common to or corresponding to those of the conventional controller shown in FIG. J is omitted, and only the 41 new parts according to the present invention -C are clear.

In the program according to the present invention, the instruction =+- among the user instructions read from the kneeliff program memory 1 to the instruction register 6 is input.
When the instruction code is a jump instruction or a jump end instruction, the decoder 10 detects this, and the jump instruction detection signal JMP is output from the decoder 10.
A flop that is set in the first state is set or reset according to the output logic state of the AGI combulator ACC of the CPU 2, and is reset when the jump command detection signal JMF is output from the decoder 10. 11 is provided, and the output signal @Q of this jump state Noritsubu flop 11 is used as part of the command
The decoder 10 receives a timing signal from the CPU 2 and performs the decoding operation at a predetermined timing. Do the following.

In this way, jump instructions and jump end instructions are not decoded by the CPU 2, but by the decoder 1.
0, and when a jump instruction is read from the user program memory 1 based on the output of the Agicombulator ACC of the CPU 2, the success or failure of the execution condition of the jump instruction is automatically determined by the jump state flip-flop 11 without going through the CPU 2. is memorized. And C.P.
i in U2, instruction from instruction register 6]--The output Q of the digital flip-flop 11 is taken in through the gate 7, and the normal instruction processing routine is executed only when the output Q is in a predetermined logic state. is executed, and when the output Q is in the other state, the Ia jump process is performed. FIG. 5 shows an outline of the system 11 program executed by CP1'2 in the present invention. Steps 100, 101, and 102 shown in FIG. 5 are exactly the same as the conventional processing area 9-3 of FIG. In other words, the instruction code imported via goo i~7 (di-thump state flip 70 knob 11
(including output Q), draw a processing routine table based on 14,
The start address of each corresponding processing routine is loaded into the index register, and the routine A is executed. In this invention, ]22 processing routine table is
It is divided into two systems depending on the logic state of the output Q of the jump state flip-flop 11. That is, instruction register 6
Even if the instruction 21-code read from is, for example, an A N l) instruction, the above output Q added to it]! l! Processing routines are divided depending on the state. In FIG. 5, the step 200 side is a jump state flip-flop 1" knob 11.
This is the processing routine for the M case when the output corner Q is 1'' (during a jump). In this case, the program counter 5 is simply updated in step 201 and the process returns to the first step 100. The step 202 side is a jump state Noritsubu flop. This is a processing routine when the output Q of step 11 is '0' (not present during the jump). ),
Return to the first step 100.

As explained in detail above, in the interpreter-based program control system according to the present invention, [1] it is possible to detect when the instruction read from the user programmable unit is a jump instruction or a jump end instruction. When the jump instruction detection signal is output from the decoder, it does not indicate the success or failure of the execution condition of the jump instruction (a), and the output of the Aki combulator of the microprocessor is and a jump state flip 70 that is activated as long as the detomp end command detection signal is output from the reader, and the output signal of the jump state flip 1 is used as a part of the yuri command. As above, I decided to import the above mll microprocessor 4 and execute the decoding.Since I configured it to execute jump instructions, there is no need to analyze jump instructions and jump end instructions on the microprocessor side. In addition, especially during the processing routine of other sequence commands, the process of always checking and overriding the di-thump status flag as in the past has become cumbersome. The execution cycle of the knee 1f program can be shortened.

[Brief explanation of the drawing]

Figure 1 shows the conventional interpreter method.
A block diagram of the controller; FIG. 2 is a diagram showing an example of a user program including jump instructions and jump end instructions shown in a ladder diagram format; FIG. 3 is a block diagram of the programmable controller shown in FIG. Figure 4 is a block diagram of the programmable programmable engine 1~roller according to the present invention; [Flowchart 1 of the system program executed by the CPU in the 1-grammaple controller 1-
It is. 1... Knee-1 Programming 2.
・・・・・・・・・CPU (Microprocessor) 5
・・・・・・・・・Program counter 6・・・・・・
...Instruction register 7...Goo 1-10...Decoder 11...Jump state Noritsubu Norotubu Patent applicant Tateishi Electric Co., Ltd. = 13-

Claims (1)

[Claims] (1) A program that sequentially reads each instruction of the sequence control program stored in the knee 1f program memory and decodes and executes it using an interpreter method using a microprocessor.
In the grammar pull controller, a decoder detects when an instruction read from the user program memory is a jump instruction or a jump end instruction;
When a jump instruction detection signal is output from this decoder, it does not indicate the success or failure of the execution condition f-1 of the jump instruction, and is set or reset according to the output logic state of the accumulator of the microprocessor. , and a jump state flip-flop that is reset when a jump end instruction detection signal is output from the decoder, and the output signal of the jump state control flop is input to the microprocessor as part of a user instruction. The programmable control system is characterized in that it is configured to perform jump processing by decoding and executing the program.
1-ra.