JPS584365B2 - Reset control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to data processing systems having input/output system reset capabilities.

This reset is used to reset the I/O channels and attached peripherals.

Resetting a peripheral terminates the reservation and partnership between the peripheral and the channel.

For details on the reset operation, refer to the IBM System/37
0 Operating Principle (IBM System/370Princ
iples of Operation. Form G
A22-7000-5, File No. S/370-
01, pages 50-53 and 195).

U.S. Patent No. 4,110,830 (Channel Storage
Adapter) and No. 4,126,897 (Request Facilitator) describe input/output system environments in which the present invention may be advantageously utilized.

U.S. Pat. No. 3,488,633 describes a prior art channel device with input/output system reset capability.

US Pat. No. 3,400,371 describes an environmental system that can be improved by the present invention.

U.S. Pat. No. 3,786,430 describes a system for adding auxiliary processing logic to a central processing system to perform auxiliary processing functions.

This type of auxiliary processing logic can be adapted to perform the ``Programmable Selective I/O System Reset'' operation of the present invention.

Technical Problem By nature, I/O system reset operations are manually initiated when automatic error recovery procedures (eg, retries) are insufficient.

Typically, this type of reset affects all physically available channels and peripherals in the system.

Being manual and indiscriminate may reduce processing efficiency.

Another problem with I/O system resets is that the reset terminates any partnerships (eg, device reservations) between switchably attached peripherals and channels.

The nature and usage of device reservations is described in, for example, the IBM System/360 Components Manual (IBMSyst
em/360 Component Descriptor
ion2841 Storage Control,
IBM System Reference Li
brary File No. 8360-07. For
m A-26-5988-3, pages 32.33)
and Component Sum.
mary 3830 Storage Control
, 3330 Disk Storage. Form G
A26-159.2-0, pageio).

Termination of such an affiliation makes each reserved device accessible from other flexibly coupled (independently monitored) systems before the affiliation can be re-established in the system that generated the reset signal. Do it like this.

As a result, the security of shared data may be compromised.

Another problem with I/O system resets is that if the I/O channel is unable to relay the reset signal to its peripheral interfaces, the reset will fail.

Another problem is that if a group of channels time share a control mechanism, disabling that control mechanism or one of the channels may disable the entire group of channels; This may prevent an I/O system reset from being performed.

SUMMARY OF THE INVENTION The present invention relates to a programmable means for selectively performing an I/O system reset operation with respect to a single channel and I/O interface.

The use of this measure is restricted for devices or control units that have not secured reservations or other affiliations due to programming.

This means is used only by supervisory programs, and only by programs that can ensure that other flexibly coupled systems are deactivated before causing a reset.

This ensures the security of shared data on reserved peripherals that are accessible from other systems.

After performing a reset and resetting reservations and other affiliations, the program operates to ensure that other deactivated systems are reactivated.

Said reset means reside partly in auxiliary logic function means, which auxiliary logic function means are adapted to act as an agent of a central processing system executing program instructions.

The auxiliary logic function means may be adapted to perform the reset asynchronously.

That is, it may be adapted to perform the reset after executing a program instruction specifying the reset.

As a result, the efficiency burden on the central processing system may be reduced.

The auxiliary processor independently controls the channel input/output interface lines.

These interface lines provide peripheral heliset signals associated with each channel (i.e., the operable out line and the inhibit out line).

As a result, the execution of the reset is not impeded by a dead channel or a group of common control channels.

Description of the Prior Art The concept of programmatically generating a system reset signal is not new, generally speaking.

For example, U.S. Pat. No. 378,791 describes an input/output system
A signal processor instruction that can indirectly generate a reset signal is described.

Execution of this instruction initiates the exchange of command and status information between the communicating processing systems.

The command is used to cause an initial program reset operation and a program reset operation in the system receiving it, thereby causing an I/O system reset in a channel attached to the system receiving the command. be done.

However, such a reset is non-selective (does not specify individual channels) and therefore resets all channels added to the system subject to that command.

Additionally, for peripherals attached to blocked channels, the command may not be possible.

In the present invention, the reset function is selectively directed to one designated channel and input/output interface, and the reset function is directed to a designated input/output interface, regardless of the operating conditions of the associated channel. It is efficient in that it is executed by a small auxiliary processor that directly controls the

Furthermore, the present invention is unique in that it provides data security for reserved (or affiliated) peripherals that are accessible from other flexibly coupled systems.

These features of the present invention will become clearer from the following description.

Detailed Description Specific Problems Consider the network of data processing devices shown in FIG.

Central processing units (CPUs) 1 and 2 are connected to human output channels 3-6.

The input/output channels 3-6 are connected to control units 7-11.

The control units 7-11 are connected to a number of equipment units, a few of which are shown as 12-18.

Note that control units 9 and 10 are cross-connected to channels 4 and 5, and the equipment units attached to control units 9-10 are switchably connected to CPUI or CPU2.

Typically, such a connection is accomplished by a two-channel switching special device.

For details, see the above-mentioned IBM System/3
60 Component Description and IBM Component Summary.

Systems related to CPUI and CPU2 are flexibly coupled.

That is, the monitoring programs controlling these CPUs are relatively independent.

Here, the non-selective program reset function
Assume that it is generated for 2.

See IBM System/370 Principles of Operation, page 51, above for the program/reset function.

Typically, this function is generated manually by actuating a switch or pushbutton on the control console.

This causes the CPU reset signal to be applied to CPU2 and the I/O system reset signal to be applied to channels five and six.

Channels 5 and 6, on the other hand, generate system reset signals at their respective input/output interfaces connected to control units 9-11, thereby causing control units 9-11 to
and resetting the associated equipment units 14-18.

Details in this regard can be found in the IBM System/360 and System/370 Human Output Interface, Channel Pair Control Unit (IBM System/360 and System/370
em/370 I/O Interface Chan
Control Unit origin
nal equipment manufacture
r's information-ion. FormAGA2
2-6974-2, File No. s/370-19,
As a result, the shaded network portion of FIG. 1 is reset, and all processing operations for that network portion require restarting.

However, suppose that the problem causing, for example, a program reset is localized to the control unit 11 and that the supervisory program associated with the CPU 2 is notified thereof, for example by an I/O interrupt from channel 6 and a limited channel logout (see above). (See IBM System/370 Principles of Operation, pages 226-228 and 236-242).

If the program has means to generate an I/O system reset signal to channel 6 only, channel 6
, control unit 11, equipment units 16-18 are reset; channel 5, control units 9-10, equipment units 14-15 are not affected.

Considering that typically the equipment unit group associated with one control unit consists of several hundred equipment units,
It is clear that the number of processing operations affected by a reset is significantly reduced.

Therefore, a programmable selective input/output system reset feature would necessarily prove useful in such situations.

Another aspect of the problem is illustrated in FIG.

To simplify matters, in FIG. 2 one direct access storage device (DASD) 40 is connected to the control unit 4.
1 and the central processing unit via channels 42 and 43}4
4.45 is connected to the switching town function to a data processing system associated with it.

These data processing systems are flexibly coupled (independently monitored).

Let these data processing systems be A and B.

Regarding the connection of switching equipment units, see, for example, Section 33 of the IBM System/360 Component Manual.
Please refer to page.

Here, as shown in FIG. 2, it is assumed that the DASD 40 is reserved by the system A (including the CPU 44 and the child channel 42) (device reservation).

Regarding the meaning of [device reservation], please refer to the above-mentioned IBM system/
See page 32 of the 360 Component Description and page 10 of the Component Summary.

It should be understood that a device reservation is a special command issued by one system system's channel and control unit to reserve a specified device from another system until a special release command is issued by the reserving system. (See page 33 of the IBM System/360 Component Description).

As shown in Table 1 below, a non-selective program reset in system A causes a CPU reset at CPU 44 and an I/O system reset at channel 42.

The input/output system reset provides a system reset signal to all control units, including control unit 41.

This system reset signal causes the control unit to reset all equipment units associated with channel 42.

Resetting a device unit terminates each "device reservation" and resets the device unit, such as the DASD 40, to the CPU 4.
4 or 45.

This allows system B, including CPU 45 and channel 43, to use or modify data in equipment units such as 40, for example.

As a result, the integrity of the data seen by both systems may be compromised by the reset operation, as shown in the last step of Table 1.

Therefore, even if System A is later able to re-reserve the reservation of equipment units such as 40, the integrity of the data that System A was using before the reset is not guaranteed.0 Reserved Equipment Units and Control Units Another issue related to this is that of path fidelity.

The reserved control unit and the species control unit (e.g., an IBM 3830 storage control unit operating in search mode) are adapted to maintain exclusive path fidelity with respect to one particular associated channel path. There is.

If a control unit is addressed by another channel path while having such fidelity, the control unit will indicate a busy state, thereby indicating an access unavailable capability.

Reserved equipment units (and e.g. IBM383
Other equipment units so adapted (such as the IBM 3330 disk storage device associated with the 0 storage control unit) have similar exclusive path fidelity with respect to one fixed channel and control unit path. , does not allow communication via other channels.

Peripherals with such path fidelity are
It responds to normal system reset signals only when the reset signal is applied via the associated path.

As a result, if the channel is affected by, for example, an internal channel failure or an external hang on the input/output interface.
UP), if the associated peripheral is disabled by a problem that does not affect its functional operability and is therefore unable to relay the system reset signal to the associated I/O interface. peripherals are effectively isolated and rendered useless.

Once reset, those peripherals are accessible via other paths.

The analysis of the problem so far shows that a new human output reset function is required.

Such a reset function (1) can be selectively directed to particular channels and human output interfaces, and (2) so that reservations are protected and alternative paths are selectively created. (3) Must be able to run under the control of the supervisory program and (3) be viable with respect to associated I/O interfaces and peripherals even when the designated channel is disabled.

The present invention satisfies all of these requirements.

3 and 4 illustrate other aspects of the I/O system reset problem.

Input/output processing system 60 includes six channels 61 that share time-shared microprocessing control circuitry 62 .

Each channel has a network of respective input/output interfaces, associated control units and equipment units.

These are indicated collectively at 64.

The entire group of channels is associated with one central processing system having a central processing unit 6'6.

Thus, a hangup of control circuit 62 or any one channel can effectively disable the entire group of channels and prevent resetting of the entire group of channels.

The outage problem for one channel is illustrated in FIG.

Central processing unit 70 is about to issue an I/O system reset for channel 72 that has been stopped.

Typically, this type of reset requires the channel to simultaneously display a down signal level on the operational and inhibited out lines of the input/output interface for more than 6 microseconds.

(See pages 6-11 and 20 of IBM System/360 and System/370 Human Output Interfaces, Channel Pair Control Units, supra.

) If this behavior is performed correctly by the channel,
All control units and associated equipment units attached to the input/output interface are reset.

However, if a channel is stopped, it will not be possible to perform the above operations with respect to its operating and inhibiting out lines.

Furthermore, when a group of channels operating under common microprogram control is stopped, all channels in the group lose control of their respective operational and inhibit out lines.

One feature of the present invention is the provision of auxiliary logic function means for inhibiting operational out lines and inhibit out lines at individual input/output interfaces independent of channel operability.

Apparatus of the Invention The apparatus of the invention will now be described with reference to the functional block diagrams and logic flow diagrams of FIGS. 5-10.

The specific logic function means may vary according to circuit technology and microsequence control methods.

Those skilled in the art may choose a wide variety of buffers, registers, gates, timing and sequence control means for the functions described herein according to common art implementations.

Please refer to FIGS. 5 and 6.

The programmable selective input/output system reset proposed herein is performed by the interaction of CPU 80 and auxiliary (service) processor 82 (SVP).

The reset function is specified by the CLEAR CHANNEL (CLRCH) program instruction, which has the format shown in FIG.

This instruction is executed by the CPU only when the CPU is in the Supervisor state.

That is, it is executed as a step in the monitoring program (see IBM System/370 Principles of Operation, page 10, supra, for details) and only when the reservation is protected, as described below.

Bits 16-23 of this instruction indicate one channel and implicitly the associated I/O interface.

The instructions send signals from CPU 80 to auxiliary processor 82 indicating the channels and interfaces to be reset.
give to

Auxiliary processor 82 returns to CPU 80 a condition code signal indicating the processing status of the designated reset function.

If the specified channel is physically available,
Auxiliary processor 82 returns condition code 0 and performs the necessary reset signal operations on the specified channel and associated interface.

If the specified channel is not physically available, auxiliary processor 82 returns a condition code 3 to CPU 80 and performs no other functions.

Upon receiving the condition code, the CPU 80 immediately executes CLEAR.
Execution of the CHANNEL instruction ends.

During the execution of a reset operation related to the return of the code O,
The auxiliary processor uses the channel 84 specified by the instruction.
The first and second reset signals are transferred with respect to the first and second reset signals.

A first reset signal is sent via line 83 (FIG. 5) to the designated channel to reset that channel (
human output reset).

The second reset signal is sent via line 85 (FIG. 5) to a logic gating circuit 88,89 that connects channel 84 to the associated enable out line 86 and inhibit out line 87.

These gating circuits 88 and 89 are effectively inhibited by the selective de-gating signal on line 85.

This causes the operational out signal and the inhibit out signal to be brought down for the amount of time necessary to indicate a system reset (at least 6 microseconds), thereby causing a system reset to the peripherals attached to each interface. can be displayed.

The operations of the auxiliary processor that perform the reset signal operations described above may be synchronous or asynchronous with respect to the return of the condition code (i.e., with respect to the completion of execution of each CLEAR CHANNEL instruction by CPU 80).

Referring to FIG. 6, it can be seen that the format of the CLEAR CHANNEL command is the same as the well-known S format.

Regarding the S format, the above-mentioned IBM System/37
0 operation principle.

The first 16 bits represent an operation (op) code expressed in hexadecimal.

The latter 16 bits are used to determine the address of the channel and interface to be reset.

The displacement argument represented by bits 20-31 of the instruction is applied to bits 20-31 of the word contained in the general purpose register specified by bits 16-19.

Bits 20-23 of the result represent the channel address to be reset, and indirectly represent the associated interface.

The first 8 bits of the operation code part are TESTCHANN
Equal to the corresponding bit of the EL(TCH) instruction.

Bits 8 to 15 of the instruction in Figure 6 are CLEAR CHA.
IBM Not Adapted to Perform NNEL Functions
Ignored by System/370 processors.

Such processors interpret the CLEAR CHANNEL instruction as a normal TESTCHANNEL instruction and
Executes the EST CHANN-EL function.

That is, the processor senses the condition of the channel specified by bits 16-23 and stores the corresponding condition code.

However, like CPU80, CLEAR CHANNEL
A processor adapted to perform a function is
Interpret the P code as a CLEAR CHANNEL command and perform the associated reset function.

That is, such a processor conditionally passes a reset signal through an auxiliary processing logic function means, such as auxiliary processor 82, and receives an associated condition code from auxiliary processor 82.

Details of the CLEAR CHANNEL command interpretation and selective I/O system reset operation are shown in Figures 7 and 8, respectively.
HANNEL) instructions required in the CPU 80 and in the auxiliary processor (SVP) 82 to perform the associated reset operations and the interface between the CPU 80 and the SVP 82. Show face.

Block 90 of FIG.
Represents the usual instruction decoding means in a central processor.

Output 92 provides an associated interrupt signal via line 96 to auxiliary processor 82 as shown in FIG.
Conditioning signal driver 94.

Interrupt acceptance control means 98 of auxiliary processor 82 responds to the interrupt signal by passing the channel indication information determined by bits 16-23 of the instruction from CPUgQ to auxiliary processor 82 via line 100 and transmitting it to the auxiliary processor. It is stored in the register 102.

When the interrupt is accepted, the decode function means 104 is enabled and the channel indication information in the register 102 is converted to condition the AND function means 108 to function state 1.
06.

AND function means 108 connects a designated channel Regarding this, the reset signal generation means 110 controls generation of the reset signal.

The decoding function means 104 has an output for each channel of the system, which output is connected to the respective AND function means 1 with respect to the reset signal generation means 110 associated with each channel.
Condition 08.

Furthermore, the AND function means 108 is the two-state latch function means 11.
Conditioned by 2.

Associated with each output of the decode function means 104 (ie for each channel) one such state latch function means is provided.

The latch function means 112 indicates the physical availability of the designated or associated channel X in the system.

If the specified channel
The reset signal is transferred via the functional means 108, the reset signal generating means 110, and the signal paths 116 and 118.

(Transfers the reset signal to the designated channel via path 116 and transfers the reset signal to the interface via path 118.

) The reset signal to the interface must be at least 6
Prevents generation of operational out and inhibit out signals in the associated input/output interface for a microsecond.

As a result, these I/O interface lines are brought down for at least 6 microseconds, thereby indicating a system reset to peripherals attached to the interfaces.

AND function means 108 and latch function means 112 control condition code generation means 120 to return the condition code to CPU 80 via return path 122.

This code is stored and is accessible by the supervisor that issued the CLEAR CHANNEL command.

Transfer of the condition code terminates execution of the CLEAR CHANNEL instruction.

In an embodiment, the condition code is a 2-bit code that can indicate four conditions or conditions, but is originally used to indicate only two conditions.

Condition 0 is the input/output system for the specified channel.
Used to indicate that the reset operation can be completed.

Condition codes 1 and 2 are unused and saved for future use.

Condition code 3 (reset of latch function means 112) is:
Indicates that the specified channel is not operational (physically available) in the system.

Execution of the reset operation causes all inbound interface lines of the specified interface to be dropped after a delay depending on the length of the external cable.

CLEAR CHANNE FOR RESERVED PERIPHERALS
USING THE L INSTRUCTION FIG. 9 and Table 1 illustrate how the CLEAR CHANNEL instruction is used in System A with respect to reserved equipment units accessible from System B that are independently monitored.

As shown at 198 in Table 1, system A associated with multiple channels including CPU 200, auxiliary processor (SVP) 202, and channel 204 (FIG. 9) detects an error in the input/output path associated with channel 204. I might.

Such errors may be indicated to the system A supervisor by I/O interrupts and limited channel logout from channel 204 when channel 204 is operational.

If a channel has been disabled and the coprocessor has a means to detect such disabling, a machine check interrupt from coprocessor 202 may similarly indicate.

Before issuing the CLEAR CHANNEL command for channel 204 (step 206 in Table 1), the supervisory program of system
08).

System B is added to channel 204 and system A
The device unit reserved for the device can be accessed.

Such deactivation is performed by linking means 2 between the two systems.
10 (FIG. 9).

Coordination means 210 provides an all-electrical link between the two systems (
channel-to-channel or direct control) or manual intervention, such as a control console signal by an operator of system A and deactivation of system B by manual operator action.

This deactivation step is shown at 212 in Table 2.

After a selective I/O system reset with a CLEAR CHANNEL command is performed on channel 204 (step 206 of Table 2), reservations and other affiliations between peripherals attached to channel 204 and system A are The settings are reset as shown in step 214 of Table 1.

The above peripheral device was aborted by the above reset.

The deactivated system (eg, system B) is then reactivated via the linking means 210 described above, as shown in step 216 of Table 1.

Systems A and B may then resume normal or independent operation, as shown in step 218 of Table 1.

Deactivation of system B prevents system B from compromising the security of data used by system A between the reset step 206 and the reconfiguration step 214.

Common usage of CLEAR CHANNEL instruction No. 10
The figure specifically shows how the reset by CLEAR CHANNEL instruction is used by the supervisory control program.

This program is CLEAR CHANNEL (CL
RCH) has two separate sequence paths for generating the reset function associated with the command.

Sequence path 280 is concerned with recovering from problems indicated by I/O interrupts;
Sequence path 284 is concerned with recovery from problems indicated by machine check interrupts.

I/O interrupts are provided by specific channels, thereby individually indicating which I/O paths require resetting.

Machine check interrupts are provided by processing means, such as the auxiliary (service) processors described above, and do not require specific designation of the I/O path, nor do they indicate the need to reset the I/O path.

In program sequence path 280, CLRC
The action taken when an H reset is required depends on the reservation state of the peripheral.

This condition is tested at program decision point 286, and if there is no reservation, the program sequence branches to the generation of the CLRCH instruction at 290.

If a reservation or other commitment is valid at decision point 286, the program at 292 ensures the deactivation of any conflicting systems or processes before proceeding to the CLRCH instruction at 290. Operate.

After generating a CLRCH reset at 290, the program branches at 294 according to the conditions of the input/output paths associated with the reset.

The availability of an input/output path is determined by the TESTCHANNE of the system/370 directed to that path, even if it does not appear in the status information exchanged by a human output interrupt.
It may be determined by executing an L (TCH) instruction or a TESTI/0 (TIO) instruction.

The availability of the aisle to be reset is determined to be either unavailable at step 296 or available at step 300, and the program then branches at 302 based on the reservation status as determined at decision point 286. .

If the reservation or other commitment was in effect before the reset, the program determines at 304 whether the same I/O path or an alternate path (if the same I/O path is not available and an alternate path is available) ) and then evaluates the effectiveness of the reconfiguration operation at 308.

If the reconfiguration operation was successful, the program returns 310
Restart the I/O process associated with the path being reset as shown at 312 and restart the previous program process as shown at 312.
Step 292 reactivates the quiesced system.

If the reservation was not valid before the reset operation,
From decision point 302, the program proceeds to restart the I/O processes affected by the reset operation on the same channel path or on an alternate path.

After step 310, the program continues with other functions other than reset.

If the I/O restart at 310 is not successful, the program will display a permanent error before proceeding.

If the test at 308 shows that the reservation resetting was not successful, the program places the system in a wait state as indicated at 314.

In that case, in sequence path 284 associated with a machine check interrupt that requires manual intervention to continue system operation, the program generates a number of TEST CHANNEL (TCH) instructions, as shown at 320, and At 322, it is determined whether a particular channel in the channel group (eg, 61 in FIG. 3) is lost.

If the determination in step 322 indicates that no channel is lost, the program continues normal operation and determines the cause of the interrupt, but if the channel or I/O path is not the cause of the interrupt, a reset is necessary. It is effectively recognized that this is not the case.

On the other hand, if the determination at 322 indicates that the rechannel is lost, the program executes a series of CLRCH instructions on the affected channels, as indicated at 324.

These reset operations are performed by the auxiliary processor (s) in FIG.
vp) 82.

If the program encounters a permanent error, the auxiliary processor executes an initial microprogram reloading (Re-IMPL) operation as indicated at 326 before proceeding to steps 294-314 described above. For example, 62) in FIG. 3 may be restarted.

If a Re-IMPL action is taken, step 294
There is a 30 second delay in the continuation of the program operation with respect to ~314 as shown at 328.

By using the CLRCH command capability described above and the programming method shown in FIG. 10, a reset means having the following characteristics is realized.

(1) The reset means can selectively initiate a system reset operation for one particular channel and associated input/output interface.

(2) This reset means can be controlled by a monitoring program.

Therefore, it should only be used when reservations are protected by quiescing potentially interfering systems, and only when input/output paths (original or alternative) are available for resetting reservations. can.

(3) The reset means can perform a reset on the designated input/output interface even when the designated channel is disabled.

[Brief explanation of the drawing]

1 to 4 show various problem situations that can be solved by the present invention, FIG. 5 shows a system implementing the invention, and FIG. 6 shows a selective input/output system according to the invention. Program instruction CLEA that generates a reset
The format of R CHANNEL is shown in Figure 7.
FIG. 8 shows the logical structure of an auxiliary processor that performs a selective I/O system reset operation; FIGS.
How the L command is used and how the reservation of equipment units is protected (i.e., how data is secure) with respect to other flexibly coupled (independently monitored) processing systems. how protected it is). 80...Central processing unit, 82...
Auxiliary processor, 83... Attendance calculation signal line, 84... Input/output channel, 85...
・Selective target (prohibition) signal line, 86... Curve operation possible out line, 8γ... Suppression act line, 88
．． 89...Logic gate circuit.

Claims (1)

[Claims] 1. A device having a plurality of input/output channels, each input/output channel being connected to a control unit and peripheral devices via an input/output interface, and each input/output channel being connected to a control unit and peripheral devices via an input/output interface, and being connected to a control unit and a peripheral device by a signal on a particular line in the input/output interface. In a data processing system in which associated peripheral devices are adapted to be reset; a processor for generating a reset command signal indicating one selected input/output channel in response to instructions in a predetermined format; and generating a first reset signal supplied to the selected input/output channel and a second reset signal supplied to the particular line in response to the reset command signal. , an auxiliary processor for resetting the selected input/output channel by the first reset signal and resetting the associated peripheral device by the second reset signal.