JPS5841525B2 - Direct memory access system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention continuously reads or writes (hereinafter referred to as read/write 1) a memory area divided into blocks of non-consecutive addresses by direct memory access (hereinafter referred to as I MA). This relates to the read/write method used.

The conventional read/write method using DMA has one address register, and the start address of the read/write area is set in the address register by a program.
A read/write is performed when a start instruction is given, and the end is recognized by counting the number of read/write bytes or by determining an end code, and is notified to the program by an interrupt or the like.

In this method, in order to continuously read/write the memory area divided into blocks 5, 6, 7, and 8 with non-consecutive addresses as shown in FIG. The time (interrupt waiting time + program processing time) from when the program is started until the start address 2 of the second block 6 is set must be made as short as possible.

For example, when reading/writing data on a 4800 BPS line, the above-mentioned time constraint is about 1.6 ms, and it is difficult with conventional methods to always keep the time constraint within this range.

The present invention solves the drawbacks of the conventional DMA method described above with a relatively simple circuit, and provides a versatile DMA read/write system.
It is intended to provide a light method.

In order to continuously read/write a memory area divided into blocks of non-consecutive addresses during read/write using DMA, the present invention provides an input/output control unit with one binary counter for updating addresses and one binary counter for updating addresses. Equipped with one register for storage; ■When a block read/write is completed, the contents of the register for address storage are transferred to a binary counter for updating the address, and the next block is continuously read/written. However, the first address of the next block is further set in the vacant address storage register, so that reading/writing can be performed continuously.

FIG. 2 shows an embodiment of the present invention.

In Figure 2a, A-1 to A7 are AND circuits, N1 to
N3 is a NOT circuit, OR is an OR circuit, B1. B2 is JK
Flip-flop, 9 is a register for storing addresses, 1
0 indicates a binary counter for updating the address.

Also, DATA BUS is a bus that provides address information as data, ADRBUS is an address bus, 11 is a command signal when setting an address, 12 is a command signal for completing one block by DMA, 13 is a count pulse of a binary counter, and 14 is a bus that outputs an address. Address bus ADRBUS
This is a gate signal to be placed on the

Next, the operation of the circuit shown in FIG. 2a will be explained with reference to the time chart shown in FIG.

First, in order to set the starting address 1 of the first block 5 shown in FIG.
When T11a is applied, flip-flop B2 is reset in the initial state, so its 0 output terminal becomes "
1'', the address set signal 11a is applied to the counter 10 through the AND circuit A3 and the OR circuit OR, and is also applied to the register 9.

Therefore, address information on the DATA BUS is set in register 9 and then in counter 10.

Flip-flop B1. B2 is address set signal 1
A trigger pulse is given at the falling edge of 1a, and in the initial state B
Each 0 output terminal of l t B2 is tl 1 n, but
When this trigger pulse is given, the J terminal of the flip-flop B1 in the previous stage becomes tt Q It, and the K terminal becomes 1.
'', its O output terminal holds "1".

However, in the flip-flop B2, since the output of the AND circuit A2 is 0 and the output of the 1-NOT circuit N3 is 1'', the outputs are inverted, and the 1 output terminal becomes ``1'' and the O output terminal becomes 01+.

That is, AND circuit A3 is turned off.

In this state, an address set signal 11b is subsequently sent to set the leading address 2 of the second block 6 shown in FIG.

This signal is not applied to the counter 10 because it is cut by the AND circuit A3, but is applied only to the register 9.

Therefore, the second block start address 2 on the DATA BUS is set in the register 9, but the first block start address 1 remains set in the counter 10.

Also, at this time, as mentioned above, the flip-flop B in the latter stage
2 is set, so at the time of trigger, the J terminal of the front flip-flop B1 is ]", and the K terminal is 0", so the front flip-flop B1 is set.

In this state, the gate signal 14 is turned on to open the output gate circuits A6 to A7 of the counter 10, and the count pulse 13
, the contents of the first block 5 in FIG. 1 are read.

When the read of the first block is completed, the DMA of one block is
An end signal 12 is issued.

This signal is applied to the counter 10 through the OR circuit OR, thereby setting the contents of the register 9 in the counter 10.

This DMA end signal is also connected to a NOT circuit N2. Through the AND circuit A1, the flip-flop B1. B2 as a trigger signal, and at this time, the previous flip-flop B
1's J and K terminals are both 1'', so its O output terminal becomes 1'', but since the subsequent flip-flop B2 picks up the state of the previous flip-flop B1 before inversion in terms of timing, the output is not inverted.

Next, in order to set the first address 3 of the third block 7 in the register 9, an address set signal 11e is applied. Since the AND circuit A3 is off, this signal is not applied to the counter 10, but is applied only to the register 9. Added D
Third head address information on the ATA BUS is set in register 9.

At this time, the 0 output terminal of the previous stage flip-flop B is O”
becomes.

Further, when the DMA ends, the program is interrupted, and after the program is processed, it is set by the next address program.

In this way, it is possible to lead continuously without crossing the 11th, 2nd, 3rd, etc. blocks.

The same applies to lights.

As explained above, by providing one binary counter and one register, the present invention can reduce the program interrupt processing time from 1 to 2 ms in the conventional system to several tens of milliseconds.
This can be extended to more than m5 (that is, about the time required to read/write a block), and it is possible to eliminate obstacles in programming.

Furthermore, the number of interfaces for outputting addresses to the DMA address bus is the same as in the conventional system, which is more advantageous than providing two binary counters.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of an area divided into blocks with non-consecutive addresses, Fig. 2 a is a circuit diagram showing one embodiment of the present invention, and a timer diagram drawn to explain the operation of a. It is a chart. Explanation of codes, 1 to 4...Start address, 5 to 8
... Memory block, 9 ... Register for address storage, 10 ... Pinary count for updating address, 11 ... Address set signal,
12...DMA end signal, 13...Count pulse, 14...Address output gate signal, A, ~A7...AND circuit, B1. B2・
...JK flip-flop, N, ~N3...
...Knot circuit, OR...OR circuit.

Claims (1)

[Claims] 1. An address storage register that captures address data on the data bus in response to an address set signal;
A counter that takes in address data from the above register in response to a signal indicating the end of a direct memory access DMA operation for one block, updates this value sequentially in response to a count pulse, and outputs it, and a counter that responds to the first address set signal. The control means allows the transfer of address data from the register to the counter and controls the transfer in response to a subsequent address set signal, and uses the output of the counter as an address to transfer the address data to the memory area. A DMA operation is performed on one block of data, and during the DMA operation, the start address of the block to be accessed next is set in the above register, and the above D
A read/write method using direct memory access, characterized in that the start address of a new block is transferred from the register to the counter when the MA operation ends.