JPS5837725A - Control system for occupancy of bus line - Google Patents

Abstract

PURPOSE:To perform occupancy control with one occupancy controlling line, by applying a timing signal for address information transmission to each unit device, transmitting address information from a high-order bit in order in synchronization with the timing signal and comparing the priority. CONSTITUTION:An occupied address information generating circuit 5 outputs occupancy address information assigned in advance in a unit device in synchronization with a timing clock outputted from a timing signal generating circuit 2 from the high-order one by one bit. The outputted occupancy address information is compared with a value appeared on an occupancy controlling line 11 at a comparison circuit 7. The timing signal is applied on a timing signal line 9 to each unit device among the unit devices. A start signal which indicates that any of the unit devices starts a bus fetch processing, is transmitted to a start signal line 10. The occupied address information is transmitted to the line 11.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides that when several unit devices OII such as a processing device, a storage device, and an input device are connected to a common path line, only one of the unit devices OII is connected to a common path line. This invention relates to a pass line occupancy control method that allows lines to be exclusively occupied.

In information processing systems such as electronic computers, there is a method in which unit devices such as a processing device, a storage device, and an input device are connected to a common path line, and information is mutually transmitted between the unit devices. In Jin's method.

This is the only unit device that can use a common path line at any time; each unit attempts to acquire a common bus by issuing a request to use the common bus before transferring information. If a plurality of unit devices simultaneously issue requests to use the common path, the device with the highest priority is given the right to use the common path.

Now, there are several conventional common path line occupancy control methods, but it is possible to disconnect each device or turn off the power to each device without stopping the operation and function of the common path line. As a method, 41 Kosho 54-151
There is a method shown in Publication No. 93, No. 111K.

In this method, a common path line is provided with multiple occupancy control lines through which priority signals of multiple unit devices are sent and received.
Each unit is wired or coupled to the occupancy control # of the unit. When a unit device attempts to acquire a bus, each unit device sends out priority signals assigned to each unit in order, starting with the one indicating the highest level of occupancy control line. eye.

If a signal higher than this signal is sent to the occupancy control line, the signal value on the occupancy control line and the value of the priority signal output from the storage unit are different. The difference between the two signal values is detected by comparing the priority signal currently output by a comparator provided in the unit device with the signal on the occupancy control line. If the priority signal being sent is not lower than the signal appearing on the occupancy control line, the next priority signal is sent to the next one of the occupancy control lines. Furthermore, if the priority signal being sent is low, the sending of the next priority signal is stopped. In this way, when all the priority signals fIi assigned to a unit device match the values on the occupancy control line, only O unit devices can occupy the common path line.

In this path line occupancy control method, each unit device takes the initiative in acquiring the common path line, so each unit device can be separated from the common path line, and priority is determined by the physical mounting location. It has the advantage that it does not depend.

However, the above-mentioned running force type requires several occupied control lines, making the hardware such as a comparator complicated.

Further, since the number of common path lines inevitably increases, this problem arises in terms of wiring and :F wiring. Furthermore, when the number of connected unit devices is increased, the number of occupied control lines must be increased, resulting in a lack of system flexibility.

The present invention relates to an improvement of the above-mentioned pass line occupancy control method, and an object of the present invention is to propose a pass line occupancy control method using one occupancy control line in order to solve the above-mentioned nine problems. .

The pass line occupancy control system of the present invention will be described in detail below using embodiments of the present invention.

FIG. 1 is a block diagram of a path acquisition control device included in each unit device connected to a common path line.

1 is a flip 70 indicating that bus acquisition processing is being executed on the common path. 2 is a circuit that generates a timing block necessary for path acquisition processing. Reference numeral 3 denotes a flip-flop that stores information on when a bus use request has occurred in this unit device. 4 indicates that this path acquisition device has started bus acquisition processing. Reference numeral 5 denotes a circuit that generates a signal (processing start signal) for notifying the inside of the device and other unit devices that this bus acquisition device has started bus acquisition processing. 6 receives a processing start signal output from the circuit 5 and synchronizes with the timing clock output from the timing signal generation circuit 2;
This is an occupied address information generation circuit that outputs occupied address information previously assigned to this unit device one bit at a time from the highest order. 7 is a circuit that compares the optical occupancy address information outputted from the circuit 6 with the value of the occupancy control 11111K, which will be described later. This is a flip-flop indicating that this unit device has obtained a pass. Reference numeral 9 denotes a timing signal line for supplying a timing signal to each unit device for synchronizing the transmission of the occupied address information (aligning the positions of the transmitted occupied address information). Reference numeral 10 denotes a start signal line to which a start signal indicating that one of the unit devices has started bus acquisition processing is sent. Reference numeral 11 denotes one occupancy control line through which the occupancy address information is sent. 12, 13, and 14 are timing signal lines 9, respectively. Start signal 4110. This is a receive gate that receives a signal from the occupancy control line 11. 1
5.16 are the start signal lines 10. Occupancy control m1
1 is a drive gate connected to 1. Especially dry,
The block gate 16 has an open collector output.

To be sure of this, the occupied address information output from this drive gate 16 is wired ORed on the occupied control line 11, and when logic "0#" and logic "1#" signals are output to the occupied control line 11 at the same time. Uniquely determined to one of the values.

In this embodiment, priority is given to the Il"l" signal. 17
18 is an inverter gate. 19.20 is AND
At the gate, 21 is an OR gate.

Next, the operation of this embodiment will be explained with reference to FIG. Figure 2 is an operation timing chart of the bus acquisition device.

When a bus use request is issued within this unit device, a bus acquisition request signal is sent via the signal line 22 to a flip 7-bit (
Hereinafter referred to as FF) 3 sector However, input to the terminal IFP3
Set. At this time, if the special bus acquisition process is being performed by the occupancy control device of another unit device, FF1 is set. Ninth, AND gate 19 cannot take the AND condition, and now prl is reset. shall be. When FF3 is set by the path acquisition request signal, the AND condition of the AND gate 19 is satisfied, and F'F4 is further set via the 1COR gate 21. 1Ft4 (暉輿; t゚氇) and its Q output signal operate the circuit 5, and a processing start signal is output to the signal line 23. This processing start signal is transmitted via the drive gate 15 to the start signal. line 10
is output to. As a result, this processing start signal is input to the FF1 via the receive gate 13 and the signal line 24, and the FP
I is set (Similarly, 9 PF1 provided in the occupancy control device of another unit device is also set), and when FFI is set, the output timing generator circuit 2 is operated by the Q output signal, and the signal line On 25th, 26th and 27th, the Thai power inertia TA, TB, and TC are outputted, respectively.

These timing signals TA, TB, and TC are signals synchronized with a timing signal inputted via the tying signal line 9 and the receive gate 12.

On the other hand, the circuit 6 starts its operation in response to the processing start signal outputted from the first circuit 5, and outputs the upper bit of the occupied address information using the timing signal TBK. At this time, since the drive gate 16 is enabled by the Q output signal of F4, the signal of the most significant bit is sent to the occupancy control line 11 via the drive gate 16. Assume that the most significant bit output from the circuit 6 is the logic "O'm." At this point, at the same time, the occupancy address information of the logic ``1'' is transmitted from the occupancy control device of another unit to the occupancy control line 11. If it is output, this occupancy control line l
Wired Oa is taken on l, and the logic '1# signal is given priority. Comparison circuit 7 compares the occupied address information signal outputted from circuit 6 and the signal on occupied control line 11 in accordance with timing signal TH. As mentioned above, if a high-priority occupied address information signal is output from the occupation control device of another unit device, the comparison circuit 7 will not find a match.At this time, the comparison circuit 7 will output a mismatch signal. Ru. This mismatch signal is on signal line 28. It is input to the reset (to) terminal of FF4 via the AND gate 20 (because FF8 is reset and φ), and FF4 is reset. This indicates that the I(s) cannot be acquired and FF4 is reset, so the drive gate 16 becomes unable to output, and the signals after the next bit of the occupied address information from path 6 are output to the occupied control line 11. In addition, the sending of the start signal from the 1 circuit 5 is also stopped.At this time, since FF3 is set to 11, the path acquisition process for the occupied # device of the other unit devices is completed. ,
When the FFI is reset, the path acquisition process is started again by a signal from the FF3.

As mentioned above, when the most significant bit of the occupancy address information is output from the 9 circuit 6 and this most significant bit signal is sent to the occupancy control line 11, the priority of this most significant bit signal is high (actual On the downstream side, either l!aIJl"l") or 2K if there is no simultaneous bus acquisition request from other unit devices.
Fi.

Signals sent from circuit 6 and occupied control line! The signal on l matches. When this coincidence is detected by the comparison circuit 7, the comparison circuit 7 does not output a signal. As a result, the next bit signal of the occupied address information is outputted from the circuit 6 in synchronization with the timing signal TH, and the occupied control #IIK is sent out via the drive gate 16 which is in the enabled state.

As described above, if the comparison circuit 7 finds a match between the signal output from the single circuit 6 and the signal on the occupancy control line 11 up to the least significant bit of the occupancy address information, it is determined that the path acquisition has been successful. At the point in time, the timing signal TC is output from the timing generation circuit 2 and inputted to the FFJI terminal 7a (CK) via the signal line 27. PP4 in set 11 is attached to the F'IP80D terminal.
The ninth timing signal TO where the q output signal is input is
FF8 is set by the input KK, is this the result of Jin? 7
3 is reset.

4. Signal S as Q output signal of FF8 and path acquisition signal
It is sent into the unit device via ZS.

The pass line exclusive control method of the present invention has been described above in detail with reference to one embodiment.According to the pass line exclusive control method of the present invention, each unit device takes the main role in acquiring a common path twin.

Each unit device can be separated from the common path line,
Another advantage is that the priority does not depend on the physical actual value position. Moreover, the present invention realizes this with simple hardware. In addition, according to the present invention, when the number of unit devices connected to a common path line increases, the flexibility of the system is achieved by simply changing the occupied address information and timing signal assigned to each unit device. It has the advantage of being large.

[Brief explanation of the drawing]

1 is a block diagram of an embodiment of an occupancy control device according to the present invention, and FIG. 2 is an operational diagram of the device according to the embodiment. 2... Timing signal generation circuit 6... Occupied address information generation circuit 1... Comparison circuit 10... Tying signal line 11-- Occupancy control line 25-- Timing signal TA signal line 26-- - Tying signal TB signal line *r-... Tying signal TC signal line

Claims (1)

[Claims] When a plurality of unit devices such as a processing device, a storage device, and an input/output device are connected to a common path line, the common path line is exclusively used for only one degree device among the unit devices. In a pass line occupancy control method that allows On the common path line, the unit device serially transmits and receives the occupied address information assigned to each device bit by bit starting from the high-order bit, and one of the two values sent at the same time has priority over the other. A book occupancy control line and a timing signal line for supplying a timing signal to each unit device for synchronizing the transmission of the address information between each unit device are provided, and each unit device means for outputting the address information one by one from the high-order bit to the occupancy control line in synchronization with the timing signal; and means for comparing the output value with the value on the occupancy control line. Equipped. When the output value and the value on the occupancy control line do not match, stop outputting the address information of the next bit, start the path acquisition operation again, and when the output value and the value on the occupancy control line match. outputs the next bit address information. A pass line occupancy control method characterized in that when all pits of address information match, the pass line acquisition operation of the unit device is completed.