JPS5837597B2 - If you have any questions or concerns, please do not hesitate to contact us. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates primarily to the manual scanning of width modulated bar codes, and more particularly to the processing of signals produced by such scanning and minimizing the opportunity for improper data collection during the scanning process. Concerning the design of concise logic circuits for.

The present invention was developed by Bruce W.
W. Dobras) US Reissue Patent No. 28,19
This is an improvement on the device shown in No. 8.

The apparatus shown in this US patent application can be used to scan width modulated bar codes.

Generally speaking, Dobras' device includes an optical bar code scanning stylus designed not to be manually drawn onto a record or ticket with a width modulated bar code.

This device is shown in its entirety in FIG. 1 of the above-referenced U.S. patent, and includes bar width decoding logic assembled from five counters, two adders, and a fairly complex array of gates and steering logic. There is.

The main purpose of the present invention is to provide a simplified form of decoding logic that is comparable in capacity to the logic used by Dobras.

In particular, one aspect of the invention can perform the same basic functions as the logic described above, but essentially includes only one counter, two shift registers, and four serial adders.

Dobras' device, described in the above-mentioned U.S. patent, is
It includes error checking circuitry that signals when an incorrect character is scanned or when the scan speed is too slow or too fast.

These basic error checks are sufficient to prevent the accumulation of most erroneous data.

However, some mistakes may be missed that occur less frequently but still reduce the reliability of the data scanning process.

It is therefore another object of the present invention to provide a barcode that can detect almost all scanning errors, even if they occur only occasionally, and can guarantee nearly 100% accuracy in the data collection process in any case. The first step is to design a scanning system.

Another object of the present invention is to achieve this ability to detect scanning errors in a simple device with low cost per unit.

In general, in one aspect of the present invention, a bar code scanning system that includes a simple logical subsystem for comparing the relative widths of scanned bars and blanks and provisions for rejecting erroneous data. It is configured.

This system is more effective than any existing device known to the applicant.
Because it is error sensitive, it cannot be erroneously operated by unskilled personnel, such as those often employed as cashiers in retail stores.

The system refuses to scan most records that have been inadvertently or intentionally altered, and also refuses to accumulate data if a scanning operation occurs when attempting to change price data for an item.

This system uses a conventional barcode scanning stylus and conventional analog input circuitry.

During the time required to scan each bar and blank code element in the series, one counter in the system is counting evenly spaced clock pulses.

Each time a bar or blank code element is scanned, this counter produces a number proportional to the time taken to scan the element.

This string of digits is instantaneously transferred to a shift register.

The shift register has at least four outputs from adjacent shift register stages.

Each time a number is loaded into the shift register, the number it contains is immediately sent forward in series and appears on the four outputs in serial form.

For reasons that will be explained more fully later, the first output represents the number itself, the second output represents the number multiplied by 2, the third output represents the number multiplied by 4, and the fourth output represents the number multiplied by 8. .

The serial adder adds the first and second outputs and displays a number multiplied by three, and adds the first and third outputs and displays a number multiplied by five.

The number multiplied by 5 is sent to k shift registers and stored in f for comparison with the numbers multiplied by 3 and 8 later.

A pair of comparator circuits, which are serial arithmetic units, are used to compare the stored 5x number represented in the shift register with the undelayed 3x and 8x values represented on the serial adder. It will be done.

The comparator circuit can accurately determine whether the stored number is large, near, or small compared to other numbers, and whether the most recently scanned bar or blank element is wider than the previously scanned elements. , narrower or the same order of magnitude can be determined accurately.

The comparison results of the several comparisons are used to address the read-only storage and initiate a retrieval from the storage of data corresponding to the data content of the series of bars and blanks.

The use of read-only storage to convert comparison results into output data is not new per se, and is illustrated, for example, in Figure 7 of Dobras, cited above.

However, one aspect of the present invention is the operation of separately converting the results of comparing each of the individual bar widths of a certain character and the result of comparing the blank widths from multiple elements.

The separate conversions are performed in smaller read-only storage than would be required if all elements of the character were being decoded as a unit.

The separately decoded read-only storage output data for a character is captured using a pair of latches that allow all decoded data representing that character to be displayed simultaneously.

Besides the basic character errors and scanning speed verification mentioned above,
The system performs some special error checking.

These error checks are geared towards specific things such as incorrect scan conditions or data errors that are only occasionally encountered.

Overall, these error checks only marginally increase the cost of the overall system and make it nearly impossible for the system to accept incorrect or corrupted data.

One of the mistakes often encountered when system operators begin a manual scanning motion in the middle of a string of barcode characters, move the scanning stylus out, and end up crossing the last start or stop character in the string of data. happens.

Previous scanners began looking for barcode characters in response to passing this start or stop character.

One aspect of the invention detects that a start or stop character as described above is not followed by another bar code character, and does not begin scanning until the stylus is moved from the edge of the record back to the center of the record.

In one aspect of the invention, the same timing mechanism that aborts the scan when the scan rate is too slow performs this error check.

It may also be possible to accidentally or deliberately fill in the blank space between two adjacent bars, thereby changing the normal letter to the start or stop letter E.

Such changes have the effect of reducing the apparent price of the product, for example by reducing the number of digits used to indicate the price.

To prevent this type of error, one aspect of the present invention compares the time required to scan any final start or stop character to the time required to scan the blank space following that final start or stop character.

Untimely start or stop characters are necessarily followed by closely spaced barcoat elements, and this condition is detected by the comparison described above.

No data will be accepted from records containing such untimely start or stop elements.

The logic that makes this comparison is also used to indicate an error if a side bar code character is scanned too slowly.

As an additional safeguard, the system will reject the scan if the final start or stop character occurs within six characters of the first start character.

This is because normally any record would not have such a small number of characters.

Of course, the number of characters may be more or less than six, depending on the length of the record to be scanned.

Other incorrect scanning techniques that can cause errors include moving the stylus from one coded area to a second barcode, e.g. if the stock count in one record is changed to another in the above way. It may be combined with the price of the record.

To prevent this from happening, an extension of the same counter that measures the time it takes to scan an individual barcode element is added to the time it takes to scan the white space separating two characters. Used to set a limit of .5 seconds.

This time limit can also be lengthened or shortened depending on the nature of the record to be scanned.

In addition, Dobras's device described above includes bar and blank width decoding logic that counts constant periodic pulses during the scanning of the bar and blank code elements, thus decoding the width of each element. There is a counter array that produces a number or count that is proportional to the time taken to scan.

It can be assumed that these numbers or counts are approximately proportional to the width of the scanned element; of course, this assumption is only valid as long as the scan is proceeding at a fairly constant speed.

If there is a sudden change in scanning speed, the above assumptions are no longer valid.

To use a simple example, if the scan rate suddenly slows down, the sudden change in scan rate will cause a narrow bar to widen.

Similarly, if the scanning speed increases rapidly, a wide bar will appear narrower.

Such sudden changes in scanning speed often result in polarity errors and can therefore be detected.

However, such changes may pass undetected and erroneous data may be accumulated.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a scanning system in which rapid and sudden changes in scanning speed can always be detected.

Broadly speaking, the present invention comprises an improved bar code scanning system with a scan rate error detection mechanism.

This mechanism measures the time required to scan groups of bars and blanks and compares these time measurements to each other.

If the times are substantially different from each other, the mechanism aborts the scan.

The preferred embodiment of the invention is designed for scanning barcoded characters of a constant width, each of four bars and three intervening spaces.

Since the width of the characters is kept constant, the mechanism is set up to measure the time to scan successive characters.

This time measurement is performed by a computing device that sums up counts representing the time required to scan each bar and space in each character.

These bar and blank width counts are generated elsewhere in the scanning system.

The resulting character scan time is doubled, divided by 2, and compared to the scan time of the previous or subsequent character using comparison logic.

If the time required to scan a character is more than twice or less than half the time required to scan an adjacent character,
The mechanism issues an error signal and aborts the scan.

Other objects and advantages of the invention will become apparent from the detailed description below.

A preferred embodiment of the invention is a digital logic system used to analyze electrical signals resulting from manual scanning of bar coded records.

The logic system that will be described is such that the signal resulting from scanning is first processed by a circuit to convert the signal into a stable two-level digital signal, so that when a bar is scanned, the blank space between adjacent bars is scanned. It is suitable for use with conventional barcode scanning styli and the like, as long as it is sometimes low.

The details of the scanning stylus and counting circuitry used are not important to the invention.

A suitable stylus is described, for example, in U.S. Pat. No. 3,509
, 3 5 3 or French Patent No. 1.3 2 3,2
7 As shown in No. 8.

A suitable amplifier circuit can be constructed using, for example, a high gain audio amplifier to drive a Schmitt trigger type circuit.

Preferably, the amplifier and Schmitt-trigger type circuit are coupled together with a capacitor, and a dual level clamp circuit is preferably connected to the Schmitt-trigger type terminal of the capacitor.

Other equivalent scanning, signal amplification, clamping, and counting elements may also be used with the present invention.

Referring to FIG. 1, a system 100 is shown that represents a preferred embodiment of the present invention.

The system 100 includes a stylus 10 that is manually traversed over a printed record 104 of barcode characters 106.
2.

The barcode character 106 is shown in more detail in the upper part of FIG. 7 and, as can be seen, consists of four elements, four black bars spaced apart from each other and three spaces between them.

Stylus 102 is the illumination source for character 106 and character 1
It is desirable to have means for converting the light reflected from 06 into an electrical signal.

The electrical signal is sent via line 108 to a conventional analog input circuit 110, the nature of which has already been briefly described.

The analog input circuit amplifies, limits, and digitizes the output signal of the stylus 102 and generates an ANALOG signal that is high when a bar is scanned by the stylus and low when a blank space between adjacent bars is scanned. ) produces a binary signal called .

For example, the ANALOG signal is zero volts when a blank is scanned, and +10 when a bar is scanned.
Bolts are fine.

The ANALOG signal is a signal from the analog input circuit 110.

This signal can take a first value when the stylus is scanning the rod and a second value when it is scanning a blank space, but it is a signal processed only by analog circuitry and is not digital. A signal that is not processed by the circuit.

Therefore, in this specification, this signal will be referred to as an ANALOG signal (analog signal).

Regarding this ANALOG signal, please refer to the ANALOG signal in Fig. 7.
This results in a signal with a waveform shown as G.

The present invention uses counter 114 to measure the width of consecutive bars and blank code elements by measuring how long the ANALOG signal remains at one of its values. ing.

For this purpose, the system uses a first radio-frequency pulse (CA
A clock 115 is provided for producing a high frequency pulse (CB pulse) and a second high frequency pulse (CB pulse) such that each CA pulse is followed by a CB pulse and vice versa.

Clock 115 is a free running clock that provides CB pulses at a rate of 200K pulses per second.

These pulses are continuously sent to counter 114.

In response to swings of the ANALOG signal in either direction, digital input circuit 112 generates a short duration 2B signal pulse to clear counter 114.

Approximately at the end of the 2B signal pulse, the counter 114 begins counting the CB pulses that have occurred and continues counting these pulses until the next 2B signal pulse is generated in response to the fluctuations in the ANALOG signal. continue.

Since the ANALOG signal swings each time stylus 102 makes a bar-to-blank or blank-to-bar transition, counter 114 measures the time it takes for stylus 102 to scan each bar and blank element. Can be counted.

After each such element is scanned, the counter 114 is left with a number proportional to the time it took the stylus to scan the bar or blank element; a 2B signal pulse clears the counter 114. Immediately before, the contents of counter 114 are loaded into shift register 116.

Each character 106 thus printed on record 104
A digital value proportional to the time taken by the stylus 102 to traverse each successive bar and blank element of the stylus 102 is successively loaded into the shift register.

The next step in the process of decoding bar and space code information is determining the relative widths of each character's bar and space code elements.

For error detection purposes, each character has one wide bar, three narrow bars, one wide blank, and two narrow blanks.

The width of each bar element of a character is compared to the width of one or two adjacent bar elements of the same character.

The width of each blank element of a character is compared to the width of one or two adjacent blank elements of the same character.

Since each character contains four bar elements, the bar width comparison is performed three times.

That is,. This is a comparison between the first width and the second width, the second width and the third width, and the third width and the fourth width.

Since each character contains three blank elements, the blank width comparison is performed twice.

That is, it is a comparison between the first width and the second width, and the second width and the third width.

Five such comparisons are made for each character.

The result of each comparison is that one bar (or blank) is wider than the other bars (or blanks), that the bars (blanks) are about the same width, or that one bar (blank) is wider than the other bars (blanks). That means it's narrow.

A result of "greater than" is a binary number "10", a result of "less than" is a result of a binary number "01", and a "
If the result of "same width" is assigned the binary number "OO", the result of the five comparisons is represented by five pairs of binary numbers, or one 10-bit binary number.

This 10-bit binary number is then easily decoded into any desired binary representation of characters corresponding to the set of bar and blank code elements.

The 10-bit number is used, for example, to address a memory location in a read-only memory containing the corresponding character code.

the first bar or blank is wider than the second bar or blank;
A common mathematical technique used to determine narrow or equal width is to multiply the scan duration of the first bar or blank by a first number greater than one, and then multiply the scan duration of the first bar or blank by a second number less than one. , and then compare the result with the scan duration of the second bar or blank.

If the duration of the first bar or blank multiplied by a constant greater than 1 is still shorter than the duration of the second bar or blank, then the second bar or blank is wider than the first bar or blank. It can be safely estimated that there is.

If the duration of the first bar or blank multiplied by a constant less than 1 is still greater than the duration of the second bar or blank, then the second bar or blank can be narrower than the first bar or blank. It can be estimated using

If neither of the above two criteria are satisfied, the two bars or blanks are assumed to be approximately the same width by default.

The special equipment used to perform the above comparison is
As shown in the figure.

Shift registers 116 are XI, X2, X4, and X8, respectively.
It has four parallel signal outputs named .

These are simply output lines connecting at each output of shift register 116 to the next stage.

First, a binary number representing the width, measured in time, of a bar or blank code element is loaded from counter 114 into shift register 116 .

This number, hereinafter referred to as the "count value", is then immediately advanced through the shift register 116 such that the binary digits comprising the count value are assigned to each signal line XI, X2, X4, X8.
They appear in serial form above.

The same signal is shown on each signal line, but the signals appear with a slight time delay in ascending order of signal line number.

To be more precise, the lowest bit of the count value is first x1
Appears on the signal line.

When the second bit from the bottom of the count value appears on the ×1 signal line, the same lowest bit as before appears again on the ×2 signal line, the second bit from the bottom appears on the ×2 signal line, and the third bit from the bottom is ×
When appearing on one signal line, this lowest bit is ×
4 signal lines; and so on.

From this shift register 116 x1, x2, x4
, x8 signal lines is equivalent to multiplying the count value sent to each line by the number assigned to that line.

So the count value sent to the ×1 signal line is multiplied by 1, ×
The count value sent to the two signal lines is multiplied by two, and so on.

An analogy can help explain why this is so.

Consider the decimal number 9,680. If each digit of this number is 1
If we shift one position to the right and add zeros to the right, this number is effectively multiplied by 10, becoming 9 6,8 0 0.

Since 10 is the base number in the decimal number system, moving a digit to the left is equivalent to multiplying by 10.

By direct analogy, if a binary number moves all of its digits one bit position to the left and a zero is added to the right, the binary number is effectively doubled.

For example 10? Five in number.

The binary number 101, which is equal to , becomes 10 after shifting by 1 bit.
10 in base.

The binary number 10102 is equal to .

It should now be clear that shifting a binary number by one bit position is equivalent to doubling the number.

Shift register 116 effectively shifts the count value sent to successive signal lines Xz, X2, X4, and X8I by one bit position, so that The counted value is multiplied by the indicated constant.

In order to perform a comparison between the first count value and the second count value multiplied by a constant greater than 1 and a constant less than 1, respectively, 5 times, 8 times, and 3 times each count value is calculated.

Then, 5 times the first count value, 8 times the second count value, and 3 times the second count value are compared.

A comparison of 5 times the first count and 8 times the second count is equivalent to a comparison of the first count and 8/5 times the second count, so the first count and A comparison of the second count value I multiplied by a constant greater than 1 equals 1.

Similarly, a comparison of 5 times the fourth count value and 3 times the second count value is equivalent to a comparison of the first count value and 3/5 times the second count value, so the first count value is It is equivalent to comparing the count value and the second count value multiplied by a constant less than 1.

Five times the count value can be easily calculated by adding four times the count value and one time the count value.

The signal line with the name ×4 extending from the shift register serially represents the number obtained by multiplying each calculated value by 4,
Signal lines labeled x1 extending from shift register 116 serially represent numbers equal to each count value.

These two series numbers are processed by a serial adder (or arithmetic unit) 11
8 and the sum is indicated by the output signal of adder 118.

Since this output signal is five times the basic count value, it is named x5.

Similarly, 3 times the base count value can be shifted and
It is calculated by a serial adder (or arithmetic unit) 120 which receives the output signals x1 and x2 from the register 116 and adds them to calculate the signal x3.

We want the width of bars to be compared to the widths of other bars, and the widths of blank spaces to be compared to the widths of other blank spaces.

For this purpose, the width of the first bar and the following blank space measured in time (the corresponding count values are memorized and the count value representing the width of the first bar represents the width of the next bar to appear). It is necessary to be able to compare it with the counted value.

Therefore, the x5 output of adder 118 is sent to shift register 121, which has sufficient capacity to store exactly two times five times the count value represented by counter 114l.

The output of the shift register 121 is a delay x 5 signal (DEL
AYED X5 signal).

When the input shift register 116 represents a count proportional to the length of the bar, the shift register 121 appears to indicate five times the count proportional to the length of the bar most recently scanned. This selects the length of the shift register.

The serial adder (or arithmetic unit) 122 then delays ×5
The difference between the signal line and the binary number represented by the x8 signal line is calculated to determine whether the most recently scanned bar is narrower than the previously scanned bar.

If the number represented by ×8 signal lines is found to be smaller than the number represented by delay ×5 signal lines, adder 12
2 produces a high level output signal called LES (Less Than Signal) indicating a less than qualification.

If the number represented by the x8 signal line is less than or equal to the number represented by the delay x5 signal line, adder 122 provides a low level output signal.

At the same time, another adder or arithmetic unit 124 calculates the difference between the binary numbers represented by the delayed x5 signal and the x3 signal so that the most recently scanned bar is less than the previously scanned bar. Determine whether it is wide or not.

If the number represented by the ×3 signal line is found to be greater than the number represented by the delay ×5 signal line, the adder 124 generates a high signal called the GTR signal (greater signal) indicating that it is determined to be greater. output signal.

Otherwise, adder 124 outputs a low level signal.

In this manner, adders 122 and 124 compare the relative widths of adjacent bars and determine whether the most recently scanned bar is wider than the previously scanned bar according to the previously described binary width code. LES and GTR signals can be generated that can indicate whether the width is the same or the width is narrower.

The relative widths of adjacent spaces can be compared in exactly the same way.

The output signal of adder 122 is sent to shift register 126 and the output of adder 124 is sent to shift register 128.

Shift registers 126 and 128 are long enough to store binary numbers representing the results of all five width comparisons for one character.

Properly decoding these two shift registers (represented 10-bit numbers would be 1,0 0 0
Read-only storage services with more storage locations are required.

For this purpose, a smaller sized read-only storage device 130 having only 128 addressable storage locations is intended for the comparative information decoding of bar and blank codes separately.

BLK signal (black signal) generated from digital input circuit 2
is sent to the address line input of the read-only memory 130 and tells it whether the read-only memory 130 is receiving comparison information equal to the bar or blank width -τ at a given moment.

The outputs of shift registers 126 and 128 are then selected alternately to store the remaining addresses in read-only storage.
Sent to line input.

In this manner, each possible combination of bar and blank width comparison data allows data to be retrieved from a unique location in read-only storage 130.

The alternating outputs of the shift registers are selected such that only bar or blank comparison data is sent to the read-only storage at any given moment.

The four outputs of storage device 130 are sent to bar latch 132.

After bar width comparison data is presented from shift registers 126 and 128, respectively, latch 132 is activated to store the data presented by storage 130.

The presentation of the same BLK signal that signals whether read-only storage 130 is decoding bar or blank information activates latch 132.

The three outputs of storage device 130 are sent to blank latch 134.

After blank width comparison data is presented by shift registers 126 and 128, respectively, latch 134 is activated to store the data indicated by storage 130.

Latch 134 is activated in the absence of the BLK signal, so it stores only the data corresponding to the blank comparison.

In this manner, character bar and blank comparisons are separately decoded and stored in latches 132 and 134 to simultaneously represent one data output 136.

In a preferred embodiment of the invention, read-only storage device 130
compares information about the actual width of each character's bars and spaces.
Easily convert into evolutionary information.

There are four bars in the character, so read-only storage 1
30 interprets the bar comparison information and outputs 4-bit output data.

Since there are only three blank spaces in the character, reading-only storage 130 produces three bits of output data when interpreting the blank comparison information.

As illustrated in FIG. 1, the outputs of the two latches 132 and 134 are combined so that bars and blank code elements of varying intensity occur in the same order as they appear in the scanned character. A blank code appears on the data output 136.

Alternatively, the output may be represented as illustrated in FIG. 5, or in any other suitable manner.

A second read-only memory 138, addressed by the output signals from bar and blank latches 132 and 134, verifies the presence of a particular starting character and also performs parity and other routine error checking on the search data.

Various control and other output signals flow from read-only storage 138 to control logic 140.

Control logic 140 supervises and controls the operation of the entire system and coordinates system operation with the functions of external data storage devices or devices to which retrieved and decrypted data is sent.

Among other functions, the control logic 140 provides a FFT to indicate whether scanning is being performed in a forward or backward direction.
Generates a WD signal (forward signal) and a BWD signal (reverse signal).

In case of an error, the control logic 140 generates an ERM signal (an error signal in the message).

When the end of a message is encountered, the control logic generates an EOMD signal (end of message signal), and also a GDRD signal (good read signal) when the message was entered correctly.

If a valid starting character is first found in a barcoded message, control logic 140 generates a short STARTP pulse signal, then a complete set of characters followed by a second starting character. A START signal is generated continuously until the message is read.

After a message has been read or an error is detected, control logic 140 issues a RES signal (reset signal) to initiate a reset of the entire system 100.

As explained in more detail in the following points, the control logic 1 also sends various error signals indicating the results of various error checks that are automatically performed during any scanning operation.
40 is received as an input signal.

System 100 is designed to send data to some external data storage device (not shown).

The system 100 is controlled by the FRMT signal (control signal) and does not output any output data except when the FRMT signal (control signal) is absent.

Other system signals may also be sent to external data storage or usage devices.

The digital representation of each barcoded character is usually DATAO
It is sent to an external device through a UT signal (data output signal) line 136.

The TAKEDATA signal (also called the JO signal) signals when data is received from the DATAOUT signal line.

TAKEDAT whenever data is received.
The A signal (data reception signal) forms the boundary.

As mentioned above, the DATAOUT signal (data output signal) and TAKEDATA signal (data reception signal) (J
The O signal) is simply a signal that instructs the external device whether to transmit data to or receive data from the external device.

In one aspect of the invention, all valid messages are designed to begin with a specific start code character and end with a specific stop code character.

In the preferred embodiment of the invention, the start and stop code characters are bolts and will always be referred to as start code characters in future sections.

These characters are special characters that can be read in either direction, and in addition to signaling the beginning or end of a message, their specific coding also indicates the direction in which scanning is taking place.

Bar code scanning is designed to begin anywhere in the record, even in the middle of a valid character.

Typically, an employee who is inexperienced in the use of a scanning stylus will simply place the stylus over the barcode using a tapping motion similar to drawing lines on printed matter with a pencil; I swing it back and forth on top of it.

This action may start in the center of the record, or it may start on one side of the record.

The stylus deflection may go all the way across the record to a blank space beyond the record, or it may not deflect much enough to include the start and stop characters at the end of the record.

Stylus deflection may be at an angle such that the stylus briefly leaves the barcode and then re-enters the barcode at another point.

In one aspect of the invention, all false scans are ignored and only valid data is produced when the stylus movement starts on one side of a complete set of characters and continues all the way to the other side in one continuous movement. It is important to be able to receive the following.

To this end, system 100 must first reject all scanned information it receives until it encounters a bar code pattern that corresponds to a valid start or stop code character.

Thereafter, the system 100 remembers exactly where each character begins and ends, and character information is decoded by read-only storage only after the system 100 has scanned a complete pattern from four bars and three blanks. It is necessary to do so.

Counter 142 serves both of these roles.

The counter 142 normally has JO, Jl, J2, J3, J4,
It is an 8-state Johnson counter that counts through eight different states, J5, J6, and J7, and then returns to the initial state JO.

However, when control logic 140 does not issue a START signal, the absence of this signal locks counter 142 in the JO state and prevents counter 142 from advancing.

When counter 142 is in the JO state, it issues a JO output signal and read-only memory 138 registers two latches 1.
Any data stored in 32 and 134 can be received as an address input signal to enable a series of control signals 144 to be issued in succession.

Any of the control signals 144 is connected to the bar and blank latch 13.
2 and 134 represent a code corresponding to a valid start or stop character.

So, when manual scanning of a record is first initiated, data determining the light-dark and dark-light transition patterns encountered on the scanned record is continuously sent to read-only storage 138.

Since control logic 140 is not asserting a START signal at this point, the data output from latches 132 and 134 to data output 136 is simply ignored, regardless of what external device is connected to output 136. It will be done.

Eventually, stylus 102 is drawn past a valid start or stop character.

When the stylus 102 reaches a blank space following such a character, the elements of the system described above latch 132 and 134 binary data representing the width of the bar and blank space in the start or stop character.
to be memorized.

Read-only storage 138 stores codes for valid start or stop code characters.

In response, the read-only storage device sends a control signal 144 to control logic 140.

Logic 140 generates a STARTP pulse, causing the START signal to rise and remain high.

A high level START signal releases the Johnson counter 142 and causes the counter to begin counting fluctuations in the PROCESS signal.

At each instant when the scan progresses from bar to blank (this PROCE
Since the SS signal (process signal) is output, the counter 14
2 begins counting bar-to-blank and blank-to-bar transitions.

Counter 142 resets when it reaches a count of 8, which is equal to the number of bar-to-blank and blank-bar transitions encountered when a character is completely scanned from four bars.

The JO signal then goes high just after the scan reaches the last bar of each character and remains high until just after the scan of the blank space separating adjacent characters occurs.

The end of the JO signal indicates when data representing a complete character is available at data output 136.

When the JO signal is absent, it disables storage 138 and causes storage 138 to be error-prone for the data displayed by latches 132 and 134 when they have data for two different character portions. It prevents checking.

The PROCESS signal changes in value from 0 to 1 C when the stylus detects a transition from a recording blank to a bar.

The PROCESS signal then changes from a value of 1 when the stylus detects a bar-to-blank transition or when the time to scan the bar is longer than a predetermined time, as detailed below. The value changes to O value.

Error checking is performed by various elements shown in FIG.

Digital input circuit 112 measures the duration of each bar and blank scan to ensure that the scan is proceeding at a rate that allows proper operation of system 100.

When a bar or blank code is encountered being scanned too quickly to be processed accurately, circuit 112 sends a UER signal (
too fast error signal) which is sent to control logic 140 to stop scanning.

When scanning is too slow within a character, gate 146 sends an OV signal to counter 114 that has reached a predetermined count, indicating an overflow that can again prevent scanning.
Outputs FL signal (overflow signal).

A counter 148 is connected in series with the most significant output of counter 114 and is configured to measure the total time interval, e.g.
The time it takes to move from one character to the next can be measured.

It is important that the time between characters is limited so that it is not possible for the stylus to be transferred from one row of barcodes to another between characters.

Therefore, when the time between characters is too long, counter 148 provides a TIMO signal that indicates that time is up and can prevent scanning.
Issue a T signal (time-out signal).

The scan is complete when the start (or stop) character of a normal delimiter is encountered.

No other character follows such a character over short distances.

This is because it indicates that the start or stop character was encountered early and indicates that the barcode has been modified slightly.

Therefore, counter 150 measures the time it takes to scan each character.

After encountering the start character of the delimiter, counter 150 is locked by the EOMD signal (end of message signal) generated by control logic 140.

While scanning the blank following the last bar of such character, a comparison gate or circuit 152 compares the output of counter 114 representing the width of the following blank with the output of counter 114 representing the width of the last starting character. The output of the device 150 is compared.

If the trailing blank is greater than or equal to some multiple of the last starting character, comparison gate 152 issues a MATCH signal (match signal) to tell control logic 140 that there is a suitably long blank following the last starting character.

In a preferred embodiment of the invention, the blank following the last bar before the MAT CH signal is at least Q.
Q: It must be 7 inches (1.8mm) wide.

The system does not honor the first starting character that is not immediately followed by another character.

The same mechanism used to detect slow scanning is also used to measure the time it takes to scan the white space following the first starting character.

If the white space is unusually wide, the starting character will be rejected.

Scanning motions proceeding outward from the center of the barcode area are then ignored.

Only scanning movements starting at the edge of the record are valid.

An unskilled operator can then begin a zigzag scanning motion from any point on the record, and the system will capture data from every such motion over the complete barcode from one end of the record to the other.

In a preferred embodiment of the invention, complementary symmetry (comp
It is constructed using a metal monoxide film and a semiconductor integrated circuit.

Especially R. of Somerville, New Jersey. C. A. COS-MOSJ(TM) integrated circuits manufactured by Solid State Physics Division of Co., Ltd. are used in the fabrication of the preferred embodiment.

Below is a brief description of the integrated circuit used.

COS-MOS Model number Simple “theory” 4001 2-person NOR gate 4006 16-stage shift register 4007 NOT or negation gate 4011 2-person NAND gate 4012 4-person NAND gate 4013 rDJ type flip-flop 4015
4-stage shift register with serial and parallel inputs and outputs 4017 10-stage decimal counter (sequential) 4021
8-stage parallel input, serial output shift register 4022 8-stage Johnson counter 4023 3-man NAND gate 4025 3-man power NOR gate 4030 Exclusive-OR gate 4032 Serial adder 4040 12-stage binary counter 4042 Latch 4049 Inverter Conventional integrated circuit logic symbols are used throughout the detailed description that follows.

More specifically, a D-type gate indicates an AND logic circuit, and a gate having an output f of such a gate indicates a NAND logic circuit.

An arrow-shaped gate indicates an OR logic circuit, and a circle at the output of such a gate indicates a NOR logic circuit.

A triangular gate with an output f circle is NOT
Shows the circuit.

The vertical rectangular box with the letter Q or Q on the output is typically a D-type flip-flop with the following characteristics:

That is, if the flip-flop's D input is high when the C input changes from low to high, the flip-flop will immediately start producing a high level Q output signal and a low level Q output signal, causing the C input to change from low to high. If the D input is low when going high, the Q output will immediately go low, and the Q output will immediately go high.

The Q output of such a flip-flop is set high by applying a high level signal to the S or reset input of the flip-flop, and set low by applying a high level signal to the R or reset input of the flip-flop. It can be done.

In any case, the Q output signal is always the negation of the Q output signal.

In some cases, shift register devices are also shown having D input terminals, C input terminals, and so on.

Such a shift register is understood to be a shift register or equivalent consisting of a series of D-type flip-flops connected in series to form a shift register.

A gate that resembles an arrow-shaped NOR gate but has an extra curve on its left edge is an exclusive OR (EXOR) gate.

Although complementary symmetrical metal monoxide-semiconductor integrated circuits are used in the construction of the preferred embodiment of the invention, any suitable type of integration or separate logic may be used to perform the functions of the invention. Also good.

In the figure, the inverted signal is clearly indicated by an overline.

Signals without an overline indicate "when the signal is high or at a positive power level.
"present" and "absent" when the signal is at a low or negative level.

The overlined signal is "present" when the signal is low or at a negative level, and "absent" when the signal is high or at a positive level.

Since the nature of each signal (inverted and non-inverted) is clearly shown in the figures, whether the signal is inverted or not will not generally be discussed in the following text.

Signals are simply stated as ``present'' or ``absent,'' and the actual polarity of the signal is determined with reference to the diagram.

Since the function of the negation gate is clear from the diagram, the negation gate, which only performs the role of converting a non-inverted signal into an inverted signal and vice versa, will not be particularly mentioned in the following description.

As a whole, logic gates have a gating (AND) logic function, a signal passing (OR) logic function, and an inversion (NOT, EX) logic function.
OR) performs a logical function or a combination of these functions.

In the case of an OR gate that simply passes all input signals as output,
"pass through" and usually does not include further discussion of gate operations.

In the case of an AND gate that performs a gating or signal control function, the gate is said to be "disabled" when certain signals are prevented from proceeding through the gate.

A gate is "enabled" if a signal can pass through it
It is said.

A gate is said to be "partially enabled" if it has more than one input signal and some, but not all, of the input signals cause the gate to pass through.

FIG. 2 shows a digital input circuit 112, a clock 115,
2 is a logic diagram illustrating details of a timing signal counter 113. FIG.

As previously mentioned, clock 115 is a simple pulse generating clock that generates a train of CA pulses and simultaneously generates a train of CB pulses interspersed between the CA pulses.

The pulse generating portion of clock 115 is derived from a pair of NAND gates 202 whose output terminals pass through a simple R-C time delay network 203 back to its input to form a very simple oscillator. ing.

The output signal of gate 202 has a square wave shape that inverts each time a capacitor in R-C network 203 charges or discharges where the input of gate 202 rises or falls below its normal switching threshold level. are doing.

The gate 204 squares this rectangular wave shape and converts it into a first
input to the clock input of the D-type flip-flop 206.

Flip-flop 206 couples its Q output to its D input, and in response to each pulse received from gate 204, the flip-flop changes state.

The Q output of flip-flop 206 is connected to the second flip-flop
It is connected to the clock input of flop 208, which also has an inverted Q output tied to its D input.

The two flip-flops 206 and 208 successively
We form a simple two-stage binary counter that goes through two sequential stages and then resets.

During one of these states, gate 210 receives all high level inputs and generates an output pulse CA.

During another one of these states, gate 212 receives all high level inputs and generates an output pulse CB.

Gates 210 and 212 are connected to two flip-flops such that pulses CA and CB alternate and are separated by a small delay time from each other.

The frequency of CA pulse is 200,000 pulses per second,
The same applies to the frequency of the CB pulse.

Digital input circuit 112 occupies the lower left portion of FIG.

The ANALOG signal sent by analog input circuit 110 is applied to the D input of flip-flop 214.

The CB timing pulse is sent to the clock input of flip-flop 214.

When the ANALOG signal goes high in response to the scanning of the bar element, the next CB pulse sets flip-flop 214, and the Q of flip-flop 214 increases.
The output (ie, BLK signal, black signal) causes flip-flop 216 to be set.

The inverted Q output signal of flip-flop 216 is
PRO passes through 18 and becomes the signal for scanning the blank one bar transition.
This becomes a CESS pulse signal.

The duration of the PROCESS pulse signal is determined by how long flip-flop 216 can remain set.

As explained below, this is determined by flip-flop 220, which clears flip-flop 216 after a predetermined delay time.

The flip-flop is then reset with a CA pulse.

When the ANALOG signal goes low, the next CB pulse clears flip-flop 214 and sets flip-flop 222 to the flip-flop's inverted output.

The output of flip-flop 222 then also passes through gate 218 and PRO signals the scanning of the bar-to-blank transition.
CESS pulse (process pulse) tonal.

After a short delay time, flip-flop 222 is cleared in flip-flop 220, similar to the way flip-flop 216 was cleared.

The digital input circuit thus generates a short duration PROCESS pulse at the output of gate 218 to correspond to each swing of the ANALOG signal.

The Q output of flip-flop 214 is called the BLK signal and indicates which bars or blanks are being scanned.

If the movement of the scanning stylus is so fast that a narrow bar or blank space is scanned too quickly for the logic circuit to respond, the ANALOG signal will fail before one of flip-flops 216 or 222 is cleared. (analog signal) makes the second swing.

This also happens when a thin mark on the record is mistaken for a very narrow bar.

This second swing of the ANALOG signal also sets the other of the two flip-flops 216 and 222, thus setting both flip-flops.

The Q output from each of the two flip-flops then enables gate 224 to generate the UER signal (too fast error signal).

This UER signal (too fast error signal) is transmitted to the control logic 140.
and it responds with a scan abort.

Normally the two flip-flops 216 and 222 are never set at the same time, so the UER signal (overspeed error signal) is never generated.

Timing signal counter 113 occupies the central portion of FIG.

A J-counter 142 is visible at the bottom of FIG.

Both of these counters are controlled by a PROCESS pulse generated at the output of gate 218.

The timing signal counter 113 receives the PROCESS signal (
It consists of a series of counting stages 226, 228, 230 that count from zero to 29 whenever a process signal (process signal) is present.

The 29th count of the timing signal counter is the flip
is sent back to the C input of flip 220, and its flip
Reset the flop, thereby terminating the PROCESS signal.

When the PROCESS signal is not present, the output of gate 218 is high and counter stages 226,
228, 230 in their cleared or reset state.

Each time a PROCESS pulse occurs, the output of gate 218 falls, allowing the timing signal counter to count from 0 to 29.

Counter stage 226 is a conventional decimal counter stage with ten independent outputs of progressively higher values.

These outputs are Do, DI, D2,...
It is named D9.

The most significant input is sent to the C (clock) input of counter stage 228.

Counter stage 228 is a simple flip-flop with the inverted Q output connected back to its D input.

As counter stage 226 advances from count D9 to count DO,
Counter stage 228 is set and causes that stage to generate a DIO output signal.

Counter stage 226 then takes a second count.

When the counter stage 226 again advances from count D9 to DO,
It issues an output pulse that clears step 228, thus terminating the DIO output signal.

Stage 228 now sets a similar flip-flop counter stage 230, which generates the D20 output signal.

Counter stage 226 then counts from DO to D9 again with the D20 output signal present, counting from 20 to 29.
Shows up to.

When the count D9 reaches again, the D20 signal and the D9B signal (
D9), strobed with the CB pulse, combine to generate the 29B signal on gate 232, toggling flip-flop 220 and terminating the PROCESS signal.

Then flip-flop 220 immediately clocks 1
It is cleared on the next CA pulse generated at 15.

The output signals produced by counter stages 226, 228, and 230 can be combined as desired to obtain a desired continuous timing signal lasting a desired number of CA or CB clock pulses.

The gate shown on the right half of FIG. 2 simply combines the timing signal counter output and the CA and CB timing pulses to generate the timing signals necessary for control of system operation.

For example, gates 234, 236, 238, and 240 cause selected outputs of counter stage 226 to be strobed with clock output pulses such that the CB clock output pulses at three selected counts during the timing interval 0 to 29. to occur.

These pulses are named DIB, D2B, D7B, D9B.

Only when the counter 228 is set, the pair of gates 242 and 244 will pass pulses D7B and D9B between the 17th and 19th counts of the timing signal counter.
Pulses 17B and 19B are synchronized with the CB clock pulse.
occurs.

The gate 246 is sensitive when the two timing clock stages 228 and 230 are both cleared, and the timing signal counter 1 and 2 counts, and only then the pair of gates 248 and 250. is usable and D
Passes IB and D2B timing pulses.

Gates 252,2 only when counting stage 230 is set.
54, 256, 232 are pulses DIB, D2B, D7B
, D9B, thereby sending the CB timing pulse only during the 21st, 22nd, 27th, and 29th counts of the timing signal counter, respectively.

Signal IB, 2B, 17B, 19B, 21B, 22B, 2
7B and 29B are pulse signals that occur when the timing signal counter reaches the corresponding count value, in lockstep with the CCB clock signal.

Bistable multivibrator 258 is set with a 1B timing pulse and then cleared with a 17B timing pulse.

So this bistable multi-bi break 258 is accurate &c
A high level input signal L that surrounds the 16 CA clock pulses and begins and ends synchronously with the CB clock pulses.
Generates DI6A.

The LD16A signal enables gate 260 and turns exactly 1
6 CA clock pulses on signal line CLK16A
, which is used to control the movement of 16-bit numbers through shift registers and the like in the system's arithmetic units.

The LDi5A signal is also sent to the D input of flip-flop 262 which is strobed with the CA clock pulse.

Surrounding exactly 16 CA clock pulses, CA
The output of flip-flop 262, which begins and ends synchronously with the clock pulses, appears on LD16B.

This LD16B signal enables gate 264 to send exactly 16 CB timing pulses to CLKl6B.
Used for passing signal lines.

The CLK16B signal is also used for shift registers, arithmetic units,
Used to control the operation of other similar items.

Johnson counter 142 is visible at the bottom of FIG.

This counter is simply PRO, which appears at the output of gate 218.
Calculate the number of CESS pulses (process pulses).

Inverted STA being sent to the reset input of counter 142
Due to the lack of RT signal (inversion start signal), counter 14
2 is initially locked in the reset state while generating the signal JO.

When an inverted START signal is present, counter 142 is free to count from JO to J7 and back to JO, advanced by the trailing edge of each PROCESS pulse.

The signal JO always reappears shortly after the scan begins to traverse the last bar of each character on the record.

FIG. 3 is a logic diagram showing the elements of bar and blank width counter 114, shift register 116, counter 150, comparison logic 152, and control logic 140 that generates the EOMD signal (end of message signal).

These elements of FIG. 3 are detailed below in the order shown, with the exception of the logic circuitry that generates the EOMD signal (end of message signal).

The latter logic circuit will be described later.

Counter 114 is a 12-bit counter with a capacity of 12 bits.

The 12 outputs of counter 114 are transferred to shift register 116.
12 inputs.

Shift register 116 includes two integrated circuit shift registers 302 and 304 and shift register stage 304.
A pair of flip-flops 3 connected in series with the output of
It consists of a 1-bit shift register stage constructed from 06 and 308.

Counter 114 and shift register 116 are controlled by a timing signal generated by a timing signal counter.

Immediately after the level transition of the ANALOG signal caused by scanning from bar to blank or vice versa, the digital input circuit generates a PROCESS pulse lasting 29 timing signal counts. .

When the timing signal counter counts 1, the 1B timing signal sends the contents of counter 114 to shift register 116.

Almost simultaneously, the D1 timing signal is applied to flip-flop 3.
Set to 10 to disable gate 312 and prevent any CB timing pulses from passing to the input of counter 114. At count 2, the 2B pulse clears counter 114.

At count 3, the D3 pulse clears flip-flop 310, enabling gate 312 and passing the CB pulse to the counter circuit of counter 114.

The counter is then reset and begins counting CB pulses to measure the width of the next bar or blank.

The count representing the width of the preceding bar or blank is now shifted/
It is stored in register 116.

Starting from timing signal count 2, 16 CB clock pulses are sent to the shift input of shift register 116, causing a serial representation of the stored count value therein.

For an extra shift register stage consisting of flip-flops 306 and 308, 16 CA pulses are sent to flip-flop 306 and 16 CB pulses are sent to flip-flop 306.
A pulse is sent to flip-flop 308.

As explained earlier, the count value is calculated by the signal lines x1 and x2.
, x4, x8.

As explained in the punishment section, the counted value is effectively multiplied by the indicated number.

When counter 114 reaches a predetermined high level count, gate 1 is activated to signal that a particular count has been exceeded.
46 generates an OVFL signal (overflow signal).

The OVFL signal (overflow signal) is used to signal when a bar or blank element is too long or scanned too slowly, and is also used to signal when the blank space after the starting character is too wide.

The highest output C12 of the counter 114 is the second counter 14
8 counting inputs are sent.

The clock counter 148 that reaches various count values outputs an output signal T40.
, T1 0 , generates a TIMOT signal (time-out signal).

In fact, counter 148 is simply an extension of counter 114 to allow it to measure long time intervals.

For example, the TIMOT signal occurs only when the stylus takes too long to move from one character to the next.

In a preferred embodiment of the invention, TIMOT
The counts are chosen to measure time intervals of approximately 0.5 seconds.

From one character to the next, the scan must proceed within that time or it is aborted.

The TIMOT signal prevents the stylus from moving from one bar code to an adjacent bar code mid-scan.

A fourteen stage counter 150 (FIG. 3) ensures that a long blank follows the last bar of the message.

While scanning the spaces between characters, counter 150
It is reset with 1 signal.

Counter J1 then registers CA while the character is being scanned.
The pulses are counted to determine the approximate time required to manually scan each character.

After scanning the final starting character, the EOMD signal (end of message signal) prevents the CA pulse from flowing through gate 320 to counter 150, so that in effect
Locks a count approximately equal to the time it took to scan the last starting character during the process.

Comparison circuit 152 then compares the count stored in counter 150 with the count shown in counter 114E, which increases as the blank space after the last or stop character is scanned.

If the blank is long enough, the two counts will eventually become equal, and a MATCH signal will be sent to the comparator circuit 152.
Let it come out.

The MATCH signal and the EOME signal then generate a GDRD signal (good read signal) at gate 324, which means the scan was successful.

However, if the space following the last or stop character is too short, the MATCH signal (match signal) and the GDRD signal (
Good read signal) does not occur.

FIG. 4 receives the output signal from the shift register 116,
FIG. 3 is a logic diagram of the arithmetic logic that performs the various width comparison operations described above.

The x1 and x2 output signals of shift register 116 are fed into serial adder 120, which generates a x3 output signal.

The x1 and x4 signals are fed into adder 118, which generates the x5 signal.

The x5 signal is then sent from the serially connected first and second 16-bit stages 402 and 404 through a shift register 121 driven by 16 CLK16B pulses.

Arithmetic units 118 and 120 also perform 16 CLs during each calculation.
Activated by K16B pulse.

The delayed x5 signal from shift register 121 is sent to arithmetic units 122 and 124 along with the x3 signal from arithmetic unit 120 and the x8 signal from shift register 116.

The computing devices 118, 120, 122, 124 are the devices 12
2 and 124 are programmed to calculate the difference between the input signals of the 122 and 124 devices and produce a GTR signal (greater signal) and an LES signal (lesser signal) representing the desired comparison result.

After a typical calculation, the outputs of arithmetic units 122 and 124 may be low level signals to represent a positive or zero result;
It becomes a high level signal to represent a negative result.

In either case, the output signal of the arithmetic unit represents the most significant bit of the result.

Since negative results are necessarily represented in complementary form, this bit is necessarily high when the result is negative.

Unless the number is too large to handle properly, the most significant bit of a positive number is always a zero bit, so this bit is always low when the result is a positive number.

Arithmetic units 122 and 124 are activated with 16 CB pulses as indicated by the CLKI6B signal line.

The logic shown in the bottom half of FIG. 4 detects sudden changes in scan speed and aborts the scan when such a change is detected.

Adder 406 and shift register 410 sum the bar and blank widths of each character.

The resulting sum CHWDTH (t character width) appears at the output of adder 406 during the beginning of the intercharacter time interval JO and is loaded into two shift registers 408 and 414 at that time.

This sum is a standard measure of the time required to scan a complete character.

Shift register 410 is cleared during the following J1 time interval, and adder 406 and shift register begin measuring the time required to scan the next character in the same manner.

After the next character is scanned, a number appears at the output of adder 406 that is proportional to the time it took to scan that character.

A pair of adders 418 and 420 calculates the difference between this number and a number representing twice the time taken to scan the previously scanned character divided by two.

Shift register 408 includes an extra seventeenth stage that effectively doubles its contents.

Shift register 414 receives an extra data advance pulse in the form of a 21B timing pulse, which effectively divides the contents of the shift register by two.

When the 21B pulse occurs, the D20 count signal is output to the gate 41.
6 is disabled and the value zero is loaded into the shift register at that time.

If the current character scan takes more than twice as long as the previous scan, adder 418 provides an inverted ACCERi signal (inverted acceleration 1 signal).

If the current character scan takes less than half the time as the previous scan, adder 420 provides an EACCER2 signal.

Both of these signals cause the control logic to abort the scan, as explained more fully below.

FIG. 7 shows a time chart when three barcode characters are scanned, and FIG. 7A shows a time chart in which a portion of FIG. 7 is enlarged.

In FIG. 7, the signal ANALOG obtained from analog input circuit 110 is shaped by digital input circuit 112 to generate the BLK signal.

This digital input circuit 112 outputs a PROCESS signal of a constant width each time the BLK signal is inverted, as shown in FIG. 2 and related explanation.

This PROCESS signal is transmitted to the timing signal counter 113.
In addition to being input to the Johnson counter 142,
The JO signal, which indicates a counter zero condition, is brought low and the J1 signal, which indicates a count of one, is generated, and this J1 signal remains high until the next PROCESS signal arrives.

When the next PROCESS signal is input, the count becomes 2 and the J1 signal becomes low level, and the counter 142 counts every time the PROCESS signal arrives thereafter, and the 8 PROCESS signals are counted.
J, which was at a low level and became zero again due to the SS signal.
o Set the signal to high level.

As shown, the barcode characters are drawn from four black bars and three spaces between them, so the BLK signal rotates eight times between one character, so when the Jo signal is in a low level state, It represents the spacing between one character.

As described above with reference to FIG. 2, the PROCESS signal is also input to the timing signal counter 113, which makes the PROCESS signal a pulse of a predetermined width.

Clock 1 that pulses continuously at 20 KHz
Fifteen CB (or CA) pulses are input to the clock terminal of counter 226 to provide CB (or CA) pulse sequencing.

When the 29th CB pulse arrives from the rising edge of the PROCESS signal, flip-flop 220 is set and flip-flop 216 is reset.

Therefore, the PROCESS signal becomes a pulse with a predetermined width, regardless of the width of the BLK signal.

This situation is shown in more detail in FIG. 7A.

Timing signal counter 113 to 6i, one PROC
The CB pulses between the ESS signals are input to a group of gates that sequence them, where signals such as IB, 2B, 17B...29B are created.

The bistable multivibrator 258 has a 1B signal and a 17B signal.
The output (LD16A) is input to the data terminal D of the flip-flop 262.

This flip-flop 262 is clocked by the CA pulse and outputs the LD15B pulse.

This LDi5B pulse rises with the rise of 1B,
This becomes a pulse that falls with the rise of 17B (FIG. 7A).

This LD15B pulse opens gate 264,
Pass 16 CB pulses to create CLK16B pulses.

That is, the CLK16B pulse is a signal that occurs at the beginning of each PROCESS signal and includes 16 CB pulses, as shown in detail in FIG. 7A.

We believe that the above explanation has clarified the timing of each signal important to the device.

FIG. 5 shows two shift registers 126 and 128, a read-only memory 130, latches 132 and 134, and a second read-only memory 138.

The GTR signal (greater signal) and the LES signal (lesser signal) representing the result of the width comparison are fed into the inputs of shift registers 126 and 128, each of which has an extra shift register stage. It consists of a 4-bit shift register with the addition of a flip-flop.

The data bits are shifted by the green after LD15B signal produced by flip-flop 262 (FIG. 2).
Loaded into registers 126 and 128.

This trailing edge occurs immediately following the occurrence of 16 clock signals from the computing subsystem.

Shift registers 126 and 128 are now loaded with the last two bits represented by two arithmetic units 122 and 124.

As already explained, it is created by a digital input circuit,
BLK indicating whether the bar or blank is currently being scanned
Two shift registers 126 along with a signal (black signal)
and 128 are alternately sent to the input of read-only storage 130.

Read-only storage 130 has eight output terminals, four of which are sent to bar latch 132, three to blank latch 134, and one that is not used.

Latches 132 and 134 are loaded synchronously with clock signal 19B.

When signal 19B occurs, read-only storage 130 represents at its output the data addressed by shift registers 126 and 128.

The latch 132 is activated only when the BLK signal (black signal) is present.
is activated with 19B pulses.

The 19B pulse is allowed to pass through gate 136' to strobe latch 132 with the inverted BLK signal enabling gate 13ff to pass the 19B pulse.

Without the BLK signal, its absence allows the 19B pulse to pass through the alternate gate 1381 and strobe data into the blank latch 134.

In this way, bar latch 132 is loaded with data from read-only storage 130 after each bar code is scanned, and blank latch 1 is loaded after each blank code is scanned.
34 is loaded with data from read-only storage 130.

Read-only storage 130 stores data in its addressable storage locations that corresponds exactly to the most recently scanned wide and narrow pattern of bars or blanks.

The data captured by latches 132 and 134 is represented as the data output of the system.

This data may or may not be meaningful depending on the state of the counter 142.

Once the counting JO is complete, assuming the character is being scanned and the counter 142 is running, the data captured actually represents the width of the bar and blank elements of the character.

When the captured data is sampled, a signal JO is sent to signal the external data utilization device.

Read-only storage 138 is only functional when signal JQ is present.

When so available, read-only storage 138 receives the data captured in two latches 132 and 134 as an address code.

Read-only storage 138 then represents the contents of the memory location indicating the nature of the "character" just scanned.

The output of read-only storage 138 is a plurality of control signals 144 that equate start and stop characters and select characters with polarity or other errors.

It is anticipated that the preferred embodiment of the invention will be used in at least two different applications with two different code configurations.

The first code configuration is primarily intended for use in retail applications, such as grocery stores and department stores, and the second code configuration is intended for use in warehouses, parcel override scanning, and the like. is intended for use.

Read-only storage 138 is designed to generate control signals for either of these two applications, and is therefore suitable for use with either code configuration.

The control signal STF-RU signal (start character forward read signal) signals the forward reading of the barcode start character.

The control signal STB-RU signal (start character backward read signal) signals backward reading of the barcode start character.

If the start character is a retail code start character, the control signal STF+STB-R (retail code start character signal) is asserted.

If the start character is a non-retail code start character, the signal STF
+STB-R (retail code start character signal) does not appear.

In response to any type of start code, whether forward or backward reading, an STF+STB-RU signal (start code signal) is generated.

The remaining two control signals indicate errors.

If you encounter an error in the retail code character, CATERR
An ET signal (error signal in retail code letter) appears.

If an error is encountered in a coded character using another type of code, a CATER UPC signal (error signal for non-retail coded characters) will appear.

Of course, read-only storage 138 does not know what type of code is currently in use.

The storage device generates control signals according to each character and how it is interpreted.

Other logic elements of the system control logic (FIG. 6) determine exactly what actions occur in response to the various combinations of control signals that may occur.

The lower portions of FIGS. 6 and 3 illustrate the details of control logic 140 that controls the overall operation of system 100.

This control logic is detailed below.

After the scanning operation is completed, the entire system is reset by the RES signal (system reset signal) generated by gate 602 (far right corner of FIG. 6).

This signal resets all of the system's counters and control circuits, particularly the flip-flop shown at the top of FIG.

This terminates the flow of the START signal from gate 616, which is connected to the inverting outputs of flip-flops 610 and 612.

The system now enters a search mode of operation while searching for a valid starting character.

Counter 142 (FIGS. 1 and 2) is locked in the reset state due to the lack of a START signal on its reset input, and counter 142 continuously outputs its JO output signal. Put it out.

As this JO output signal continues to be present, it causes the read-only storage device to continuously scan the captured data as indicated by latches 132 and 134.

When the latch is capturing data corresponding to a start code, read-only storage 138 generates the STF+STB-RU signal (start code signal) and sends this signal to gate 604 at the top left of FIG.

After the system is reset by the FEB signal (four black bar signals) produced by the simple shift register 606, the gate 604 is disabled before the fourth black bar scan.

Furthermore, after a blank scan by the BLK signal being sent to gate 604 through gate 608, gate 604 is prevented from responding.

Gate 604 is periodically strobed with timing signal 22B coming from a timing signal counter.

The output of gate 604 is a STARTP signal (start pulse signal) pulse.

To summarize briefly, due to the presence of the RES signal (System Reset Signal), when a valid start code combination containing four bars and three spaces between them is encountered and all of them have been scanned, the STARTP signal (Start Pulse Signal) is detected. ) a pulse is created.

The trailing edge of the STARTP signal Hals is sent to the clock inputs of flip-flops 610, 612 and 614.

If the start character just encountered is a forward start code, read-only storage 138 stores the control signal STF-RU signal (
Start character forward read signal), which causes flip-flop 610 to begin generating the FWD signal (forward signal).

If the start character just encountered is a reverse start code, read-only storage 138 stores the control signal STB-RU signal (
Start Character Backward Read signal), which causes flip-flop 612 to begin generating a BWD signal (backward signal).

Usually only one of these flip-flops is set.

If the opening code is a retail code start character, read-only storage 138 issues an STF+STB-R signal (retail code start character signal), which causes flip-flop 614 to generate a STARTRET signal (retail start character signal). Let it start.

When either flip-flop 610 or 612 is set, its inverted output passes through gate 616 to ST
This becomes the ART signal (start signal).

If flip-flop 614 is set again,
Gate 618 is disabled and the STARTUPC signal (
non-retail start character signal) cannot be generated.

The absence of this signal indicates that the start character is a retail start character.

If flip-flop 614 is not set, gate 618 is disabled, and a START UPC signal (non-retail start character signal) is generated to indicate that the start character is not a retail start character.

The function of shift register 606 deserves a brief explanation.

Before scanning the four black bars, latches 132 and 134 may contain some meaningless data, so gate 604 is activated to search for a valid starting character until at least four bars have been scanned. It is not desirable to attach it to the operation of

The 4-bit shift register 606 is reset by the RES signal (system reset signal) at the beginning of each scan period.

The D input to this shift register connects to the positive node,
The BLK signal (
The shift register is strobed each time the black signal) goes high.

The shift register was initially loaded with the "O" bit by the RES signal (system reset signal).

After four positive swings of the inverted BLK signal (inverted black signal),
The Q4 output of shift register 606 goes high and FBB
A signal (four black bars) is generated that causes gate 604 to begin searching for the start code.

The START signal generated by gate 618 is sent back to counter 142 shown in FIG. 2 to release the counter.

Counter 142 then begins counting the bars and blanks of each character.

Counter 142 except immediately after each character is completely scanned.
The JO output of in turn disables read-only storage 138.

In this manner, read-only storage 138 prevents the width of one bar of a first character and the width of another bar of subsequent characters from being interpreted as valid or non-valid characters.

If the bars represent valid characters, the system functions in a scan mode during which it examines each connected set of four bars that it sees.

Valid character testing is performed by a pair of gates 620 and 622 shown in the center of FIG.

- When the %reto sell code is scanned, START
The UPC signal (non-retail start character signal) enables gate 620, and when a retail code is being scanned, the START RET signal (retail start character signal) enables gate 622.

The output control signal, the CATER RET signal (error signal on the retail code letter), is sent to gate 622 and the non-retail error output control signal, the CATER UPC signal (error signal on the non-retail code letter), is sent to gate 620.

When a retail code is scanned and a retail code error occurs, gate 622 provides an output signal.

If a non-retail code is being scanned and a non-retail code error occurs, gate 620 provides an output signal.

Both of these output signals pass through gate 624 and are strobed through gate 626 in synchronization with timing signal count-i/L's 21B.

The resulting pulse passes through gate 628 and strobes error flip-flop 630.

Flip-flop 630 then issues an ERM signal (an error signal in the message) to inform the external data utilization device that an error has been encountered.

The inverted output of flip-flop 630 passes through gate 632 and sets flip-flop 634.

Then, the output signal from the flip-flop becomes the RES signal (
Gate 636 is enabled so that the system reset signal (system reset signal) line can be reached to reset the system.

So if any error is encountered in the message, the system will be reset immediately.

Then flip-flop 634 is set to 1B timing.
Reset by clock pulse.

The system now returns again to the exploration mode of operation described above.

Flip until another valid starting character is encountered.
Flop 630 is set and at that time flip-flop 630 is cleared by a START P signal pulse.

Assuming that the scan proceeds normally without encountering any errors, the end of the scan is detected by the logic shown at the bottom of FIG.

If a second starting character is encountered in the message, read-only storage 138 again outputs the output signal STF+STB.
-Generates the RU signal (start code signal).

This signal, in combination with the continuing high START signal, causes gate 326 to send a high signal to the D input of flip-flop 328.

Flip-flop 328 is then strobed with the next subsequent 22B timing pulse and begins to issue an EOMD signal (end of message signal).

Gate 3 is activated by the EOMD signal (end of message signal).
30 is enabled and passes one 29B timing pulse to the signal line labeled EOMD-29B.

This signal pulse is sent through gate 632 in FIG. 6 to set flip-flop 634 and initiate a system reset, as previously described.

After the last bar of the last starting character is scanned, the EOMD signal (
The lack of an end-of-message signal prevents the CA clock pulse from flowing through gate 320 to counter 150, and the process described above is performed while the width of the blank space following the final start character is compared to the width of the start character itself. Start.

If the space is too narrow, this indicates that the last intended starting character was followed by another character, causing an error.

In that case, no GDRD signal (read good signal) pulse is generated.

If the blank is wide enough, a GDRD pulse (good read pulse) is generated.

The GDRD pulse (good read pulse) sets flip-flop 332.

The inverted output of flip-flop 332 is connected to the CB clock.
The pulse passes through gate 334 and clears flip-flop 328 which generates the EOMD signal (end of message signal), thereby disabling gate 324 and allowing the GDRD pulse (good read pulse) to terminate.

Flip-flop 332 remains set until the next valid start character is encountered, at which time it is cleared by the START signal.

In the absence of a GDRD pulse (good read pulse), flip-flop 332 is set by the next occurring 1B timing pulse, and its inverted output is caused by the CB pulse clearing flip-flop 328 and the EOMD signal (end of message signal). allows you to exit.

The failure of the GDRD pulse (good read pulse) to occur during the brief period during which the EOMD signal (end of message signal) is present signals an improperly narrow space following the final starting character.

At the starting point of a valid scan after encountering the first starting character,
It is inappropriate to immediately encounter a second starting character.

Therefore, whenever a start character of any type is scanned, the control signal STF+STB-RU signal (start code signal) is first passed through gates 646, 624, and 626 to the error reset logic. pull the trigger.

Before encountering the first starting letter, flip-flop 63
Since there is no START signal at the D input of 0, the error reset logic is disabled.

Only after gate 626 has been synchronized by timing signal 21B, gate 604 is strobed to issue a START signal by timing signal 22B.

So the error signal sent at gate 642 when the first start code is encountered reaches flip-flop 630 when the START signal is still missing;
Flip-flop 630 cannot respond to error signals.

After encountering the first start code, the appearance of a bar pattern similar to the start code sends an error signal to gates 642, 624.
, 626, 628.

Since the START signal is present, this error signal sets flip-flop 630.

Then an ERM signal (error signal in the message) occurs,
The system resets itself to scan mode.

After six characters have been scanned, the gate is disabled by the MIN signal (scanning signal for the minimum number of characters).

Flip-flop 638 and shift register 640 are both initially cleared.

The J1 signal repeatedly toggles flip-flop 638 when a valid character scan begins.

All other toggles are sent to shift register 640 as shift pulses that load a "1" data bit into the shift register from the +12 volt voltage source.

Gate 64 after the 6th barcode character is scanned
2 is prohibited from use.

"1" data bits continue to flow through shift register 640, so gate 642 remains disabled for the remainder of the scan.

Starting characters encountered after the seventh character of the message cannot cause an error reset action.

This circuit also detects the condition when the stylus is lowered into the middle of a pattern of all zeros that sometimes resembles a series of consecutive start codes.

The time required to scan the spaces between characters is measured by a counter 114.
is measured by counter 148, which is simply an extension of .

If the blank scanning between characters continues for more than 1/2 second, the TIMOT signal (time-out signal) generated by the counter 148
sets flip-flop 648 and OVFLER
Issues a signal (overflow error signal) and starts error reset operation.

The time required to scan a valid bar or blank element is measured by counter 114.

If scanning is done too slowly, gate 14
6 provides an OVFL signal (overflow signal), which flows through gate 652 and flip-flop 6
48 and start error reset operation.

J1 is inverted at gate 650 to disable flip-flop 648 from responding to the OVFL signal (overflow signal) while scanning spaces between characters.
During this time, the OVFL signal (overflow signal) is normally prevented from setting flip-flop 648.

However, while scanning the blank following the first starting character, there is a lack of an available Q1 signal, so gate 65
0 is prevented from passing the J1 signal.

So the first starting character must also be placed near the next succeeding character.

Thus, for practical purposes, it is impossible to scan from a starting character to an adjacent blank space without incurring an error reset operation.

A counter 150 that measures the width of the blank space following the last scanned character.
is also used to measure the width of each character.

If the character is too slow or contains too many wide segments, counter 150 issues signal CHl4, which flows through gates 644, 646, 624, 626 to initiate an error reset operation.

While scanning spaces between characters, the counter 150 is normally reset by the J1 signal that keeps the counter 150 reset.
0 is disabled.

After the final start or stop character is scanned, the J1 terminal is no longer able to reset counter 150 because Johnson counter 142 is locked in the JO state by the absence of an inverted START signal at its reset terminal.

So, as previously mentioned, counter 150 can indicate the width of the last character scanned.

Although preferred embodiments of the invention have been described, it will be apparent to those skilled in the art that numerous modifications and changes can be made without departing from the scope of the invention.

[Brief explanation of the drawing]

1 is a block diagram of a scanning system designed in accordance with the present invention. FIG. 2 is a logic diagram of digital input circuit 112, system clock 115, and timing signal counter 113. FIG. 3 is a logic diagram of a portion of counters 114, 148, 150, shift register 116, comparison circuit 152, and control logic 140. Figure 4 shows bar and blank width comparison adders 118, 120, 12.
2,124 is a logic diagram of shift register 121 and scan rate change detection logic. FIG. 5 is a logic diagram of shift registers 126 and 128, read-only stores 130 and 138, and latches 132 and 134. FIG. 6 is a logic diagram of control logic 140 with the elements of control logic 140 appearing at the bottom of FIG. 3 removed. FIG. 7 is a time chart of signals of the main parts of the barcode scanning device of the present invention. FIG. 7A is an enlarged time chart of portion 7A in FIG. 100...System, 102...Stylus, 106...Bar code character, 114...
... Counter, 115 ... Clock, 11
6...Shift register, 118, 120...
... Adder, 121 ... Shift register, 122, 124 ... Adder (comparator).

Claims (1)

[Scope of Claims] 1. A barcode scanning device for scanning a plurality of barcode characters each formed as a unit character by a plurality of bars and spaces having different widths, the device comprising: a positionable scanning stylus; a barcode character scanned by the stylus is decoded from the combination of the bar and the blank; and when the barcode character is decoded, when a change in the scanning speed of the stylus is within a predetermined value, the barcode is scanned by a positionable scanning stylus; a means for measuring the speed of the stylus scanning one unit of barcode characters; and a means for measuring the speed of the stylus scanning one unit of barcode characters;
means for comparing the scanning speed of the bar code character of the unit; and means for providing an error indication when the comparison results in a speed change between the previous scanning speed and the current scanning speed exceeding the predetermined value. A barcode scanning device featuring: