JPS5834624A - D/a converter - Google Patents

Abstract

PURPOSE:To reduce errors due to deviation of capacity of a capacitor by transferring charge accumulated in the first capacitor to the second capacitor to make it 1/2 charge successively and making the sum of output of two times of conversion obtained by interchanging the first and second capacitors its output. CONSTITUTION:Switches S6, S7 are made as shown by 1, 1'. A switch S1 is closed and a capacitor C1 is charged. When S2 only is closed, charge is distributed to C1 and C2 and becomes nearly 1/2. Switches S3 and S4 are controlled according to digital signal and converted analog value is accumulated in a capacitor C3. When conversion is completed, switches S6, S7 become 2, 2' side and similar conversion is performed. The sum of two times of conversion is outputted from a sample hold circuit, and regarded as conversion output.

Description

[Detailed description of the invention] The present invention is suitable for semiconductor integrated circuits/Mugen equipment KJII
do. In recent years, home appliances have gradually become more accurate (14 biy).
16-bit) N/M converters came into use,
There is a need for a low-cost, highly integrated D/A converter, which typically has high resolution. sK
In some cases, a D/A converter using a ladder resistor is used, and the ladder resistor is formed into a highly accurate resistor network using a laser trimming method. This has the potential to increase manufacturing costs.Additionally, ladder resistors based on the Lepto ring method are undesirable because their accuracy deteriorates due to changes over time and temperature.

The present invention is considered to be the above-mentioned kll, and the D/A converter is M08,
The purpose is to provide an inexpensive and compact D/A converter that is self-manufactured using the MO8 process, which is the manufacturing process of L81.
*The purpose of this invention is to provide a D/A converter that compensates for conversion errors caused by processing precision such as slivers.

The present invention will be explained below based on the drawings.

FIG. 1 shows a conventional example of a D/A converter that uses an MO8 PUTATARYUS to achieve low jitter. Such a conventional example has the disadvantage that conversion accuracy deteriorates depending on the processing accuracy of the capacitor. Moreover, FIG. 2 shows one eleventh embodiment of the present invention. The present invention will be described below with reference to conventional examples.

In Fig. 1, 81 to S- are switches consisting of MOB transistors, and 01 to C1 are MO8 capacitors.
is an operational amplifier, a capacitor C1 is connected between its inverting input terminal and its output terminal to form an integrator A, and a sample and hold circuit 2 is connected to the output terminal of the integrator.
A conversion output is obtained from the pull-hold circuit 2. Operational amplifier 1
Switch S4 is connected to the inverting input terminal of , and switches S, , S and capacitor C8 are connected to the other end,
A switch V f 8 t and a capacitor C8 are connected to the other end of the switch S, and a reference voltage source V is connected between the other end of the switch Sl and ground. Switch S, and:! /
The other ends of the power output terminals C, , Q are grounded, and the non-inverting input terminal of the operational amplifier 1 is also grounded.

The operation of the D/A converter shown in FIG. 1 will be explained.

First, turn on the switches S,,S,,S,.

The switches S, , S4 are turned off, the capacitor CI is charged with the reference voltage v3, and the charges in the capacitors C, , C1 are discharged. Next, when the switch 8 is turned on, the charged load of the middle capacitor CI flows into the capacitor O, and if the capacities of the middle capacitors CI and C are equal, the charging voltage becomes +3. MSll (most significant bit!P) of the digital input signal is 1
If so, turn on switch 8a, switch S,...
When S is turned off, the charge on capacitor C8 is transferred to capacitor C1. At this time, the output voltage FE of integrator A
v. is expressed as follows.

V, Tan-+V m Also, if MSll is O, switch 8. is turned on, the charge in capacitor C3 is discharged without being transferred.

Next, switch 8. When the capacitor C3 is turned on, the charge of the capacitor C3 is distributed to the capacitor C3, and the capacitors C,,C,
The voltage of is +V.

If the second bit of MOB is 1, switch S4 is turned on and the charge distributed to capacitor fC9 is transferred to output capacitor C8, and if the second bit of MOB is 0, switch S8 is turned on. The charge on capacitor CI is discharged. If this operation is repeated according to the digital input signal, an analog conversion output corresponding to the digital human input signal can be obtained from the output terminal of the integrator A.

The analog conversion output obtained by this operation is obtained when the capacitors c, , c, , C1 are completely equal, and in reality, there is a processing precision F[K error in the manufacturing process, resulting in a conversion term difference.

Below, we will show what changes can be made by the difference in w4 between capacitors c, , c, , c.

Capacitor 0. The charge Q charged in the capacitor C,
When it is distributed to , it is shown by the following formula.

Qs ''Vcs-Ct-(Ct+O*)VX Also, when the charge q accumulated in the middle capacitor C8 is transferred to the middle capacitor CsIC, it is expressed as the 9th equation.

Q, mO, -VzmQ, -Vy (However, Vy: The charge of capacitor C3 is
Since this operation is repeated, the analog output V is expressed as follows.

If factor K and middle yapashita CI $01 +Cs are equal, then V, -d a ・(+) ・V.

L-rl However, due to manufacturing precision, the capacitor C*
-Cs -Cs I'Cw4 0 where the difference occurs For example,
If an error occurs in the capacitors C,,C,, a linearity error occurs, and one difference due to the capacitors,C,,C,generates a gain,m*. The gain machine difference is the reference voltage V.

Since it can be easily compensated for by setting C1 to 1, it is sufficient to compensate for the linearity error.Therefore, the charge of the capacitor C1 is assigned to the following relationship.

(3, -20, 0-+(Ct +C*) Also, an embodiment according to the present invention that compensates for linearity errors is shown in FIG. 2.t
In the practical example of FIG. 42, the capacitors CI, O, are configured to be replaceable by switches S, , S,. Switch 8. One of the other ends is capacitor C
I, the other end is connected to one end of the capacitor C1, and the switch S! One of the other ends is connected to one end of the capacitor C1, and the other end is connected to one end of the capacitor C3.Other circuit configurations are the same as the 111th.

First, the first D/A conversion is performed with the switch S connected to one end of the capacitor C3 and the switch S connected to one end of the intermediate capacitor C8.

The output voltage v0 of the integrator at that time is expressed by the following equation. ``Next, the switches S, , S, are switched without discharging the charge Q, transferred to the power capacitor C3.

Switch S is switched to connect capacitor CI to capacitor C8. Also, switch 8. Connect the switching destination, capacitor C, to capacitor C1, and re-connect ¥M8B.
From D/A@fusuma.

The output V of the L-th bit is expressed by the following equation.

becomes.

Here, if C, -C (1 + Δ) and C1 - C (1 - Δ), then the error ΔVz from the ideal output car v will be L ΔV ↓ - YusumizuYΔ・, which will be a great improvement. Therefore, the sum of four errors is -Δ1
It will be in the range of ~++Δelectricity. That is, Nakayano (Sita C,,C
, if the error is 1%, the conversion error will be 1101jll. Since the capacitance error of the capacitor can be up to α1%, the conversion error in this case is 1 PPM, which is extremely effective.

FIG. 3 shows another embodiment of the D/MU converter according to the present invention, in which the middle capacitors C, , C, are switched at the 211th! In the embodiment of switch 8. ．． 8. However, in FIG. 3, the switches S, , a.

is used. In that case, switch 8□ to promote discharge.
・is added. These switches repeat the same operation as shown in Figure 2 to convert the digital input signal into D/M. Note that the middle capacitor is an MO8 capacitor, and the switch is formed of a capacitance using a dissipative capacitor, etc.
) Not only transistors but also various transistor switches are possible.・Also, selector switches 8. ．． 8. is formed by at least two transistor switches.

Thermal theory, the present invention is not limited to FIGS. 2 and 3, but the main body of the present invention is to perform two D/A conversions by using the charges charged in the capacitors am, a, and Vc to form a group of switches. Without departing from this, there are various applications of combinations of switches.

[Brief explanation of drawings]

Figure @1 is a conventional example of a D/▲ converter using a medium yapashita. Figure 2 shows an embodiment of a D/l converter according to the present invention. FIG. 3 shows another 111 example of the D/A converter according to the present invention. 'I! Figure 51 Figure 2

Claims (1)

[Claims] It includes first and second capacitors having substantially equal capacities, and a switch group for charging and discharging these capacitors, distributing the charge between the capacitors, and transferring the charge of the integrator Kij41 or the second capacitor. , the charge of the first capacitor is distributed to the second capacitor, and the photocharge of the capacitor 1Ii2 is transferred to the limb integrator according to the digital input signal Nobit, or the charge of the second capacitor is discharged. , $1 means for converting the digital input signal from analog to analog in order of MSB (most significant bit), and distributing the charge of a second capacitor to the first capacitor after the first means, and converting the digital input signal to the digital signal. Therefore, K.
A second means converts the digital input signal into analog to analog in order from the MSB, and the sum of the analog conversion output obtained by the first and second means is obtained as an analog conversion output of the digital input signal. A D/A converter characterized by: