JPS5834621A - Delay circuit for staircase wave signal - Google Patents

Abstract

PURPOSE:To delay staircase wave without deforming waveform by sample holding output of the first circuit that sample holds the staircase wave by a sampling pulse of different phase and outputting. CONSTITUTION:A signal of a signal source 1 is converted to staircase wave in a circuit 2, and added to the first sampling hold circuit 9 through a buffer 4. An output of the circuit 9 is added to the second sampling hold circuit 11 through a buffer 12. An output of the circuit 11 becomes a delay output OUT through the buffer 12. Sampling pulse of different phase from a two-phase pulse oscillating circuit 3 is added to the first and second sampling hold circuits 9, 11.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a staircase wave signal delay circuit that delays a staircase wave signal for a predetermined period while maintaining its waveform, and more specifically, to a staircase wave signal delay circuit that delays a staircase wave signal for a predetermined period while maintaining its waveform. This invention relates to a staircase wave signal delay circuit that can be used in circuits that require

Conventional staircase wave signal delays include lumped constant type delay circuits using coils, resistors, and capacitors, or distributed constant type delay circuits using coaxial cables.

However, when the staircase wave signal is delayed by the above-mentioned conventional delay circuit, there is a drawback that the waveform of the staircase wave signal after the delay is distorted, and the original signal waveform cannot be faithfully delayed.

Further, for this reason, conventional delay circuits are unsuitable for circuits that compare the original signal waveform and the delayed signal waveform.

The present invention has been made in view of the above, and is a staircase wave signal delay that eliminates the above drawbacks, reduces distortion of the signal waveform after delay with respect to the original signal waveform, and can delay the original signal with high precision. The purpose is to provide a circuit.

This purpose, according to the present invention, includes a plurality of stages of sandal hold circuits connected in cascade and to which an input staircase wave signal whose amplitude changes at a constant time interval is applied, and a a multiphase Noyals oscillation circuit that oscillates a plurality of sampling pulse trains that are synchronized and have a phase difference; This is achieved by applying a sampling pulse to each of the sandal hold circuits constituting the signal, and sequentially delaying the input staircase wave signal by each of the sandal hold circuits.

Hereinafter, the present invention will be explained by examples.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a two-stage sandal hold circuit delays a staircase signal by one cycle of the amplitude change of the staircase signal.

In FIG. 1, 1 is a signal source. Reference numeral 2 includes a sample and hold circuit that samples and holds the signal from the signal source 1 at, for example, a fixed period, and is a staircase wave generation circuit that converts the signal from the signal source 1 into a staircase wave signal whose amplitude changes at fixed time intervals. . Reference numeral 3 designates a two-phase pulse oscillator that generates two Sunsoling pulse trains that are synchronized in phase with the period of amplitude change of the staircase wave signal generated in the staircase wave generation circuit 2 and have a phase difference. 4, 6 and 12 are h-
It is a buffer amplifier with high input impedance and low output impedance.

Further, 5 and 7 are switch circuits consisting of electronic switches such as CMO8 analog switches, transistors, field effect transistors, etc., and the switch circuit 5 is a two-phase Nofrus oscillator 3.
The switch circuit 7 is turned on and off by the sampling pulse of the first sampling pulse train from the two-phase pulse oscillator 3, and the switch circuit 7 is turned on and off by the sampling pulse of the second sampling pulse train from the two-phase pulse oscillator 3. Further, the switch circuit constitutes a first sandal hold circuit 9 together with a capacitor 8, and the switch circuit 7 constitutes a second sandal hold circuit together with a capacitor 1o.
The sandal hold circuit 11 of FIG.

The staircase wave signal generated by the staircase wave generation circuit 2 is applied to the 10th sample bold circuit 9 through the amplifier 4, and the output of the first sample bold circuit 9 is applied to the second sample hold circuit through the amplifier 6. 11, and the output of the second sandal hold circuit 11 is configured to be outputted to the output terminal OUT through the buffer amplifier 12. Each sampling pulse is generated at the same time as the amplitude of the staircase wave signal output from the staircase wave generation circuit 2 changes, and each sampling pulse of the first sampling pulse train is generated at the same time as the amplitude of the staircase wave signal output from the staircase wave generating circuit 2 changes. Since the phase of each sampling pulse is also advanced, this phase difference is set to be shorter than the period during which the amplitude of the staircase wave signal outputted from the staircase wave generation circuit 3 is constant.

Now, when the signal shown by the broken line in FIG. 2(1) from the signal source 1 is applied to the staircase wave generation circuit 2, as shown by the solid line in FIG. 2(a), from the staircase wave generation circuit 2, A staircase wave signal whose amplitude changes at regular time intervals is output.

This staircase wave signal is applied to the first sandal hold circuit 9 via the buffer amplifier 4.

On the other hand, the two-phase pulse oscillator 3 is
Figure (a) The first sampling/mother pulse train shown in K and the 20th sampling pulse train are output, and 1il
Sampling of L1/each sampling of 4 pulse strings/4'
rus turns on and off the switch circuit 5, and the second switch circuit 5 turns on and off.
” jl 7 r /4k The two-column O sandering pulse turns the switch/chi circuit 7 on and off.

The switch circuits 5 and 7 are connected to the applied
When the potential is high, the pulse is in the on state, and when the potential is low, it is in the off state.

Therefore, the switch circuit 5 is turned on when each sampling pulse shown in FIG. 2(b) is at a high potential, and charges the capacitor 8 to a potential that follows the amplitude of the input signal. When the potential of the Sunsolings 4 becomes low, the switch circuit 5 is turned off and the connection between the buffer amplifier 4 and the capacitor 8 is disconnected. At this time, since the buffer amplifier 6 has a high input impedance, the potential of the capacitor 8 is maintained without discharging the charges accumulated in the capacitor 8 until the next sampling/4th pulse becomes a high potential.

Therefore, the potential of the staircase wave signal in FIG. 2(a) when the sampling/4 pulse 0) in FIG. 2(b) occurs is transmitted to the capacitor 8 via the switch circuit 5, and the sampling pulse (b) is generated. It is retained until the timing of the hour. Next, at the timing when the sampling pulse (b) is generated, the potential of the staircase wave signal shown in FIG. It is retained until the timing of occurrence. Furthermore, since the switch circuit 5 is bidirectional in that the current flows both in the direction of charging the capacitor 8 and conversely in the direction of discharging the charge of the capacitor 8 and the amplifier 4, the first sandal hold circuit 9 If the signal applied to the capacitor 8 is at a lower potential than the potential already charged in the capacitor 8, the charge of the capacitor 8 will be sucked into the buffer amplifier 4.

As described above, the potential of the capacitor 8 is changed according to the potential of the staircase wave signal of FIG. 2(1) at each timing of the sampling/fourth pulse shown in FIG. It is retained until the timing of occurrence. For this purpose, the output staircase wave of the staircase wave generation circuit 2 is generated for the time t1 between the occurrence of the sampling/rust shown in FIG. The signal is delayed by the first sample and hold circuit 9, and the first sample and hold circuit 9 outputs the staircase wave signal shown in FIG. 2(C).

In this case, the output impedance of the buffer amplifier 4 is set sufficiently low, the input impedance of the buffer amplifier 60 is set sufficiently high, and the switch circuit 50
If the on-resistance is small, even if the width of the sampling pulse is narrow, it is possible to completely charge the capacitor 8 to the input voltage when the switch circuit 5 is on and off, and to discharge the charge in the capacitor 8. Even if the staircase wave signal applied to the sample hold circuit 9 of No. 1 is a staircase wave signal with sharp rising and falling edges, the waveform can be delayed by 11 hours t1 of a similar shape. .

Further, a second sample and hold circuit 11 is cascade-connected to the first sample and hold circuit 9 via a buffer amplifier 6, and a second sample and hold circuit 11 is also connected in cascade to the first sample and hold circuit 9.
The second pulse shown in Fig. 2(d) is used as a sampling pulse.
The sampling pulses of the sampling pulse train are applied, and the switch circuit 7 is turned on by each sampling pulse (E), (E), (G), ■, etc. shown in FIG. 2(d).・It is turned off.

However, each sampling pulse of the second sampling pulse train is set to occur at the time when the amplitude changes with respect to the staircase wave signal shown in FIG. . Therefore, if the period during which the amplitude of the staircase wave signal is constant is tl, then between the first sampling sequence shown in Figure 2(b) and the second sampling sequence shown in Figure 2(a), There is a phase difference, and the time of this phase difference is (tt=)ts.

Therefore, in the same manner as described for the first sandal hold circuit 9, the waveform of the output staircase wave signal of the first sandal hold circuit 9 shown in FIG. Instead, it is delayed by the time is. Therefore, as shown in FIG. 2(-), the staircase wave shown in FIG. 2(a) is applied to the output terminal OUT for exactly the time 1. That is, it is possible to obtain a staircase wave signal delayed by a period in which the amplitude of the staircase wave signal shown in FIG. 2(a) is constant.

Further, as in the embodiment of the present invention described above, the staircase wave signal shown in FIG. 2(a) is delayed by one cycle of its amplitude change to obtain the staircase wave signal shown in FIG. 2(・). In order to do this, it is necessary to construct a /44 pulse oscillator circuit 3 that generates two pulse trains having a phase difference and synchronized with the period of the amplitude change of the staircase wave signal shown in FIG. 2(a). For example, if the signal of the input source 1 is a condigital signal in the stereo demodulation circuit of a 7M stereo tuner, and the staircase wave generation circuit 2 is a sampling-and-hold type stereo demodulation circuit, the t44 pulse oscillation circuit 3 is a 19kHi/
Any two-phase 14 pulse generation circuit that is phase-synchronized with the f-irot signal may be used.

Furthermore, as is clear from the embodiment of the present invention explained above, one embodiment is extended to a delay circuit that delays the input staircase signal by a time longer than the time t1 by connecting two or more sample hold circuits in cascade. It is also easily possible to do so.

As explained above, according to the present invention, a plurality of sample and hold circuits are connected in cascade to increase the accuracy of sampling and holding, thereby reliably delaying a staircase wave signal without causing waveform distortion. be able to.

In addition, since the staircase wave signal can be delayed without waveform distortion, it can be used in circuits that compare the original signal waveform and the delayed signal waveform.In addition, the sampling pulse can be used to change the amplitude of the input staircase waveform. If it is locked to the period of , there will be no deviation in the amount of delay due to aging or environmental changes.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of one embodiment of the present invention. FIG. 2 is a waveform diagram for explaining the operation of one embodiment of the present invention. 2... Staircase wave generation circuit, 3... Two-phase pulse oscillation circuit, 4.6 and 12... Pa, F amplifier, 5 and 7... Switch circuit, 9 and 11... No. 1 and a second sample hold circuit. Patent applicant: Trio Co., Ltd.

Claims (1)

[Claims] a plurality of sample and hold circuits connected in cascade and to which an input staircase wave signal whose amplitude changes at a constant time interval is applied to the first stage; and a multiphase pulse oscillation circuit that oscillates a sampling/base pulse train, and each sampling pulse train output from the multiphase pulse oscillation circuit is sampled into each sample hold circuit constituting the plurality of sample hold circuits. /4' pulse, and the input staircase wave signal is sequentially delayed by each of the sample and hold circuits.