JPS5833789B2 - Pulse amplifier for gate control - Google Patents

Pulse amplifier for gate control

Info

Publication number
JPS5833789B2
JPS5833789B2 JP9501274A JP9501274A JPS5833789B2 JP S5833789 B2 JPS5833789 B2 JP S5833789B2 JP 9501274 A JP9501274 A JP 9501274A JP 9501274 A JP9501274 A JP 9501274A JP S5833789 B2 JPS5833789 B2 JP S5833789B2
Authority
JP
Japan
Prior art keywords
voltage
winding
transformer
outputs
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9501274A
Other languages
Japanese (ja)
Other versions
JPS5127050A (en
Inventor
敬信 畠山
清哉 島
剛 大平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9501274A priority Critical patent/JPS5833789B2/en
Publication of JPS5127050A publication Critical patent/JPS5127050A/en
Publication of JPS5833789B2 publication Critical patent/JPS5833789B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 この発明は、パルス増幅装置に係り、特にサイリスタを
用いた誘導性負荷の位相制御に好適なパルス増幅器に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse amplifier, and more particularly to a pulse amplifier suitable for controlling the phase of an inductive load using a thyristor.

電源と負荷との間にサイリスタなどの導通角制御□□素
子を介在させて負荷への電力を制御するようにし7た電
力料(財)装置において、負荷が誘導性負荷の場合、電
圧に対する電流の位相が遅れる関係上、前記サイリスタ
のゲートパルスはある幅をもった広幅のパルスが必要で
ある。
In an electric power equipment that controls the power to the load by interposing a conduction angle control element such as a thyristor between the power source and the load, if the load is an inductive load, the current with respect to voltage Since the phase of the thyristor is delayed, the gate pulse of the thyristor needs to be a wide pulse with a certain width.

第1図は先に提案した電力制御装置の回路接続図で、E
aは交流電源、5CR1,5CR2は逆並列接続サイリ
スク、Lは誘導性負荷で、主サイリスタ5CR1,5C
R2の導通角を制御して誘導性負荷りへの電力を制(財
)する。
Figure 1 is a circuit connection diagram of the power control device proposed earlier.
a is an AC power supply, 5CR1 and 5CR2 are antiparallel connected thyristors, L is an inductive load, and main thyristors 5CR1 and 5C.
The conduction angle of R2 is controlled to limit the power to the inductive load.

点線で囲まれた部分が上記主サイリスタ5CRI 。The part surrounded by the dotted line is the main thyristor 5CRI.

5CR2の導通角を制(財)するための広幅パルス増幅
装置で、Trは電源変圧器、5CRsは補助サイリスタ
(スイッチング素子)、Tpは1個の鉄心からなる広幅
パルス変圧器で、Pl、P2゜PSは一次巻線端子、8
1.S2.S3.S4は二次巻線端子、D1〜D4はダ
イオード、R1−R4は抵抗、PSは狭幅パルス移相側
■装置である。
This is a wide pulse amplification device for controlling the conduction angle of 5CR2. Tr is a power transformer, 5CRs is an auxiliary thyristor (switching element), Tp is a wide pulse transformer consisting of one iron core, Pl, P2゜PS is the primary winding terminal, 8
1. S2. S3. S4 is a secondary winding terminal, D1 to D4 are diodes, R1 to R4 are resistors, and PS is a narrow pulse phase shift side device.

第2図は第1図の広幅パルス増幅装置の各部の電圧波形
図である。
FIG. 2 is a diagram of voltage waveforms at various parts of the wide pulse amplification device shown in FIG. 1.

Eaは電源電圧、egは狭幅パルス移相制御装置の出力
、Esは補助サイリスタ5CRsの端子電圧、Ep12
は広幅パルス変圧器Tpの一次巻線P1〜P2の端子電
圧、Egl、Es2はそれぞれ主サイリスタ5CR1,
5CR2のゲート電圧である。
Ea is the power supply voltage, eg is the output of the narrow pulse phase shift control device, Es is the terminal voltage of the auxiliary thyristor 5CRs, Ep12
is the terminal voltage of the primary windings P1 to P2 of the wide pulse transformer Tp, Egl and Es2 are the main thyristor 5CR1, respectively.
This is the gate voltage of 5CR2.

第1図において狭幅パルス移相側(財)装置PSの出力
で補助サイリスタ5CRsの電源に同期して半サイクル
ごとに点弧すると、電源電圧Eaが正のときは広幅パル
ス変圧器Tpの一次巻線P1〜P2にはダイオードD1
を介して正の電圧が印加され、電源電圧Eaが負のとき
は広幅パルス変圧5Tpの一次巻線P3〜P2にはダイ
オードD2を介して負の電圧が印加される。
In Fig. 1, if the output of the narrow pulse phase shift side device PS is fired every half cycle in synchronization with the power supply of the auxiliary thyristor 5CRs, when the power supply voltage Ea is positive, the primary of the wide pulse transformer Tp A diode D1 is connected to the windings P1 and P2.
A positive voltage is applied through the diode D2, and when the power supply voltage Ea is negative, a negative voltage is applied to the primary windings P3 to P2 of the wide pulse transformer 5Tp through the diode D2.

そして、広幅パルス変圧器Tpの出力電圧をダイオード
D3゜D4を介して主サイリスタ5CRI 、5CR2
のゲートに印加する。
Then, the output voltage of the wide pulse transformer Tp is transferred to the main thyristors 5CRI and 5CR2 via diodes D3 and D4.
applied to the gate of

このとき、広幅パルス変圧器Tpが所要の電圧一時間積
分になるように設計すると、第2図に示すように、時間
幅Tの広幅のゲートパルスが得られる。
At this time, if the wide pulse transformer Tp is designed to integrate the required voltage over time, a wide gate pulse with a time width T can be obtained as shown in FIG.

このパルス増幅装置は、極めて簡単な構成で、所望の広
幅パルスが得られる点で、従来の装置に比べて非常に有
利である。
This pulse amplifying device is very advantageous over conventional devices in that it can obtain desired wide pulses with an extremely simple configuration.

しかし、1個の鉄心からなる広幅パルス変圧器Tpの一
次巻線に正負の電圧を印加するため、磁束のリセットの
過程でゲートパルスEg1.Eg2にそれぞれ第2図に
示すEgel、Ege2の誤パルスを発生することが判
明した。
However, since positive and negative voltages are applied to the primary winding of the wide pulse transformer Tp consisting of one iron core, the gate pulse Eg1. It has been found that erroneous pulses of Egel and Ege2 shown in FIG. 2 are generated in Eg2, respectively.

これは、広幅パルス変圧器Tpの鉄心のB−H特性に起
因するもので、例えば、鉄心の角形比が第3図に示すよ
うに1の場合は、電源電圧が正から負あるいは負から正
に変化する過程で、電源電圧が零になり、起磁力Hが零
になっても、磁束Φの変化がない(Φ=ΦS)ので広幅
パルス変圧器Tpの巻線に誘起する電圧は零となり誤パ
ルスは発生しない。
This is due to the B-H characteristics of the iron core of the wide pulse transformer Tp. For example, when the squareness ratio of the iron core is 1 as shown in Figure 3, the power supply voltage changes from positive to negative or from negative to positive. Even if the power supply voltage becomes zero and the magnetomotive force H becomes zero in the process of changing to No false pulses occur.

しかし、所望の広幅パルスを得るためには、起磁力Hの
増加に対して簡単に飽和しない変圧器を用いる必要から
第4図に示すように角形比が1以下の鉄心を使用する。
However, in order to obtain the desired wide pulse width, it is necessary to use a transformer that does not easily saturate as the magnetomotive force H increases, so an iron core with a squareness ratio of 1 or less is used as shown in FIG.

この場合、電源電圧が零になり起磁力Hが零になると、
飽和磁束ΦSから残留磁束Φmまで磁束が変化して電圧
を誘起し、誤パルスEge1.Ege2を発生するので
ある。
In this case, when the power supply voltage becomes zero and the magnetomotive force H becomes zero,
The magnetic flux changes from the saturation magnetic flux ΦS to the residual magnetic flux Φm, inducing a voltage and generating an erroneous pulse Ege1. It generates Ege2.

この誤パルスが主サイリスタの誤動作苓まねく場合があ
る。
This erroneous pulse may cause the main thyristor to malfunction.

この発明の目的は、上記の欠点をなくし、負荷が誘導性
負荷である電力制御装置に用いても誤動作することのな
いゲート制(財)用パルス増幅装置を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse amplifying device for a gate system that eliminates the above-mentioned drawbacks and does not malfunction even when used in a power control device whose load is an inductive load.

こい発明の特徴は、上記のごときゲート制御用のパルス
増幅器において変圧器の予定値以下の二次出力電圧を除
去するクリッパ回路を接続したことであり、具体的には
、広幅パルス変圧器の一次又は二次巻線と並列に抵抗体
を接続するか、あるいは二次巻線と制御対象の制御極と
の間に直列に定電圧素子を接続する。
The feature of this invention is that a clipper circuit is connected to the pulse amplifier for gate control as described above to remove the secondary output voltage below the expected value of the transformer. Alternatively, a resistor is connected in parallel with the secondary winding, or a constant voltage element is connected in series between the secondary winding and a control pole to be controlled.

以下この発明を図面に示した一実施例により説明する。The present invention will be explained below with reference to an embodiment shown in the drawings.

第5図は、この発明の一実施例を示す回路接続図であっ
て、R5は誤パルスを除去するための広幅パルス変圧器
Tpの一次巻線Pi、P2゜P3と並列に接続された抵
抗、CI、R6およびC2,R7はコンデンサと抵抗の
直列回路で、それぞれ電源変圧器Trの二次巻線に並列
に接続される。
FIG. 5 is a circuit connection diagram showing an embodiment of the present invention, in which R5 is a resistor connected in parallel with the primary windings Pi, P2 and P3 of the wide pulse transformer Tp for removing erroneous pulses. , CI, R6 and C2, R7 are series circuits of a capacitor and a resistor, each connected in parallel to the secondary winding of the power transformer Tr.

他は第1図と同一であるので、同一符号を付けて説明を
省略する。
Since the other parts are the same as those in FIG. 1, the same reference numerals are given and the explanation will be omitted.

第6図は第5図の各部の電圧波形図で、Eaは電源電圧
、egは補助サイリスタ5CRsの狭幅ゲートパルス、
Esは補助サイリスタ5CRsの端子電圧、Ep12は
広幅パルス変圧器の一次巻線P1〜P2の端子電圧、E
gl、Es2は広幅パルス(端子01〜に1,02〜に
2間の電圧)電圧である。
FIG. 6 is a voltage waveform diagram of each part in FIG. 5, where Ea is the power supply voltage, eg is the narrow gate pulse of the auxiliary thyristor 5CRs,
Es is the terminal voltage of the auxiliary thyristor 5CRs, Ep12 is the terminal voltage of the primary windings P1 to P2 of the wide pulse transformer, and E
gl and Es2 are wide pulse voltages (voltages between terminals 01 and 1 and 02 and 2).

第5図において、電源電圧Eaが正のときはコンデンサ
C1に電流を充電しておいて、補助サイリスタ5CRs
を点弧すると、コンデンサC1の電荷がC1−R1−D
1−P 1−P 2−8CR5R6−ClおよびCI
−Ftl−DI−PIR5−P3−P2−8CRs−
R6−CIの経路で急放電し、電源電圧が負のときはコ
ンデンサC2に電流を充電しておいて、補助サイリスタ
5CRsを点弧するとコンデンサC2の電荷がC2−R
2−D2−P 3−P2−8CR5−R7C2およびC
2−R2−D2−P3−R5P1−P2−8CRs−R
7−C2の経路で急放電し、−次巻線P1〜P2の電圧
Ep12は第6図のように補助サイリスタ5CRsの点
弧時に大きな広幅パルス状の電圧が発生し、所要のパル
ス幅で広幅パルス変圧器が飽和して電圧Ep12は零と
なる。
In FIG. 5, when the power supply voltage Ea is positive, the capacitor C1 is charged with current, and the auxiliary thyristor 5CRs
When igniting, the charge on capacitor C1 becomes C1-R1-D
1-P 1-P 2-8CR5R6-Cl and CI
-Ftl-DI-PIR5-P3-P2-8CRs-
When the power supply voltage is negative due to sudden discharge in the R6-CI path, the capacitor C2 is charged with current, and when the auxiliary thyristor 5CRs is fired, the charge in the capacitor C2 is changed to C2-R.
2-D2-P 3-P2-8CR5-R7C2 and C
2-R2-D2-P3-R5P1-P2-8CRs-R
A sudden discharge occurs in the path of 7-C2, and the voltage Ep12 of the negative windings P1 and P2 generates a large wide pulse-like voltage when the auxiliary thyristor 5CRs is fired, as shown in Fig. The pulse transformer is saturated and the voltage Ep12 becomes zero.

電源電圧が正から負に、あるいは負から正に変化すると
きに発生する誤パルスは抵抗R5に分圧されるためほぼ
零になる。
An erroneous pulse generated when the power supply voltage changes from positive to negative or from negative to positive becomes almost zero because it is divided by the resistor R5.

ここで、コンデンサCLC2および抵抗R6R7が無く
、誤パルス除去用抵抗R5のみを接続した場合、誤パル
スが除去できるが、同時に出力電圧Egl、Eg2も小
さくなり、主サイリスタを点弧できるための所要の電圧
に達するまでの時間がおそくなる。
Here, if capacitor CLC2 and resistor R6R7 are not provided, and only resistor R5 for eliminating false pulses is connected, false pulses can be eliminated, but at the same time, the output voltages Egl and Eg2 will also become smaller, and the required voltage to fire the main thyristor will decrease. It takes longer to reach the voltage.

このため、第5図に示すように電源変圧器の二次巻線と
並列にコンデンサC1と抵抗R6の直列回路およびコン
デンサC2と抵抗R7の直列回路を接続して、補助サイ
リスタ5CRsの点弧時にコンデンサC1,C2の電圧
を急放電してパルスの立上り時に大きな狭幅パルスを発
生して、出力電圧Eg1.Eg2の立上りを非常にはや
くしている。
Therefore, as shown in Fig. 5, a series circuit of capacitor C1 and resistor R6 and a series circuit of capacitor C2 and resistor R7 are connected in parallel with the secondary winding of the power transformer, and when the auxiliary thyristor 5CRs is fired, By rapidly discharging the voltages of the capacitors C1 and C2 and generating a large narrow pulse at the rising edge of the pulse, the output voltage Eg1. Eg2 rises very quickly.

以上のようにこの実症例によれば、従来発生していて問
題となっていた誤パルスを除去できる。
As described above, according to this actual case, it is possible to eliminate the erroneous pulses that have conventionally occurred and caused problems.

また出力パルスの立上りも非常にはやくすることもでき
るので、高性能、高信頼性の経済的なゲート制(財)用
のパルス増幅装置が得られる。
Furthermore, since the rise of the output pulse can be made very fast, a high-performance, highly reliable, and economical pulse amplification device for gate system (goods) can be obtained.

第7図ないし第9図はそれぞれ他の実施例を示す。FIGS. 7 to 9 each show other embodiments.

第7図は誤パルスを除去するための抵抗R7R8を広幅
パルス変圧器Tpの二次巻線S1〜s2 、s3〜S4
と並列に接続している。
Figure 7 shows resistors R7R8 for removing erroneous pulses connected to the secondary windings S1-s2, s3-S4 of the wide pulse transformer Tp.
are connected in parallel.

第8図は広幅パルス変圧器Tpの二次側にツェナーダイ
オードZD1 、Zn2を接続してこれに誤パルスを分
圧させた場合である。
FIG. 8 shows a case where Zener diodes ZD1 and Zn2 are connected to the secondary side of the wide pulse transformer Tp, and erroneous pulses are voltage-divided therein.

なお、第5図の実症例では補助サイリスタ5CRsに流
れる電流が5CRsのターンオフタイム以内に零になる
ことが必要であるので、電流がターンオフタイム以内に
零にならないような回路の場合は、第9図のように2個
の補助サイリスタ5CRs 1.5CRs 2を用い、
これら補助サイリスタに逆電圧を印加して消弧させれば
よい。
In addition, in the actual case shown in Fig. 5, it is necessary that the current flowing through the auxiliary thyristor 5CRs becomes zero within the turn-off time of 5CRs, so if the current does not become zero within the turn-off time, the 9th Using two auxiliary thyristors 5CRs 1.5CRs 2 as shown in the figure,
A reverse voltage may be applied to these auxiliary thyristors to extinguish the arc.

この場合、誤パルスを除去するための抵抗R5゜R6は
広幅パルス変圧器Tpの一次巻線P1〜P2.p3〜P
4に並列に接続する。
In this case, resistors R5°R6 for eliminating false pulses are connected to the primary windings P1-P2. p3~P
Connect in parallel to 4.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は電力制御装置と先に提案したパルス増幅装置の
回路接続図、第2図は第1図のパルス増幅装置の各部の
電圧波形図、第3図は角形比が1の鉄心のB−H特性図
、第4図は角形比が1以下の鉄心のB−H特性図、第5
図はこの発明の一実施例を示す回路接続図、第6図は第
5図の各部の電圧波形図、第7図ないし第9図はそれぞ
れこの発明の他の実施例を示す回路接続図である。 Ea・・・・・・交流電源、5cRL2・・・・・・主
サイリスタ、Tr・・・・・・電源変圧器、Tp・・・
・・・広幅パルス変圧器、5CRs・・・・・・補助サ
イリスタ(スイッチング素子)、D1〜D4・・・・・
・ダイオード、R1−R8・・・・・・抵抗、CI 、
C2・・・・・・コンデンサ、PS・・・・・・多相側
(財)装置、ZDl 、Zn2・・・・・・ツェナーダ
イオード(定電圧素子)。
Figure 1 is a circuit connection diagram of the power control device and the previously proposed pulse amplifier, Figure 2 is a voltage waveform diagram of each part of the pulse amplifier shown in Figure 1, and Figure 3 is the B of the iron core with a squareness ratio of 1. -H characteristic diagram, Figure 4 is the B-H characteristic diagram of iron core with squareness ratio of 1 or less, Figure 5
The figure is a circuit connection diagram showing one embodiment of this invention, FIG. 6 is a voltage waveform diagram of each part of FIG. 5, and FIGS. 7 to 9 are circuit connection diagrams showing other embodiments of this invention. be. Ea... AC power supply, 5cRL2... Main thyristor, Tr... Power transformer, Tp...
... Wide pulse transformer, 5CRs ... Auxiliary thyristor (switching element), D1 to D4 ...
・Diode, R1-R8...Resistance, CI,
C2... Capacitor, PS... Multi-phase side equipment, ZDl, Zn2... Zener diode (constant voltage element).

Claims (1)

【特許請求の範囲】 1 正および負に変化する二次電圧を出力する電源変圧
器と、その正の二次電圧および負の二次電圧を位相側(
財)するスイッチング素子と、当該位相制御された正の
電圧を入力する第1の巻線と負の電圧を入力する第2の
巻線から成る一次巻線、および上記圧の電圧で誘起され
る電圧をゲート信号用に出力する第1の巻線と上記負の
電圧で誘起される電圧をゲート信号用に出力する第2の
巻線から成る二次巻線を有する変圧器とを備え、上記第
1および第2の一次巻線又は上記第1および第2の二次
巻線と並列に抵抗体を接続したことを特徴とするゲート
制(財)用パルス増幅装置。 2 正および負に変化する二次電圧を出力する電源変圧
器と、その正の二次電圧および負の二次電圧を位相制御
するスイッチング素子と、当該位相制御された正の電圧
を入力する第1の巻線と負の電圧を入力する第2の巻線
から成る一次巻線、および上記圧の電圧で誘起される電
圧をゲート制(財)用に出力する第1の巻線と上記負の
電圧で誘起される電圧をゲート信号用に出力する第2の
巻線から成る二次巻線を有する変圧器とを備え、上記第
1および第2の二次巻線と直列であって、当該発生電圧
と逆方向に定電圧素子を接続したことを特徴とするゲー
ト制(財)用パルス増幅装置。
[Scope of Claims] 1. A power transformer that outputs a secondary voltage that changes positively and negatively, and a power transformer that outputs a secondary voltage that changes positively and negatively, and a phase side (
a primary winding consisting of a first winding to which the phase-controlled positive voltage is input and a second winding to which the negative voltage is input, and a voltage induced by the above voltage. a transformer having a secondary winding consisting of a first winding that outputs a voltage for a gate signal and a second winding that outputs a voltage induced by the negative voltage for a gate signal; 1. A pulse amplifying device for a gate system, characterized in that a resistor is connected in parallel with the first and second primary windings or the first and second secondary windings. 2. A power transformer that outputs a secondary voltage that changes positively and negatively, a switching element that controls the phase of the positive secondary voltage and negative secondary voltage, and a switching element that inputs the phase-controlled positive voltage. A primary winding consisting of a first winding and a second winding that inputs a negative voltage, and a first winding that outputs a voltage induced by the above voltage for gate control, and a second winding that a transformer having a secondary winding consisting of a second winding that outputs a voltage induced by the voltage for a gate signal, the transformer being in series with the first and second secondary windings, 1. A pulse amplification device for a gate system, characterized in that a constant voltage element is connected in a direction opposite to the generated voltage.
JP9501274A 1974-08-21 1974-08-21 Pulse amplifier for gate control Expired JPS5833789B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9501274A JPS5833789B2 (en) 1974-08-21 1974-08-21 Pulse amplifier for gate control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9501274A JPS5833789B2 (en) 1974-08-21 1974-08-21 Pulse amplifier for gate control

Publications (2)

Publication Number Publication Date
JPS5127050A JPS5127050A (en) 1976-03-06
JPS5833789B2 true JPS5833789B2 (en) 1983-07-22

Family

ID=14126043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9501274A Expired JPS5833789B2 (en) 1974-08-21 1974-08-21 Pulse amplifier for gate control

Country Status (1)

Country Link
JP (1) JPS5833789B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11478698B2 (en) 2016-05-12 2022-10-25 Gree, Inc. Program, information processing device, and control method
US11691074B2 (en) 2016-09-13 2023-07-04 Gree, Inc. Program, server apparatus, and game system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11478698B2 (en) 2016-05-12 2022-10-25 Gree, Inc. Program, information processing device, and control method
US11691074B2 (en) 2016-09-13 2023-07-04 Gree, Inc. Program, server apparatus, and game system

Also Published As

Publication number Publication date
JPS5127050A (en) 1976-03-06

Similar Documents

Publication Publication Date Title
US2826731A (en) Transistor converter
US4016482A (en) Pulse energy suppression network
KR900015423A (en) Switch mode switching circuit
US3541428A (en) Unsaturating saturable core transformer
US2912634A (en) Electrical control circuits
US3390320A (en) Transistor inverter for synchronized operation with a like paralleled inverter
US3204172A (en) Semiconductor controlled rectifier circuits
US4161773A (en) Push-pull inverter including starter circuit
JPS62503142A (en) Proportional base drive circuit
JPS5833789B2 (en) Pulse amplifier for gate control
US3676766A (en) Multiphase alternating current regulation system for transformer-coupled loads
US3189796A (en) Apparatus for suppressing transients during switching
US3582764A (en) Circuit for forcing turnoff of thyristor
US3768038A (en) Selectable pulse width modulator
GB940669A (en) Improvements in or relating to free-running electric current converters
US3348128A (en) Phase controlled alternating current power circuits using bidirectional conducting devices
US3349311A (en) Control circuit for unsymmetrical power converter
US4333139A (en) Static inverter
US3359484A (en) Power supply apparatus
US3299279A (en) Turn-off circuitry for silicon controlled rectifier and other thyratron-like devices
GB891187A (en) Frequency changer
US3200322A (en) Transistor switching circuit
US3562626A (en) Circuit arrangement for automatically controlling the voltage of an electrical filter
GB676347A (en) Improvements in and relating to electromagnetic scanning systems
JPH0429081B2 (en)