JPS5832542B2 - Paging receiver signal detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection method for a paging receiver such as a pager.

Generally, in a paging receiver such as a pager, the signal extracted from the receiving section is applied to a detection circuit via a filter, the detection circuit detects and rectifies the signal that has passed through the filter, and converts the signal into a pulse width using a monomulti circuit. It is configured to convert the signal and use it as a control signal to control the gate circuit on and off to detect the signal. If a filter that generates impact noise due to vibration, such as a reed filter, is used as a filter, it may malfunction. The disadvantage was that it was more likely to cause

The present invention eliminates the drawbacks of such conventional devices, and the present invention will be described below with reference to drawings of embodiments.

FIG. 1 shows an embodiment of the present invention, in which 1°4 indicates the first
, a second gate circuit, 2 and 5 are first and second filters,
3 and 6 are first and second waveform conversion circuits, 7 is a digital control circuit, 8 is a power amplifier circuit, and 9 is a sounding body.

Here, the digital control circuit 7 generates first and second gate signals e for alternately opening and closing the first and second gate circuits 1 and 4.

gate signal generating means for generating f, first and second counting means for counting pulse waveforms from the first and second waveform converting circuits 3 and 6 up to a predetermined value, and the eleventh and second counting means. The apparatus further includes a reset signal generating means for generating a reset signal for resetting the count values of the first and second counting means in response to a coincidence signal of the bit outputs of all stages.

That is, the digital control circuit 7 inputs the pulse waveform from the first waveform conversion circuit 3 to the input terminal 1 as shown in FIG.
1, the pulse waveform is counted up to a predetermined value by the counter 12, and when the predetermined value is reached, the completion signal is applied to the mono multi circuit 14 via the delay circuit 13, and the mono multi circuit 14 is inverted and its pulse waveform is counted up to a predetermined value. The inverted output of the monomulti circuit 14 is applied to one input terminal of the AND circuit 15.

On the other hand, the pulse waveform of the second waveform conversion circuit 6 is applied to the input terminal 17, the pulse waveform is counted up to a predetermined value by the counter 18, and when the predetermined value is reached, a completion signal is sent to the other input of the AND circuit 15. Apply to the end.

At this time, the signal from the monomulti circuit 14 is normally in an off state, and is used as the gate signal f, and the signal obtained via the inverter 16 is used as the gate signal e to be used as the gate signal e for the first and second gate circuits. It is designed to add 1 and 4.

Further, the output signal from the AND circuit 15 is applied to a latch circuit 19, and its output is applied to an AND circuit 21 to which a signal from an oscillator 20 is applied, and an oscillation output as a calling signal is taken out at an output terminal 22. There is.

In addition, the bit outputs of all stages of the counters 12 and 18 are sent to each OR circuit 23 and 24 in addition to the OR circuits 23 and 24.
40 output to the AND circuit 25, and the AND circuit 25
The output is applied to the counters 12 and 18 as a reset signal.

In such a configuration, a low frequency burst signal F1. F2 is applied to the input terminal 10 and input to the first and second gate circuits 1 and 4.

When the first and second gate circuits 1 and 4 are waiting for a signal, the gate signal e is ON and the gate signal f is OFF, so that the burst signal F1 passes only through the first gate circuit 1. The output is converted into a pulse by the first waveform conversion circuit 3 and input to the input terminal 11 of the digital control circuit 70.

The digital control circuit 7 counts the input pulses b from the input terminal 11, and when a certain value is reached, internally generates a pulse count completion signal d corresponding to the pulse 1 signal F.

The count completion signal d is delayed for a certain period of time by the delay circuit 13 and applied to the monomulti circuit 14, and at the same time the gate signal e is turned OFF, the gate signal f is turned ON, and the second gate circuit 4 is opened.

The next burst signal F2 is input to the filter 5 through only the second gate circuit 4, and its output is converted into a pulse by the second waveform conversion circuit 6 and input to the input terminal 17 of the digital control circuit 7.

The digital control circuit 7 counts the input pulses C from the input terminal 17, and when a constant value is reached, generates a pulse count completion signal g corresponding to the burst signal F2.

When this signal g is generated, the AND circuit 15 latches the latch circuit 19, and the AND circuit 21 outputs the calling signal from the oscillator 20, which passes through the power amplifier circuit 8 to the sounding element 9.
It is configured to sound.

In addition, as a countermeasure against impact noise generated by the filters 2 and 5, the digital control circuit 70 input terminal 11 or 17
If a pulse C or b is simultaneously input from the input terminal 17 or 11 while counting pulses b or C, the output of the AND circuit 25 based on the signals from the OR circuits 23 and 24 counter 12,1
The configuration is such that all count values of 8 are reset and the count is restarted from the beginning.

That is, as shown in FIG. 4, the digital 41J control circuit 7
The pulse input b1 of the burst signal F1 is input to the input terminal 11 of the
′ comes in, and the noise pulse C1 of the filter comes to the input terminal 11 of the digital control circuit 70.
Each of the OR circuits 23 and 24 outputs a pulse signal 1, and the pulse signal i is added to the AND circuit 25, which outputs a reset signal j. , 18 is reset by the reset signal j and manually inputted pulse b1'
, 01' are not counted, and a pulse count completion signal corresponding to the burst signal F1 is not generated.

Furthermore, as shown in FIG. 5, if filter impact noise occurs at the same timing as the burst signal F2 when the frequency of the burst signal F2 and the resonance frequency of the filter 5 do not match, the impact noise will be generated by both the filters 2 and 5. Therefore, due to the configuration of the reset signal generating means described above, the pulse count completion signal of the burst signal F2 is not generated, and malfunctions due to filter impact noise are prevented from occurring.

As described above, according to the present invention, it is possible to digitize low-frequency control, and it is easy to create a circuit on a chip using an IC or microprocessor, so it is possible to significantly reduce the size and cost of the product. It has the advantage of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram of its main circuit, and FIGS. 3, 4, and 5 are diagrams explaining its operation. 1.4...Switching circuit, 2,5...
...Filter, 3, 6...Amplification circuit, 7...
...Digital control circuit, 8...Power amplifier circuit, 9...Sounding body.

Claims (1)

[Claims] 1 11th to which the first and second low frequency burst signals detected and extracted from the receiving section and having a fixed time interval are added.
a second gate means, and fourth and second waveform converting means to which the first and second low frequency burst signals outputted from the eleventh and second gate means are added via a filter;
The control means is provided with a control means for adding pulse waveforms corresponding to the first and second low frequency burst signals outputted from the fourth and second waveform conversion means, and the control means is configured to control the first and second low frequency burst signals. a first gate means for alternately opening and closing two gate means;
, comprising a gate signal generating means for generating a second gate signal and first and second counting means for counting input pulse waveforms from the first and second waveform converting means to a predetermined value,
The first gate means is opened by a first gate signal from the gate signal generating means, and corresponds to a first low frequency burst signal output from the first gate means during the generation period of the first gate signal. The number of human pulses is counted by a first counting means, and when the count value of the "first counting means" reaches a predetermined value, the gate signal generating means is inverted, the first gate means is closed, and the gate The second gate means is opened by a second gate signal from the signal generation means, and an input pulse corresponding to a second low frequency burst signal output from the second gate means during the generation period of the second gate signal. a second counting means, and is configured to output a calling signal when the count value of the second counting means reaches a predetermined value, and the first,
a reset signal generating means for generating a reset signal for resetting the first and second counting means in response to a match signal of the bit outputs of all stages of the second counting means; When the second counting means is counting the number of input pulses corresponding to the fourth burst signal or the second burst signal of the low frequency, the second counting means of the low frequency
When a pulse enters from the input path of the burst signal or the first burst signal, the reset signal generation means generates a reset signal in response to a coincidence signal of the bit outputs of all stages of the first and second counting means. A signal detection method for a paging receiver, characterized in that the count values of the first and second counting means are reset by the reset signal.