JPS583200A - Memory check system - Google Patents

Abstract

PURPOSE:To improve the reliability of check, by accumulating the number of the content of the same bit at the same bit location, calculating the accumulated value and collating the value with the check value. CONSTITUTION:In checking a memory 2, 8-bit or B0-7 of each address in a program memory area 2a is read out altogether and stored in a register 3. A bit register 5 detects if the content of a specific bit in the register 3 is at ''1'' and outputs an addition signal S1 to an adder 6 only at ''1''. The adder 6 reads out a register 7 with the signal S1, adds ''1'' and stores the value to the register 7 as an accumulated value T. All the addresses are checked and outputted to a check circuit 9. The check circuit 9 reads out a check value stored in a check memory area 2b for collation. When the check value of each bit location and the value T are coincident, it is decided that the check value is correct.

Description

DETAILED DESCRIPTION OF THE INVENTION Conventionally, a memory checking method has been to check whether the number of III is an even number or an odd number for the same bit position across all addresses of the memory, that is, the vertical bit. Detecting bar17/? The Itek method was known, but in this method, each bit has 111
If the number of 1's changes by an even number, there is an inconvenience that it becomes impossible to check for erroneous p.

Therefore, the present invention is configured such that the number of identical bit contents at the same bit position across all addresses in the area to be inspected of the memory is accumulated to calculate a cumulative total of 4vA, and this is compared with the inspection value in the check memory area. However, it is an object of the present invention to provide a memory check method that eliminates the above-mentioned drawbacks.

The present invention will be specifically described below based on embodiments shown in the drawings.

FIG. 1 is a block diagram showing an example of a memory check circuit to which the present invention is applied, and FIG. 2 is a schematic diagram showing an example of the memory check method according to the present research.

The memory check circuit 1 has a memory 2t- as shown in FIG. 1, and the memory 2 has memory addresses ME-0 to MFi-nl as shown in FIG. , a program memory area 2a which is an area to be inspected, and a check memory area 2b whose memory addresses are from ME-(n+1) to ME-(m+n) are provided, and each memory address has eight bits from BO to B7. is being eclipsed. Further, as shown in FIG. 1, a bit register 5 is connected to the memory 2 via a register 3, and an adder 6, which constitutes a totalizing means together with a register 7, which will be described later, is connected to the pit register 5. ing. Adder 6 has register T
is connected to the register 7, and the check circuit W&9 connected to the memory 2 is connected to the register 7.

Since the present invention has the above configuration, in order to check the memory 2, the 8 bits of BO to B7 of each address in the program memory area 2a are stored in the read register 3 at once. Pit register 5 is register 3
Detect whether the content of a specific bit in the is 1111, for example, whether the content of the BO bit is l11, and 'l
The addition signal 81 is output to the adder 6 only in the case of -. 7
The JII 8 machine 6 reads the contents of the register 7 in response to the signal 81, and stores the value by 1 in the register I again as 71 [1 calculation L, cumulative value T. In this way, (n + 1) from ME-0 to ME-n in memory 2
For the same bit position fit (in this case, BO bit) of addresses of
The cumulative value T is updated by adding l at a time. M
When the reading of addresses up to E-n is completed, the number of 11'' in the BO bits of all addresses from MFi-o to ME-n is accumulated in the register 7, and the accumulated value T is immediately sent to the check circuit 9. Output.

The check circuit 9 checks the address M of the check memory area 2b.
The test value Kl stored in the BO bit in ME-(mn) is read from E-(n+1) and compared with the cumulative value. In the area 2b, the number of IIm at the same bit position across all addresses is stored for each bit position as a check value, assuming that the contents of the blockrum memory area 2a are all correct. If the check value of and the cumulative value K match, it is determined that the contents of the bit in question over all addresses are correct, and if they do not match, the contents of the bit in question are judged to be incorrect. In this way, by checking the number of IIm for all 87 bits from BO, the contents of blockrum memory area 2a can be accurately checked.

In addition, although the above embodiment described the case where the contents of the memory 2 are checked by accumulating the number of 1II11 at the same bit position over all addresses, the object to be checked, that is, the object to be accumulated is the same bit contents. If so, it goes without saying that it is not limited to 1llI+ but may also be +1O1.

As explained above, according to the present invention, the number of identical bit contents of 1111 or I is calculated and compared with the test value stored in the check memory area 2b, so even if the number of nl- changes by an even number, wA9 can be checked immediately, unlike in the conventional method. This makes it possible to provide a highly reliable memory check method.

[Brief explanation of the drawing]

FIG. 1 shows a memory check circuit to which the present invention is applied.
1. FIG. 2 is a schematic diagram showing an embodiment of the memory check method according to the present invention. 2... Memory 2a... Area to be inspected (program memory) 2b
...Memory check area 6...Accumulation means (adder) 7...Accumulation means (register) K...Test value T... Cumulative value applicant Fujitsu Co., Ltd.

Claims (1)

[Claims] A cumulative means for accumulating the number of identical bit contents at the same bit position over all addresses in the area to be inspected of the memory, and a check memory area for storing the number of identical bit contents at the same bit position over a predetermined address area as a check value □ are provided. . A memory check method configured to check the memory by comparing the calibration value with the cumulative value obtained by the cumulative totaling means.