JPS583175A - Virtual storage controller - Google Patents

Abstract

PURPOSE:To simplify the device, by providing a plurality of page alteration display sections for a table in a TLB device, checking the 2nd display section when the content of the TLB is revised, and rewriting the 1st display section based on the content. CONSTITUTION:A TLB9 has an alteration bit C' as a pair of a virtual and a real address, and the bit C' is set to ''1'', when write is made to a page in service of the address conversion. The TLB has the same page correspondence as the storage key as the hardware and performs the detection and recording of page write generation to the hardware of the TLB primarily, and the R, C bit recording is formed for the storage key with the firmware simply. The alteration bit C' is set to ''1'' with a logical sum AND 12 between a write control output from a decoder 10 and the TLB table retrieval output, when the execution of an instruction 4 includes the write access.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a virtual memory control device in a data processing device using a virtual memory method, and in particular to a simple method for changing change bits and reference bits in a storage key. This invention relates to a virtual storage controller having a management control mechanism.

Conventionally, control mechanisms for managing storage keys have mostly been constructed from hardware, and there have been problems in terms of cost and other aspects of adopting them in relatively small data processing devices. The present invention does not detect (7) record the occurrence of writes to and accesses to pages by the storage key device itself, but partially enhances the function of the TLB (table lookaside table). Storage key management is achieved by keeping a record of the occurrence of page switching in the TLB, and setting the information display of changed bits and reference bits using a microprogram based on the information from the storage key. It is 2+ because it is made easier by the firmware of the mechanism.

For this purpose, the present invention provides a storage key device and a TLB device that include a first page change display section that indicates whether or not each page on the main storage device has been rewritten and a page reference display section that indicates whether or not each page has been accessed. In a virtual memory type data processing device, a second page change display section similar to the first page change display section of the storage key device is arranged in a table in the TLB device to correspond to each piece of address translation data.
A page change display section is provided for TLB faults, etc.
When the contents of the LB are updated, the second page change indicator attached to the old address translation data evicted from the TLB device is checked, and the first page change in the storage key device is performed based on the contents. The present invention provides a virtual storage control device characterized by having storage key control means for rewriting display and page reference display.

First, the conventional technology that is the background of the present invention will be explained. FIG. 1 is a schematic diagram of a conventional virtual storage control device equipped with a storage key and a TLB. In the figure, 1 is a central processing unit, 2 is a storage control device, 3 is a main storage device, and 4
is an instruction with a virtual (logical) address, 5 is a TLB, 6 is a TLB control unit, 7 is a storage key, 8 is a storage key control unit, 9
represents the real (physical) address of the main memory.

When the central processing unit 1 performs translation mode processing using virtual addresses, the virtual address must be translated into a real address on the main memory each time the main memory is accessed during instruction execution.

Therefore, the page frame address PFN, which is a part of the real address, is determined by referring to the segment table and the page table (not shown). T.L.B.
5 is a high-speed register containing a plurality of segments and page-real address (PFN) pairs that are frequently accessed at that time, and is controlled by the TLB control unit 6, and refers to the segment table and page table. It can save you time. However, the capacity of the TLB cannot be increased very much because high speed is required. Therefore, even if the TLB is referenced, there may be cases where data for the desired pair of virtual address and real address cannot be found. At this time, a TLB fault occurs and the TLB is updated by reading the required virtual address and real address pairs from the segment table and page table. During this update, a less frequently used virtual address and real address pair is evicted from the TLB instead of a new virtual address and real address pair. , even if the virtual address space is changed, the contents of the TLB in that hole cannot be used, and the contents of the TLB are invalidated by the PURGE TLB instruction. Note that, as described later, the present invention focuses on the fact that when a TLB fault or a purge TLB occurs, the paired data of the old virtual address and real address is purged from the TLB. The reference bit and change bit on the storage key are set.

After the target page frame address PFN is obtained by referring to the TLB, the table of the storage key device 7 is searched using this page frame address PFN, and the corresponding storage key is read. The read storage key is used as storage protection information for access control of the storage device 3.

The storage key device 7 will be explained below. If a program running on a data processing device mistakenly accesses important storage areas such as other program areas, data areas, or operating system areas on the storage device, the program may run out of control or other programs may or data may be destroyed. For this reason, memory protection information is generally provided, and one method is to divide the main memory into pages or other appropriately sized blocks and provide one storage key for each block. .

FIG. 2 shows an example of the structure of the storage key. The storage key in the figure is the program status word PSw or the channel address word CA.
An access control signal (A) for determining access permission based on a match with the security key in W, a read protection signal (F) that indicates the presence or absence of memory protection information when reading information from a storage device, and a main memory It consists of a reference bit (R) that indicates whether a page (block) in the device has been accessed or not, and a change bit (C) that indicates whether or not a page (block) in the main memory has been written.

The present invention is particularly related to the control unit 8 that manages the reference bit R and change bit C in the storage key described above. Reference pin) R is set to 1# when the corresponding page is accessed, and is read at an appropriate time to read L R as information representing the frequency of use of the corresponding page.
Used as basic data for TJ management. Change again)C
is set to "1" when a write is made to the corresponding page, indicating that the corresponding page has become inconsistent between the main memory and auxiliary memory, and causes Edge to transfer the page from the main memory to the auxiliary memory. The page frame address PFN obtained from the 0 TLB 5, which is useless information, and the intra-page displacement of the instruction address are combined and given to the main memory 3 as a real address 9 for access. At this time, the storage key control unit 8 sets the reference bit R of the storage key of the corresponding page to 1'', and if the access is for writing and is rare, the storage key control unit 8 sets the change bit C to @
Set to 1.11. The above processing has been executed by the hardware logic mechanism of the control unit 8 so far.

Next, embodiments of the present invention will be described with reference to the drawings. Third
The figure is a schematic configuration diagram for explaining the present invention in detail.

The TLB 9 shown in FIG. 3 differs from the conventional one in that it has a change bit C' for each virtual address/real address pair in its table. The change bit C' in the TLB is controlled in the TLB so that it is set to "1" when a write is made to a page for which the TLB has serviced address translation. In the conventional storage key device, a dedicated hardware logic circuit was prepared in order to quickly record the reference bit (R) and the changed bit (C), but in the storage key device of the present invention, the TL
Taking advantage of the fact that B has the same page correspondence as the memory key as hardware and also has the function of storing only the frequently used page addresses that are currently requested for access, the page write occurrence detection record is stored in the TLB. No--
The R and C bit records of the storage key are simply created by the firmware, using the fact that the relevant page was stored in the TLB as information to detect the occurrence of a page reference. That's what I do. The TLB modification bit C' indicates that the decoder 10
1'' is set by a match in AND gate 12 between the write control output from comparator 11 and the TLB table search output from comparator 11.

As the program progresses, there may be cases where the required address translation data does not exist in the TLB, and the TLB shown in 13
LB fault and subsequent <TLB update processing is performed. New address translation data that is rarely requested is TLB.
Address translation data 14 that is determined to be used less frequently is evicted from the TLB table when inserted into the TLB table.

The reference bit ()R and the change bit ()C of the storage key 7 are set by referring to the change bit C' of the old TLB address conversion data 14 that has been evicted.

If the modified bit C' of the old TLB data is 1''', it indicates that a write access was recently made to the corresponding page, so the corresponding reference bit R and modified bit C of the storage key are both '1'''. ``Must be set to 1#. Also, when the change bit C' of the old 'I'LB data 14 is 0'', it means that no write access has been made to the corresponding page recently, so the change bit C of the storage key is set to 1''. do not have to. However, even if the old TLB address conversion data 14 was evicted because it was used infrequently, since it was previously registered in the TLB table, it is relatively recently stored in the main memory. It can be seen that it was used for accessing the device. Therefore, in this case, only the corresponding reference pin ()R of the storage key is set to °'1''.The above processing is summarized in 15 in the figure.

The table position search for the storage key 7 corresponding to the old TLB data 14 is performed using the page frame address PFN of the data 14. The storage key device 7 is configured with a normal storage device,
By executing process 15 using a microprogram, the hardware configuration of the storage key device can be greatly simplified.

Note that the display of the change bit C' of the TLB does not match the display of the change bit C of the memory key during the correction process by expelling address translation data due to a TLB fault, and the change bit C does not match the actual change bit C. The fact that there is a period in which the state is not reflected does not pose a problem that would cause the data processing device to malfunction. That is TLB
Until replacement occurs due to a fault, the corresponding page continues to be updated in the main memory, and after that, no processing is performed to manipulate the corresponding page in the auxiliary memory that has not been updated. Similarly, the fact that the display of the memory key reference pin (H) is delayed from the actual state has a very small effect on the performance of LPU management.

The present invention has been described above according to examples, but T L
B [Although the hardware required to process the changed bits will increase slightly, the storage key management control unit can be implemented as firmware, so the overall and 1. The effect of simplifying the equipment is large.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a conventional virtual storage control device. FIG. 2 shows an example of the configuration of a storage key. Figure 3 shows
0 is a schematic configuration diagram of an embodiment of the present invention. In the figure, 4 is an instruction including a Fi virtual address, 9 is a TLB table, 10 is an instruction decoder, 11 is a Fi address comparator,
12 is an AND gate, 13 TLB update processing, 14 is T
1-7 represent the address conversion data evicted from the LB, and 15 represents the storage key update process, respectively. 0 Patent Applicant Fujitsu Limited Agent/Patent Attorney Mori 1) Hiropitsu 54 3 Zl 0zffi

Claims (1)

[Claims] A data processing device using a virtual storage system, which includes a storage key device including a first page change display section that indicates whether each page on the main storage device has been rewritten, and a page reference display section that indicates whether or not it has been accessed, and a TLB device. In this case, a second page change display section similar to the first page change display section of the storage key device is provided in a table in the TLB device corresponding to each piece of address conversion data, and a second page change display section similar to the first page change display section of the storage key device is provided in the table in the TLB device, and the contents of the TLB are is updated, the second page change display attached to the old address translation data evicted from the TLB device is checked, and the first page change display and the page in the storage key device are checked based on the contents. A virtual storage control device characterized by having a storage key control means for changing a reference display 'f:vp.