JPS5829247A - Data communication device - Google Patents

Abstract

PURPOSE:To make an error check by allowing the data transfer device at a transmitting station to compare transmitted data with resent and received data without including data for the error check in the transmitted data. CONSTITUTION:The data transfer device of a device DV2 disconnects an input and an output line from each other and sends address information for specifying a device DV3 to an exchange LKE through the output line. The data is transmitted through the input line of the channel CH2 of the exchange LKE and is returned to the DV2 through the output line of the CH2. At the exchange LKE, the presence of the transmitted call from the CH2 to the CH3 is known. The transfer device of the DV2 compares the transmitted data with the received data to make an error check and stops the transmitted call if an error is found. Once the transmitted call arrives, the LKE connects the input line of the CH3 to the output line of the CH2 and sends address information on the DV2 to the output line of the CH3. The address information is read by the DV2, LKE, and DV3 and the DV2 confirms the connection between the DV2 and DV3 by the returning of its address information.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data communication connections, and more particularly to selective communication connections between eight or more devices as well as data communication between two specific devices.

Forms of this type of data communication system include star format,
There are ring (loop) formats, bus formats, etc. These are shown in Figures 1a, 1b and 1c, respectively.

In these drawings, tDVI, DV2. DV8
．． Songs - Songs, etc. are scanned.

A data processing device or person such as a printer, memory device, input board, facsimile machine, computer, etc.

It is an output device. In these communication system configurations, all devices transmit and receive data equally. Also, Figure 2a,
As shown in FIGS. 2b and 2c, there is also a type that includes a main station equipped with an LSI with high processing capacity, such as a microprocessor, and allows this main station to manage and control connections. In any case, star format (Figures 1a and 2a)
) and bus format (Figs. 1c and 2c),
It was necessary to divide the data into sections of a certain length and add a CRc check code, etc., before transmitting the data, which required a buffer on the device side. Furthermore, even in redundant data such as image data, errors cannot be detected unless a CRC code or the like is added, making the circuit complex and requiring a transmission sequence.

In the loop format (Figures 1b and 2b), errors can be detected by comparing the looped back data and the transmitted data, but if even one station is not powered on, relaying will not occur. There were many practical problems.

The first object of the present invention is to provide a communication device that can perform error detection similar to loopback even if all the devices in the communication network are not powered on.
It is an object of the present invention to provide a communication device that is still capable of simultaneous communication on two or more lines.

To achieve the above object, the communication device of the present invention has a plurality of input channels and a plurality of output channels, and connects the paired input channel and output channel while waiting for a communication call, and When there is a call, connect the input channel assigned to the destination to the output channel paired with that input channel, connect the input channel with the call to the output channel assigned to the destination, and go up and down 1
Equipped with a switching device that forms a pair of transmission paths, each device D
VI, DV2. DV8. ..., while waiting for a call or receiving a call, it continues to connect its own input channel and output channel5, and when transmitting, it disconnects the input channel and output channel and compares the transmitted data and received data. It includes a plurality of data transfer devices that perform error detection.

Due to this star connection type loop transmission, data communication can be performed simply by turning on the power of the devices necessary for transmission and reception, as long as the power of the exchange device is turned on. When sending a destination address, loop transmission is performed between the transmitting station and the switching device, and after linking, loop transmission is performed between the destination device and the transmitting station. As a result, there is no need to divide data into blocks and add error detection codes, etc., and by monitoring the line status on the transmitting side, transmission can be promptly interrupted when one transmission path is abnormal. Furthermore, with redundant data such as image data, it is possible to overlook random errors and detect only burst errors. Since CPU (microprocessor) data and the like can be divided into blocks and the CRC can be freely added to the data, it is possible to transfer data according to the characteristics of various types of data. Particularly suitable for optical fiber transmission.

An outline of the communication device of the present invention is shown in FIGS. 8a to 8C.

Figure 8a shows a situation in which all devices DVI-DV6 are on standby. The data transfer devices Dvl to DV (3) are connected to the exchange LKE by two-core optical communication cables. During standby as shown in Fig. 8a, each optical communication cable (channel) is The input line (input channel) and the output line (output channel) are connected, and on the device DVl-DV43 side, the input line (input channel)!!: Output line output channel) is connected in the data transfer device. ing. now device DV
Assuming that data is to be sent from 2 to DV3, switch LK
To explain one operation mode of E and devices DV2 and Dv8, first, the data transfer device of DV2 cuts off the input line and the output line as shown in FIG.
Address information specifying 8 is sent to the output line. It enters the input line of channel CH2 of exchanger LKE and returns to DV2 through the output line of CH2. Exchanger L
In KE, it is reported that there is a transmission call from CH2 to CHf3. The DV9 transfer device performs an error check by comparing the transmitted data and the received data, and stops the transmission call if an error occurs. When the exchange LKE receives a call to send, it first sends CUB to the output line of channel CI (2).
The input line of CH8 is connected to send address information indicating DV2 to the output line of CH8. This address information is DV
2. It is read by LKE and DV3, and DV2 judges that there is no error in the connection between DV2 and DVB when its own address information is returned, and if it is not its own address information, it interrupts communication, and LKE sends and receives data. Compare the data and if they match, connect the input line of CH2 to CH8.
If there is a mismatch, connect the output line of CH2, and then connect the output line of CH8.
DV3 knows the source. Therefore, if there is no error, a loopback is formed which loops back at DV8, as shown in FIG. 8c. Therefore, the DV2 performs an error check by comparing the received data with the received data while transmitting the data.

FIG. 4 shows the device DV1. ．． DV2. DV8.・・・・・・
-Specifically shown as an example. The device pvIJ is a data sending and receiving device that sends and receives image data to and from the public internet communication line LDT, and includes a network control device, a data compression/reproduction device, a communication processing/control unit such as a modem, etc. D
l is an optical memory disk, DV is a large capacity memory device up to 3G, DV4 is a floppy disk, DV5 to DV7 are word processors, DV8 is a scanner 1. DV9 and D
VIO is a printer, and each of these devices includes a data transfer device DTI-DTIO.

Next, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 5a shows the configuration of the exchanger LKE in one embodiment, and FIG. 5b shows the configuration of the data transfer device. First, the fifth
The configuration of the exchanger LKE will be explained with reference to FIG. In the exchange LKE, each of the optical-to-electrical converters 0EI-OEn is connected to the human power line of each channel (optical communication cable).
Further, each of the electro-optical converters EOI-EOn is connected to the output line. The respective output ends of OE 1-OE n are input electrical signal lines IN-CH, ~IN-C.
Hn through each of the multiplexers Ml-wMn
The output terminals l-n of the multiplexers M1 to MH are connected to the respective input terminals of the multiplexers M1 to MH, and the output terminals of the multiplexers M1 to MH share the output terminals with the same number, respectively, and output electrical signal lines OUT -CH, to
It is connected to each of EOINEOn via OUT-CHn. The multiplexers Ml-wMn have a latch function, and the setting thereof is indicated by the output of the decoder DE1, and the connection thereof is indicated by the data of the output port of the ROM memory ME1. When the output of MEI instructs the successor to the first output terminal and a set signal is given to the decoder DE1/M1, M1 is set to output its input to the first output terminal. In this setting, channel CH1
input data is sent to the output line of that channel.

Each of the input electric signal lines IN-CH, .about.IN-CHn is connected to a data selector DSI, and the input selection of this data selector DS1 is designated by the output of the decoder DE2. Output electrical signal line OUT -CH,
~OUT -CHn is connected to the output line of the multiplexer MAl, and which output end of the multiplexer MAl is connected to the input end is determined by the output of the decoder DE3.

The exchanger LKE is further equipped with plug-in type code setters CGI - CGn that have a one-to-one correspondence with each of the channels CH1 to C) In, and each of these setters has a The address data of the specified channel is set. address data&j
There is ADD-DATA "r shown in FIG. 6a, and in this embodiment, the address data of channel CHx is
Type instruction code for the device DVX connected to the device (distinction code for printer, scanner, memory, keyboard, word processor, etc.) DV-TYPE, model positive code within each category (for example, for printers, laser, non-impact, dot impact, etc.) (distinction) DV-Nu, code indicating whether or not to transmit packets (indication of whether or not line lock is required until transmission is completed) DV-LOCK, and code PRIOR indicating priority of DVx in the entire system
The device DVx has this address as its own address, and when the DVX is connected to the CHX, the address data of the DVX is set in the setting device CGX. As a result, the address of each channel is flexible, so to speak, and each device specifies the communication destination not by the channel floor fixed to the exchange, but by the destination requirement data. Address data is set in the exchange. The configuration hood is extracted by the data selector DS2, which is controlled by the microprocessor CPJ via the decoder DE4 and the output port of the RAM memory M)J.

The input signal is given to the microprocessor CPJ via the data selector DSI, and also to the error detector ED.
L, is applied to the exclusive or gate EX-OR. - output data is applied to a serial-in-parallel out shift register SHL. When the CPU sends address data, it clears the counter COI, and when the data is sent, it enables COL and starts counting up. When the CPU receives the output data, it clears the counter COI.
Counting up is stopped by disabling L, and thereafter the output of EX=OR is monitored until data transmission is completed. The exchanger LKE sends data to the output line of a certain channel CHy, and the counter COI counts up until it is received at the input channel of CHy. During this time, the output data is stored in the shift register, and the round trip delay of the transmission line is Since the output data delayed by an equivalent amount of time is applied to EX-OR, EX-OR compares the corresponding output data and input data, and when the two match, a low level "0" is output.
A mismatched throat will produce a high level rlJ output.

Next, the configuration of the data transfer device DTX included in the device DVI-DVn-1DVX will be explained with reference to FIG. 5b. Note that data transfer devices included in devices other than DvX also have the same configuration as DTX. In DTX, an optical-to-electrical converter 0F-R is connected to the input line of the optical communication cable of channel CHX, and an electric-to-optical converter EO- is connected to the output line.
The input and output lines of 0E-R and EO-R are connected to the terminal RTX of the DVX, and are interconnected by a loop switch L-8W. The input and output lines are further connected to a microprocessor CPUx and an error detector EDx of the same construction as the EDL.

Next, exchanger LKE (Fig. 5a) and data transfer device (
The operation of FIG. 5b) will now be explained. First, the operation of exchanger LKE will be explained. Exchanger LKE microprocessor CPU
7a and 7b according to the programming of the ROM memory MEI and the programming of its own internal ROM.
The exchange control shown in the figure is performed.

This control is performed by converting the destination call data into address data with a synchronization bit added, as shown in FIG. 6a.
It is transmitted using the address carrier with the Tac cycle shown in Figure b, and the transmission data such as image data is Tdc = as shown in Figure 6B.
This is a case where the network agreement is to transmit data using a data carrier of 54 TAC cycles.

First, referring to FIG. 7a, when the CPU is powered on, it initializes the input/output capo (Ilo) and then sequentially specifies Ml-wMn and sets them to the output settings of the output terminals Nn1-n, respectively. shall be. That is, the multiplexer Mi connects the input line IN CHL to the output line O
Set to connect to UT-CHi. This causes exchange LKE to be connected in a standby loop as shown in FIG. 8a. When you exit this standby loop connection set, CPUTIJ
is the data selector DSL via the decoder DE2,
Every Td, the scanning connection is activated to move the input read line to the next, and the input signal IN-DA is read. If IN-DA is at high level rlJ within Td, read the rear address data from IN-DA, and then the DSL rlJ is stored in the flag memory FLS-no associated with the input line CH to which CHj is connected, and address data is stored in the input channel register Re associated with CHj. When one scan reading of the input line is completed in this way (the seventh
a), PR of the address data of the manual channel register Re- which stores "l" in the flag memory FLS-.
Read the I 0RYTY code and select the highest priority CHj
If the priorities are the same, identify the channel CHj with the smaller channel floor, read the address data including its PRIORYTY code, and send the code to the decoder DE4 indicating Nhl, positive 2, and tJn8. and sequentially increase the floor one by one and set the code setting device CGI, C.
G2. CG8. Read the setting code of .
4 is read as the connection destination channel CHk, and if rlJ is not stored in the input read flag memory FLS-k, DE4 specifies CG, reads the address data of CG, and reads the code given to multiplexer Mk (input line IN -CHl) to output line OUT -CHj
Connect to EJ, EX-OR for error checking
While monitoring the output of CGj address data (that is, CHj address data D V
j address data) to 0UT-CHk. Sending out the Dvj address data to 0UT-CHk is performed by giving CH& instruction data to the decoder DIJ and setting the multiplexer MAL to the Nnk output. There are no errors in this transmission! : CPUL connects multiplexer Mj to OUT-CHl and connects it to the destination (D
EST) Store A in register Rej, and set multiplexers Mk and Mj to 0UT if there is an error.
-CHk and 0UT-CH.

Return to the connection of the connection flag memory FLI-NO° and FLO
-k is set to IJ) and a line abnormality signal NET-ERROR is sent to CHA&'C. And flag memory FLS-
)' and set "1" to the flag memory FLS- again.
reads the PRIORTY of a certain input register Re, and performs similar channel connection control (see the flowchart in the left column of Figure 7b). In this way, when connection control is completed for all the channels called for input reading, the flag memory FLI- is searched for the transmission channel that is connected for communication, and the input line of that channel is
When the m number IN-DA of N-CH1 is read through the data selector DSl, and no data carrier appears on it, the channel CH1 is returned to the output connection, and the channel CHm that was connected to CHl is also changed to the input/output connection. and return to the input reading scanning shown in FIG. 7a (as shown in the right column of FIG. 7b).

Note that DV-LOCK of address data requires locking t=
The device shown will continue to operate until the end of communication, even if data is interrupted.
It continues to output data carriers of lJ or "0". For devices that do not require a lock, the carrier will quickly disconnect if data is interrupted.

Next, the entire transmission and reception operations of the data transfer device DTX will be explained with reference to the flowcharts of FIGS. 8a and 8b.

The microprocessor CPUx of the data transfer device monitors the input line while keeping the normally closed switches L- and SW closed, and waits for a transmission instruction from the terminal device RTX. When there is a transmission request from RTX, the C'PU engineer transmits RTX
It requests destination address data and self address data from , stores them in the register gate, and opens L-8W.

Then, the Tt timer (internal timer) is triggered and a synchronization pit is added to the output line, and the destination address data (A
DD DATA) while sending error detector EDx
If there is no error, it monitors the large number line (IN-DA) for the remaining time of Tt and waits for the arrival of its own address data. When IN-DA becomes "l", it reads the incoming address data, and if it matches the own address data received earlier from R'l'X, it instructs RTX to transmit, and outputs the error detector'EDx. It monitors and gives an error signal to RTX when it becomes rlJ indicating an error. When the signal END indicating the end of transmission arrives from RTX, %L-8W is returned to close, and the process returns to standby for sending and receiving. When the number of call transmissions reaches P times, a call error is notified to the RTX, and L-8W is returned to the closed position to return to the standby mode for issuing and receiving calls (see FIG. 8a).

The input line (IN-DA) is rl when waiting for transmission and reception.
When it reaches J, it triggers timer T8 and waits for the reception address data to arrive, and when it arrives, it stores it in the input register, and if N1T-ERROR arrives before the T8 time period is completed, it returns to reception standby, and if it does not arrive, it When the T8 time period is completed, the RTX is notified of the reception call and the reception address data is transferred.After that, the IN-DA data carrier is monitored, and when it disappears, it returns to reception standby. During this reception, L-8W remains closed.

Due to the operations of the exchange LKE and the data transfer device DTx explained above, when a transmission call is made from the device DV node to the DMA, the input/output channels are separated at the DVj as shown in FIG. At the same time, the destination address data is sent out, and an error check is performed by comparing the sent data and the received data at Dvj. With this error check, DVj-LKE
It can be seen if there is an abnormality in the channel between the two or if the LKE is powered off. L.K.
If the power is turned on to E and there is no abnormality in the channel between DVI and LKE, Dv
j and DVk are connected only one way (downward) from DVA to DV, 7', exchanger LKE sends address data indicating DVj to DVA, exchanger LKE checks for errors, and connects between LKE and DV1. Check for channel abnormalities and check that the DVk is powered on. At this time, if the channel between LKE and DV1 is normal and DVk is powered on, Dvj receives its own address data, so it can check separately from LKE that channel t, KE, and DVk are normal. know. DVA learns from DVj that there is a transmission call. (LKE is DV) If there is no error in the address data, nvj as shown in Figure 9C.
Error checking is performed by further comparing the upstream line of the channel between -DVA (upstream) and the received data (downstream). When there are more errors than permissible, or when the data transmission is finished, Dvj will do the following as shown in Figure 9d:
The up and down lines of channel CH are connected, and LKE returns channels CHj and CHk to a standby state, input/output short-circuited state, in response to the quick disconnection of the carrier.

In the above embodiment, addresses are hierarchical and assigned to channels in the switching device, so each device does not have to set its own address individually, and the destination address may also be, for example, No. 1 of the printer device. Thus, it can be set functionally regardless of the channel. Furthermore, since the address data includes the priority level PRIORITY, when there are transmission calls from multiple devices addressed to the same device, the one with the higher priority setting is connected.

Furthermore, when the exchange LKE calls DVk (Fig. 9b),
DVk can verify the transmitting station DVj, and DVI can verify its own address. However, unlike conventional bus formats and loop formats, it is not necessary to determine the destination address unless the exchanger LKE malfunctions, so such verification can be omitted and only one device (DVI, DV2...・・・・・・
), or the transfer device may not have address identification capability. The exchange LKE is also equipped with another set of error detectors, so that in the connection shown in Figure 9b the transmitting station DVI
By making a loopback connection, both the LKE-DVk 5-in and LKE-DVj lines can be checked for errors at the same time at the exchange LKE. Since transmitting station DVj is not transmitting at this point, a loopback is possible.

As described above, according to the communication device of the present invention, the data transfer device of the transmitting station can perform error checking by comparing transmitted and received data and return received data, and there is no need to include data for error checking in the transmitted data. Good too. Furthermore, communication can be performed in parallel between multiple sets of devices at the same time. The features of the present invention are particularly useful in communication systems that transmit and receive highly redundant image data using optical communication cables.

[Brief explanation of drawings]

Figures 1a, 1b, 1c, 2'a, 2b, and 2C are explanatory diagrams showing communication line connections of conventional data communication systems, respectively. 8C are explanatory diagrams showing communication line connections by the communication device of the present invention, respectively,
FIG. 8a shows the sending and receiving standby state, FIG. 8b shows the sending call state, and FIG. 8C shows the communication state. FIG. 4 is a block diagram specifically showing a combination of a communication device and a terminal device of the present invention;
FIG. 5a is a block diagram showing the configuration of an exchange according to an embodiment of the present invention, FIG. 5b is a block diagram showing the configuration of the data transfer device DTX, FIG. 16a is a plan view showing the transmission call data configuration, and FIG. FIG. 3 is a waveform diagram showing carrier cycles of address data and communication data. 7a and 7b are flowcharts showing the channel connection control operation of the microprocessor CPUL of the exchange LKE, and FIGS. 8a and 8b are the data transfer device DT.
9a, 9b, 9C, and 9d are flowcharts showing the transmission and reception control operations of FIG. 9b shows the first half of the call, FIG. 9C shows the data communication in progress, and FIG. 9D shows the standby state after the communication has ended. DVI-DVIO, DVj-DVI: Communication terminal device L
KE: Exchanger DTI-DTIO, DXx: Data transfer device = CH1
-CHn: Communication channel EOI-EOn, EO-R: Electrical-optical converter OEI→
En, 0E-R: Optical-to-electrical converter IN-CHI~IN
-CHn: Input electrical signal line 0UT-CH, -0
UT-CHn: Output electrical signal line Ml~Mn1MA
l: Multiplexer DSL, DS2: Data selector DEINDE4: Decoder EJ, EDx
: Error detector CPUII, CPUX: Micro ηH chain Figure 8b D 243-

Claims (5)

[Claims] (1) It has multiple input channels and multiple output channels, and when waiting for a communication call, connects the paired input channel and output channel, and when a call is received on a certain input channel, the paired input channel and output channel are connected. a switching device that connects an input channel assigned to a destination to an output channel that has been received, and connects an input channel that has a call to an output channel assigned to a destination to form a pair of up and down transmission lines; a plurality of data transfer devices that continue to connect their own input channels and output channels during reception, and disconnect between the manual channel and the output channel during transmission, and perform error detection by comparing transmitted data and received data; data communication equipment including; (2) When destination address information indicating a call arrives on an input channel, the switching device connects the input channel assigned to the destination to the output channel paired with that input channel, and to the output channel,
A data communication device according to claim 1, which sends out address information assigned to a transfer device that has made a call. (3) The switching device performs error detection by comparing transmitted and received data during data relay.
The data communication device described in Section 1. (4) The switching device has an address setting means associated with a person and an output channel pair, and determines the destination channel by comparing the receiving destination address information with the setting of the address setting means. The data communication device described in Section 1. (5) The data communication device according to claim 2, wherein the switching device compares the input channel that received the call with the setting of the address setting means and reads the address information assigned to the input channel.