JPS5825740A - Encoding system for transmission line - Google Patents

Abstract

PURPOSE:To suppress the continuity of the same code, by inserting two bits, which consist of the combination of a one-bit mark and a one-bit space and have the relation of NOT to each other, at every interval of a certain number of bits to constitute a frame. CONSTITUTION:Input data consisting of m-number of bits is inputted continuously by a clock CLKL of a frequency f0. A voltage controlling oscillator (VCO) 2 receives the clock CLKL and converts the frequency f0 to (m+2)f0/m to generate a new clock CLKH. An (m+2) frequency dividing circuit 3 receives the clock CLKH from the VCO2 and divides it by (m+2) to generate a signal of the time interval corresponding to insertion bits in input data. A speed converting circuit (SPDCONV) 1 receives the clock from the VCO2 and the (m+2) frequency division signal to convert the speed of input data having the frequency f0 to the clock frequency (m+2)f0/m. The output of the SPDCONV1 has a two-bit space at every interval of m-number of bits, and insertion bits P1 are inserted to the space.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention enables same-sign continuation by inserting insertion bits in which each of the two bits consisting of a combination of one mark and one space has a negative relationship with each other for every fixed number of bits. This relates to a transmission line coding system that prevents this.

Transmission line coding methods used in digital communications include:
In order to ensure bit synchronization on the receiving side, it is desirable that the same code #0'' or #11'' does not continue for a long period of time. The scrambled binary encoding system, which has been widely used in the past, prevents the same code from occurring consecutively by multiplying the data signal with a pseudorandom (PN) code.
Still, it is probable that the '01' or '1' code continues for a long period of time, and the complete K BSI (Bit 5
sequence Indmpgndout).

Therefore, IF7B1P is used as a BSI code.

Various coding systems such as pxsr and ppxs (References: Communication System Study Group Materials CS8O-176 [On the transmission line code structure of 1oCWh/s optical transmission system JP-17 to 12)
), but all of these have the drawback that the same code sequence is relatively long compared to the rate of increase in transmission line speed, and fault detection cannot be done in-service, or even if it is possible, the circuit size will be large. was there.

The purpose of the present invention is to prevent the same code from occurring consecutively and to implement BSI by inserting a 2-bit insertion bit consisting of a combination of a 1-bit mark and a space for every m bits of information (m is an arbitrary integer). The purpose of this invention is to provide a coding system with a high degree of accuracy. In the method of the present invention, by using even parity money as the insertion bit, it is also possible to perform in-service fault searching.

In order to achieve this purpose, in the transmission line coding system of the present invention, input data is speed-converted on the transmitting side to create two free bits for every given number of bits, and
Two insertion bits, each of which has a negative relation to each other, are inserted into the empty part and transmitted. On the receiving side, the insertion bits are extracted from the input data and the input data from which the insertion bits have been removed is transmitted. The feature is that the original data is played back after speed conversion.

Furthermore, if this code is used, a combination of inserted bits and negated bits will appear every m+2 bits, so if you take the exclusive OR with the bit delayed by one time slot, it will always be +2
A mark always appears for each bit. By monitoring this mark, it is also possible to check the error rate of the transmission path.

Examples will be described below.

The coding system of the present invention inserts insertion bits each consisting of a combination of one mark and one space, each of which is in a negative relationship with each other, for every fixed number of bits.
The feature lies in the way the frame is constructed.

In other words, in the conventional coding system, a method is used to suppress the same code consecutively by inserting odd parity, marks, and spaces at a fixed period, for example, every m bits. ``The length of the sequence could be up to 2 bits, for example.

The present invention was developed based on the idea that in order to suppress the same code from occurring consecutively, it is sufficient to insert a negation bit after the first inserted bit.

In the coding system of the present invention, the length of dO" continuity or #1" continuity is always +2 bits at the longest for the same bit period. Furthermore, by setting the inserted bits to even parity, it is possible to perform in-service fault searching.

The code in the method of the present invention is mjNP+
This will be named the 1P code.

FIG. 1 is a diagram showing a frame structure in an embodiment of the transmission line coding system of the present invention. In the figure, (- indicates a generated (Q pulse train). One frame consists of 16 blocks, and each block consists of an information poison bit and 2 insertion bits. Therefore, the frame length is 16 (m+
2) It is a bit. Also, in (mouth), the position of the inserted bit is numbered 1, 2, 3, etc. It is shown by... (6) indicates a frame synchronization signal, and signal F
, (1) and F, (Of) are inserted alternately every 8 blocks. (d indicates a service signal.

As a service signal, a service control signal SC
1 bit and its negation, 1 bit of the Ω° signal, or 1 bit of the auxiliary signal AUX, and 1 bit of the i signal, its negation, are inserted alternately every 8 blocks. (,g)
indicates a parity signal.

Of the inserted bits in the 90 pulse train shown in (b), they are inserted at positions other than the frame synchronization signal and service signal. In FIG. 1, parity signals (Fl sP**Il) + CP*eP signals are inserted at the positions of insertion bits (2eL*('s7*8)*...), respectively.
F@)+... are inserted sequentially.

FIG. 2 is a diagram showing the structure and insertion method of a parity signal, and corresponds to the inserted bits 1 to 30 in FIG. 1. In the same figure, '1*'marot 1m s...
. . . indicates information bits, each consisting of an inertia bit. The insertion bit P1 for the information bit 11 is
It consists of an even parity pit P1E and one negation bit thereof. The sign of the even parity bits p, x is from the negation bit in the insertion bit preceding the information bit 1m,
It is determined by counting the parity up to the last bit of information bit 11 and taking the even parity. The same holds true for the relationship between the information bit I and the insertion bit P, and the relationship between the other information bits and the corresponding insertion bits. In the method of the present invention, the number of bits of information may be an even number or an odd number.

FIG. 5 is a block diagram showing an example of the configuration of a transmitting/receiving section in the transmission path coding system of the present invention. In the figure, (α) indicates the transmitter, and 1 indicates the speed conversion circuit (SPD C0NV).
, 2 is a voltage controlled oscillator (rc), 5 is an (m+2) branch circuit, 4 is an even parity check circuit (E PARI C
0UNT), 5 is a pulse x insertion circuit (PLS IN5). In addition, (6) indicates a receiving section, 11 is an insertion bit extraction circuit (EXTRACT), 12 is an (m+2) branch circuit, 13 is a synchronization detection circuit (SYNC), 14 is a voltage controlled oscillator (VC), and 15 is a speed conversion circuit. Circuit (SPD CO
N, 16 is a parity check circuit (PARK CHE
CK).

In FIG. 3(b), the input data consists of bits and is continuously inputted by a clock cLKL having a frequency f0. The VCO 2 receives the clock CLKL, converts its frequency f to fini 70, and generates a new lock CLKH. (m+2) frequency divider circuit 3 is V
The clock CLKII of CO2 is received and frequency-divided by (m+2) to generate a signal with a time interval corresponding to the inserted bit in the input data. SPD C0NV 1 is VCO2
In response to the original clock CLKH and the (m+2) branch signal, the input data having the clock frequency f is speed-converted to the clock frequency -fo. Therefore, the output of SPD C0NV1 has two free bits for each poison bit. E PARI COUNT 4 is SPD C0N
The number of marks for each +1 bit between the information groove pit outputted from V1 and the negation bit in the preceding insertion bit is counted, and even parity pits are created and output. PLS lN55 is 5PDCONV1
The speed-converted data output from the , ie the information is always 2 per bit. For signals with empty bits,
E PARI 3rd parity signal consisting of even parity pits and their negation bits output from C0UNT4
Insert the service control signal indicated by A in Figure (-) and the auxiliary signal also indicated by B at the positions indicated in Figure 1. In this way, the Output data with (m+2) bits as one block and 16 blocks as one frame is output from the PLS IN 55 along with the clock CLKH.

In FIG. 5 (6), the data sent from the transmitter is transmitted to EXTR along with the clock CLK which is sent out at the same time.
Input to ACT 11. On the other hand, the (m+2) frequency divider circuit 12 receives a clock CL having a frequency m 2 y.
KHt is received and divided by (m+2), and 5Y
Upon receiving a signal that determines the frame period from the NC 15, it generates a signal that determines the block period necessary for extracting the inserted bits and supplies it to the 5YNC'13. 5YNC
EXTRACT 15 receives input data and detects a frame synchronization signal contained therein, and also receives a signal for determining a block period from the (m+2) branch circuit 12 and generates a signal for determining a frame period. and (m+2) are supplied to the branch circuit 12. EX
TRACT 11 thereby extracts and outputs a parity signal, a service control signal indicated by C, and an auxiliary signal indicated by D from the input data, and outputs the data from which these inserted bits have been removed to SP.
Input to D C0NV 15.

The VCO 14 receives the clock CLKH with the frequency list +2 fa input from the EXTRACT II, converts the frequency, generates the clock CLKL with the frequency f, and outputs the clock CLKL with the frequency f.
Supply to COME' 15. SPD C07vP'
15 is its input clock frequency m + 2
The input data imaginary + 2 bits (regular bits are information bits and 2 bits are empty) of t, are speed-converted into data m bits of clock frequency f, and are output. PARI CHE
The CK 16 checks the false alarm rate using the parity signal extracted by the EXTRACT 11, and issues two types of alarms (KINERRALM and MAJ ERRALM) depending on the magnitude of the false alarm rate according to the evaluation criteria of the transmission path.
occurs.

In this way, in the transmission line encoder of the present invention, a 2-bit insertion pit consisting of a combination of a mark and a space is inserted for each bit of the information part, so there is a risk that the same code will continue for m+2 bits or more. This method eliminates the possibility of occurrence of consecutive same codes, and can shorten the number of consecutive same codes that may occur compared to conventional methods.

Furthermore, by using parity pits as insertion pits, it is possible to check for occurrence of errors on the receiving side. Furthermore, by sending a frame synchronization signal as an insertion bit, it can be used for frame synchronization on the receiving side, and by sending various service signals as insertion bits, various services with auxiliary purposes on the transmission path can be used. You can also do In the above embodiment, even parity is inserted as the insertion bit, but it goes without saying that odd parity may also be used. However, when even parity is used, there is an advantage that fault search can be performed in-service.

In other words, when using even parity, by adding the output data to a T-type 7 lip-flop (T-FF),
If there is no bit error, the sign of the output will not be inverted, but
By utilizing the fact that the output sign is inverted due to a one-bit error, it is possible to easily search for a fault even during information transmission. However, if odd parity is used, the output of the T-FF will always be inverted even if there is no bit error, so such a fault search cannot be performed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a frame structure in an embodiment of the transmission line coding method of the present invention, FIG. 2 is a diagram showing the structure and insertion method of a parity signal, and FIG. 3 is a diagram showing transmission and reception in the transmission line coding method of the present invention. FIG. 2 is a block diagram showing an example of the construction of a part. 1... Speed conversion circuit, 2... Voltage controlled oscillator (PC
6... (Quantity 2) Branch circuit, 4... Even parity check circuit (EPARK COUNT), 5... Pulse insertion circuit (PLSINS), 11... Insert bit extraction circuit (EXTRACT), 12 ... (Work 2) Branch circuit, 16... Synchronization detection circuit (SYN, 14...
Voltage controlled oscillator (VCO), 15...speed conversion circuit (
SPDCONV), 16... Parity check circuit (
PAR1cgEcx). Patent applicant: Fujitsu - large company (one other person) agent
Patent attorney Gobe Tamamushi (3 others) Figure 1 Figure 2

Claims (4)

[Claims] (1) On the transmitting side, input data is speed-converted to create two empty bits for every given number of bits, and two inserted bits, each bit of which has a negative relationship, are inserted into the empty part. A transmission line coding system characterized in that the inserted bits are inserted and transmitted, the inserted bits are extracted from input data on the receiving side, and the input data from which the inserted bits have been removed is speed-converted to reproduce the original data. (2) The transmission line coding system according to claim 1, wherein the inserted bits are comprised of a parity bit and its negation bit for the input data of the arbitrary fixed number of bits. (3) A parity signal in which the insertion bits are composed of parity pits and negation bits of the input data of the arbitrary fixed number of bits, a frame synchronization signal for frame synchronization, and a service for auxiliary purposes in the transmission path. 2. The transmission line coding system according to claim 1, characterized in that the transmission path coding system is comprised of a bit and its negation bit. (4) The transmission line coding system according to claim 2 or 3, wherein the parity pit is an even parity bit for the input data of the arbitrary fixed number of bits.