JPS5825622Y2 - Vertical oscillator - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a multivibrator type vertical oscillation device, and its purpose is to improve interlaced scanning within a vertical synchronization holding range.

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a circuit diagram of a vertical oscillation circuit, in which transistor 3 and transistor 10 constitute a multivibrator.

First, to explain the general operation, when a DC voltage for operating the oscillation circuit is applied to terminal A, one transistor 10 is turned on, and the current flows from the base of resistor 2 → capacitor 5 → transistor 10 to the emitter. , and the capacitor 5 is charged with electric charge.

When the charging of the capacitor 5 is completed, the transistor 1
The base of 0 is at ground potential and transistor 10 is cut off.

Then, the collector potential of the transistor 10 rises, so the base potential of the transistor 3 rises, turning on the transistor 3, and the charge charged in the capacitor 5 becomes
It is discharged in a loop from the transistor 3 to the variable resistor 7 and back to the capacitor 5.

The charging/discharging time constant at this time is approximately determined by R2.C5<R7.C5, where the value of resistor 2 is R2, the value of capacitor 5 is C5, and the value of resistor 7 is R7.

Therefore, by changing the resistance value of the variable resistor 7, the oscillation frequency can be changed.

When capacitor 5 finishes discharging, transistor 1
The base potential of 0 rises, the transistor 10 turns on, and oscillation is repeated again.

In this way, the transistor 10 is turned on during the retrace period, and the transistor 3 is turned on during the scanning period.

The basic operation waveform at this time is shown in FIG.

Here, O is the earth conductor.

FIG. 2 shows the base voltage waveform of the transistor 10, and C shows the voltage between the output terminals D and E in FIG. 1, which is the output voltage waveform of the oscillation circuit.

In addition, for the synchronization signal, a negative pulse signal as shown in FIG. In addition to

Note that resistor 4 and resistor 6 are the emitter resistor and base resistor of transistor 3, respectively, and resistor 8 is transistor 1's emitter resistor and base resistor, respectively.
The collector resistance is 0.

9 is a capacitor that is a feature of the present invention.

FIG. 3 is an enlarged view of the base voltage waveform of the transistor 10 shown in FIG. 2, and is the waveform when the capacitor 9 is not present.

If a horizontal current is flowing through the ground of the oscillation circuit or the power supply, resistor 4. A horizontal ripple is applied to the discharge loop during the scanning period through the resistor 2 and the like.

Here, O is the ground potential, and the dotted line d is the transistor 10.
As shown in the figure, the level d at the operating point of the transistor 10 is a horizontal component.If there is a ripple, the transistor 10, which is off during the scanning period, will turn on once due to the influence of the horizontal component, and then immediately turn on. After that, it turned off, and then turned on again, for a short period of time, but in small increments.
This repeats the OFF state, causing a slight shift in the scanning period, which causes a shift between the synchronization signal and the retrace period, which makes it impossible to perform interlaced scanning properly.

However, when the capacitor 9 is inserted between the collector base of the transistor 10 as in the present invention, the transistor 10 is off during the scanning period, so the circuit shown in FIG. 1 is equivalently a circuit without the transistor 10. ,
That is, the capacitor 9 is inserted between the connection point of the capacitor 5 and the resistor 7 and the connection point of the resistors 6 and 8, and the capacitor 9 and the resistor 7 form an integrating circuit for the discharge loop. Resistor 7 and capacitor 9
By selecting the best value for the time constant with respect to the ripple, the ripple is integrated as shown in FIG. 4, and the malfunction of turning on and off the transistor 10 due to the influence of this ripple is eliminated.

This allows interlaced scanning to be performed smoothly.

Also, during the retrace period, the transistor 10 is turned on, so even if the capacitor 9 is inserted between its collector and base, both ends of the capacitor 9 are at ground potential, so no integration is performed during the retrace period. .

Another embodiment of the invention is shown in FIG.

In the figure, numerals 1 to 10 are similar to those in FIG. 1, except that transistor 11 and transistor 10 form a Darlington circuit.

In this circuit as well, the horizontal component is integrated by the capacitor 9, making interlaced scanning smooth.

Conventionally, in order to perform interlaced scanning smoothly, the number of stages in the integrating circuit was increased, the time constant of the filter was increased, and the horizontal component was minimized as much as possible, but it has not been possible to achieve a completely satisfactory result in either case. In addition, the former method has the drawback that the configuration becomes complicated, and the latter method has the drawback that the capacitance of the capacitor constituting the filter must be increased.

As explained above, according to the present invention, integration is almost perfect by inserting one capacitor, so even if the number of stages of the integrating circuit is reduced or the capacitance of the filter capacitor is reduced, interlaced scanning can be performed smoothly. can be done,
It is extremely effective in practice.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a vertical oscillation device according to an embodiment of the present invention, Figures 2 a-c are voltage waveform diagrams of various parts of the circuit in Figure 1, and Figure 3 is an enlarged view of Figure 2. FIG. 4 is an enlarged view of FIG. 2, a waveform diagram when capacitor 9 is included, and FIG. 5 is a circuit diagram of another embodiment of the present invention. 3.10...transistor, 9...capacitor.

Claims (1)

[Scope of utility model registration request] A first resistor is inserted between the collector of the first transistor that is conductive during the scanning period and the supply power terminal, and a first resistor is inserted between the collector of the first transistor and the base of the second transistor that is conductive during the retrace period. A second capacitor is inserted between the emitter of the first transistor and the base of the second transistor, and the retrace period is equal to the time constant of the first resistor and the first capacitor. vertical oscillation, in which a second capacitor is inserted between the collector base of the second transistor; Device.