JPS5823929B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5823929B2
JPS5823929B2 JP14743176A JP14743176A JPS5823929B2 JP S5823929 B2 JPS5823929 B2 JP S5823929B2 JP 14743176 A JP14743176 A JP 14743176A JP 14743176 A JP14743176 A JP 14743176A JP S5823929 B2 JPS5823929 B2 JP S5823929B2
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
silicon film
electrode layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14743176A
Other languages
Japanese (ja)
Other versions
JPS5371576A (en
Inventor
大曽根隆志
堀内司朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14743176A priority Critical patent/JPS5823929B2/en
Publication of JPS5371576A publication Critical patent/JPS5371576A/en
Publication of JPS5823929B2 publication Critical patent/JPS5823929B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は電極層を膜上に形成する半導体装置の製造方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which an electrode layer is formed on a film.

第1図、第2図に従来例を示す。A conventional example is shown in FIG. 1 and FIG. 2.

第1図において、シリコン等の半導体基板上に形成され
た5102膜等の第1の膜11の上面に、多結晶シリコ
ンやモリブデンなどからなる電極層12を形成する場合
常温(約400℃)に保持しながら多結晶Sl膜12を
真空蒸着法で形成する。
In FIG. 1, when an electrode layer 12 made of polycrystalline silicon, molybdenum, etc. is formed on the upper surface of a first film 11 such as a 5102 film formed on a semiconductor substrate such as silicon, the electrode layer 12 is formed at room temperature (approximately 400° C.). A polycrystalline Sl film 12 is formed by vacuum evaporation while maintaining the structure.

この試料を、後に行なう不純物拡散や熱酸化工程で、1
.100°Cの電気炉中で熱処理した場合、電気炉から
取り出すと上記多結晶Si膜12は剥離してしまい、密
着性が悪い。
This sample is subjected to impurity diffusion and thermal oxidation processes that will be performed later.
.. When heat-treated in an electric furnace at 100°C, the polycrystalline Si film 12 peels off when taken out from the electric furnace, resulting in poor adhesion.

第2図a ”−eにCCD等の半導体装置に従来方法を
適用した場合について説明する。
A case in which the conventional method is applied to a semiconductor device such as a CCD will be explained with reference to FIGS. 2a" to 2e.

シリコン基板上に形成された5i02膜等の第1の膜2
1の上面にCVD法によって第1の多結晶シリコン膜2
2及び、リン、ガラス等の第2の膜23を形成する(同
図a)。
A first film 2 such as a 5i02 film formed on a silicon substrate
A first polycrystalline silicon film 2 is deposited on the upper surface of 1 by CVD method.
2, and a second film 23 of phosphorus, glass, etc. is formed (FIG. 1A).

第2の膜23及び多結晶シリコン膜22の二層膜を通常
のフォト・エツチングによって島状に形成する(同図b
)。
A two-layer film consisting of the second film 23 and the polycrystalline silicon film 22 is formed into an island shape by ordinary photo-etching (Fig.
).

その後、多結晶シリコン膜22の露出した側面を加熱酸
化法によって選択的に酸化し5i02膜24とする。
Thereafter, the exposed side surfaces of the polycrystalline silicon film 22 are selectively oxidized by a thermal oxidation method to form a 5i02 film 24.

この場合、多結晶シリコン膜22はCVD法で形成され
ているため第1の膜21との密着性に優れ、高温(例え
ば1.100℃)の加熱酸化処理に於いても剥離は生じ
ない(同図C)。
In this case, since the polycrystalline silicon film 22 is formed by the CVD method, it has excellent adhesion to the first film 21 and does not peel off even during heat oxidation treatment at high temperatures (for example, 1.100°C). Figure C).

次に、基板21を加熱しつつ真空蒸着法によって第2の
多結晶シリコン膜25を形成する。
Next, a second polycrystalline silicon film 25 is formed by vacuum evaporation while heating the substrate 21.

この時、第2の膜23の側面には多結晶シリコン膜25
か付着形成されないようにする(同図d)。
At this time, a polycrystalline silicon film 25 is formed on the side surface of the second film 23.
(d) in the same figure.

その後、第2の膜23を選択的に除去すれは(リン・ガ
ラスを用いた場合にはHF水溶液を用いる)、その上に
形成された第2の多結晶シリコン膜25も同時に除去さ
れる(リフト・オフ・エッチ法)(同図e)。
After that, when the second film 23 is selectively removed (using an HF aqueous solution when phosphorus glass is used), the second polycrystalline silicon film 25 formed thereon is also removed at the same time ( lift-off etch method) (Figure e).

以上の工程によって、多結晶シリコン膜22゜25がS
iO□膜24で絶縁されて配置される。
Through the above steps, the polycrystalline silicon film 22°25 becomes S
It is arranged so as to be insulated by an iO□ film 24.

これ等の構造は電荷結合素子の高密度ゲート電極として
有用である。
These structures are useful as high density gate electrodes in charge coupled devices.

このように従来法で得られた第2図eに示す構造では、
高温の熱処理工程(例えば、この後の加熱酸化工程や熱
拡散工程)を施こすことにより、第2の多結晶シリコン
膜25の剥離が発生し実用に供することができない。
In the structure shown in FIG. 2e obtained by the conventional method,
By performing a high-temperature heat treatment process (for example, a subsequent thermal oxidation process or thermal diffusion process), peeling of the second polycrystalline silicon film 25 occurs, making it impossible to put it to practical use.

本発明は上記の電極層のはく離現象をなくすためになさ
れたもので、電極層の形成を確実に行なうことのできる
半導体装置の製造方法を提供するものである。
The present invention was made in order to eliminate the above-mentioned peeling phenomenon of the electrode layer, and provides a method for manufacturing a semiconductor device that can reliably form the electrode layer.

以下図面とともに本発明を実施例に基いて説明する。The present invention will be explained below based on examples together with the drawings.

第3図は本発明の基本を示す説明図である。FIG. 3 is an explanatory diagram showing the basics of the present invention.

同図において、まず半導体基板上の第1の膜11の上面
にCVD法によって100人〜1.000人の多結晶シ
リコン膜31(第1の電極層)を形成した後、基板を1
00°C〜400°Cに熱しつつ、所望の厚さの多結晶
シリコン膜12を真空蒸着法で形成する。
In the figure, first, a polycrystalline silicon film 31 (first electrode layer) of 100 to 1,000 layers is formed on the upper surface of a first film 11 on a semiconductor substrate by the CVD method, and then the substrate is
A polycrystalline silicon film 12 having a desired thickness is formed by vacuum evaporation while heating to 00°C to 400°C.

この試料は、1.100℃の電気炉で急熱急冷の熱処理
を行なっても多結晶シリコン膜31゜12の剥離は全く
発生しない。
In this sample, the polycrystalline silicon film 31.degree. 12 does not peel off at all even when heat treatment is performed by rapid heating and cooling in an electric furnace at 1.100.degree.

第4図a ”’−eにこの基本を用いた本発明の一実施
例を示す。
An embodiment of the present invention using this basic principle is shown in FIGS. 4a''-e.

第4図aは従来例の第2図までと全く同様に形成する。FIG. 4a is formed in exactly the same way as the conventional example up to FIG. 2.

次に全面にCVD法によって100λ〜1.000人の
多結晶シリコン膜41を形成する。
Next, a polycrystalline silicon film 41 having a thickness of 100λ to 1,000 is formed over the entire surface by CVD.

この時、CVD法で形成しているため、5IO2膜24
の側面も含めて全面に均一に付着形成される(同図b)
ここで、第2の被膜23はリフトオフ用に用いられるの
で、多結晶シリコン膜41が第2の膜23の側面に厚く
形成されるのは好ましくないからである。
At this time, since it is formed by the CVD method, the 5IO2 film 24
It is evenly deposited on the entire surface including the side surfaces (Figure b)
Here, since the second film 23 is used for lift-off, it is not preferable for the polycrystalline silicon film 41 to be formed thickly on the side surface of the second film 23.

従って、多結晶シリコン膜41は半導体基板21七の密
着性が図れる程度の厚さに形成している。
Therefore, the polycrystalline silicon film 41 is formed to have a thickness that allows for good adhesion to the semiconductor substrate 217.

その後従来例と同様に基板21を100℃〜400℃に
加熱して真空蒸着法によって第2の電極層となる多結晶
シリコン膜25を形成する。
Thereafter, as in the conventional example, the substrate 21 is heated to 100 DEG C. to 400 DEG C., and a polycrystalline silicon film 25, which will become the second electrode layer, is formed by vacuum evaporation.

この時第2の膜23の側面の多結晶シリコン膜41には
多結晶シリコン膜25が付着形成されないようにする(
同図C)。
At this time, the polycrystalline silicon film 25 is prevented from being deposited on the polycrystalline silicon film 41 on the side surface of the second film 23 (
Figure C).

従って、第2の膜23の側面には薄い多結晶シリコン膜
41のみが形成されることとなる。
Therefore, only the thin polycrystalline silicon film 41 is formed on the side surface of the second film 23.

この様に、蒸着法により多結晶シリコン膜25をCVD
法により多結晶シリコン膜41の後に形成することによ
り、半導体基板21への密着性及び後述する第2の膜2
3のリフトオフが容易になる利点がある。
In this way, the polycrystalline silicon film 25 is deposited by CVD using the vapor deposition method.
By forming the film after the polycrystalline silicon film 41 by the method, it is possible to improve the adhesion to the semiconductor substrate 21 and the second film 2 to be described later.
This has the advantage that the lift-off of step 3 becomes easier.

次に全面を多結晶シリコン膜41の膜厚に等しい分だけ
エツチング除去すれば、多結晶シリコン膜41の第2の
膜23の側面に形成された部分41のみが除去され、第
2の膜23の側面が露出する(同図d)。
Next, when the entire surface is etched away by an amount equal to the thickness of the polycrystalline silicon film 41, only the portion 41 formed on the side surface of the second film 23 of the polycrystalline silicon film 41 is removed, and the second film 23 is removed. The side of the is exposed (d in the same figure).

この状態で、第2の膜23を選択的に除去すれば第2図
eと同様の構造が得られる(同図e)。
In this state, if the second film 23 is selectively removed, a structure similar to that shown in FIG. 2e can be obtained (FIG. 2e).

すなわち、本発明では、蒸着法によって形成された多結
晶シリコン膜25は、全てCVD法によって形成された
多結晶シリコン膜41を介してSiO2膜24中24の
膜21と接しており密着性は極めて高いものである。
That is, in the present invention, the polycrystalline silicon film 25 formed by the vapor deposition method is in contact with 24 of the SiO2 films 24 through the polycrystalline silicon film 41 formed by the CVD method, and the adhesion is extremely high. It's expensive.

1.100°Cの急熱急冷処理を施こしても従来例に見
られる如き蒸着多結晶Si膜25の剥離は観察されず、
著るしく密着性が改善された。
1. Even after performing rapid heating and cooling treatment at 100°C, peeling of the vapor-deposited polycrystalline Si film 25 as seen in conventional examples was not observed.
Adhesion was significantly improved.

尚、こ5では蒸着法によって形成された多結晶シリコン
膜25について説明したが、Mo膜やW膜等に於いても
同様の密着性改善効果が得られる。
Incidentally, although the polycrystalline silicon film 25 formed by the vapor deposition method has been described in this 5, the same adhesion improvement effect can be obtained with a Mo film, a W film, or the like.

以上説明したように本発明を用いれば、従来の半導体装
置の製造に導入され難かった蒸着法による多結晶シリコ
ン膜等の電極層の形成が可能になり、リフト・オフ・エ
ッチ法と組合わせることにより、高温処理工程でもはく
離現象の生じない確実な電極層の形成を行なうことがで
きる。
As explained above, by using the present invention, it is possible to form electrode layers such as polycrystalline silicon films by vapor deposition methods, which have been difficult to introduce into conventional semiconductor device manufacturing, and can be combined with lift-off etching methods. Accordingly, an electrode layer can be formed reliably without peeling even in a high-temperature treatment process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図a ”’−eは従来例を示す構造断面図
、第3図、第4図a ”−eは本発明の各実施例を示す
構造断面図である。 11.21.24・・・・・・S 102膜(第1の膜
)、22.31.41・・・・・・CVD多結晶シリコ
ン膜、23・・・・・・第2の膜、12,25・・・・
・・蒸着による多結晶シリコン膜。
1 and 2 a''-e are structural cross-sectional views showing a conventional example, and FIGS. 3 and 4 a''-e are structural cross-sectional views showing each embodiment of the present invention. 11.21.24...S 102 film (first film), 22.31.41...CVD polycrystalline silicon film, 23...second film, 12, 25...
...Polycrystalline silicon film by vapor deposition.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板上にリフトオフ用の被膜を形成する工程
と、前記被膜のパターンを形成する工程と、前記パター
ン及び前記半導体基板上にCVD法により第1の電極層
を形成する工程と、その後蒸着法により前記第1の電極
層上に前記第1の電極層と同一材料からなる第2の電極
層を形成する工程と、前記被膜の側面が露出する様に前
記第1の導電層をエツチングする工程と、前記被膜を除
去することにより、前記被膜上に形成された第1、第2
の導電層をリフトオフする工程を含むことを特徴とする
半導体装置の製造方法。
1. A step of forming a film for lift-off on a semiconductor substrate, a step of forming a pattern of the film, a step of forming a first electrode layer on the pattern and the semiconductor substrate by a CVD method, and a subsequent vapor deposition method. forming a second electrode layer made of the same material as the first electrode layer on the first electrode layer; and etching the first conductive layer so that the side surface of the coating is exposed. By removing the coating, the first and second layers formed on the coating are removed.
1. A method of manufacturing a semiconductor device, comprising the step of lifting off a conductive layer.
JP14743176A 1976-12-07 1976-12-07 Manufacturing method of semiconductor device Expired JPS5823929B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14743176A JPS5823929B2 (en) 1976-12-07 1976-12-07 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14743176A JPS5823929B2 (en) 1976-12-07 1976-12-07 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5371576A JPS5371576A (en) 1978-06-26
JPS5823929B2 true JPS5823929B2 (en) 1983-05-18

Family

ID=15430156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14743176A Expired JPS5823929B2 (en) 1976-12-07 1976-12-07 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5823929B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0353879Y2 (en) * 1985-09-25 1991-11-26
JPH0479132U (en) * 1990-11-21 1992-07-09

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2538664B2 (en) * 1989-02-28 1996-09-25 沖電気工業株式会社 Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0353879Y2 (en) * 1985-09-25 1991-11-26
JPH0479132U (en) * 1990-11-21 1992-07-09

Also Published As

Publication number Publication date
JPS5371576A (en) 1978-06-26

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