JPS5823678B2 - How to use the warm air conditioner - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction circuit having a self-checking function, and particularly to a circuit that inspects data used in information processing devices, detects errors, and corrects error locations.

Conventional large-capacity storage devices generally include an error correction circuit, that is, a 1-bit error correction circuit and a 2-bit error detection circuit, for the purpose of improving reliability.

FIG. 1 shows a conventional error correction circuit.

In the figure, WDR is a write data register, RDR is a read data register, RCR is a read check pit register,
AO and AI are AND circuits, 01 is an OR circuit, CG is a check bit generation circuit, CK is a check circuit, SY is a syndrome circuit, DEC is a decoder, COR is a correction circuit, ■
0 is an inverter circuit.

In this circuit, when writing, the WR multiplied signal II OII becomes A
ND circuit AO is selected, and as a result, write data is transferred from write data register WDR to OR circuit 01 and correction circuit CO.
It is sent to the check bit generation circuit CG via R.

At that time, a check bit corresponding to the write data is generated from the check bit generation circuit CG, and it is sent to the memory ME.
Written to M.

At the time of reading, the read data is sent from the read data register RDR to the check circuit CK, and the check circuit generates a check bit for the read data.

The check bit is sent to the syndrome circuit SY together with the check bit read from the memory MEM to generate a syndrome.

If there is an error in the read data or check bit, the syndrome is decoded by the decoder DEC,
The error bit is corrected in correction circuit CQR.

In this case, if the check bit generation circuit CG or the check circuit CK has a defect or failure, an erroneous check bit will be written or an erroneous check bit will be generated for read data.

Therefore, in this case, in the conventional circuit as shown in FIG. 1, if a defect causes a syndrome in which a 1-bit error occurs, the error correction circuit COR determines that there is a 1-bit error in the read data or check bit. However, the disadvantage is that error correction is performed.

The present invention has been made in order to overcome the above-mentioned drawbacks inherent in the prior art, and an object of the present invention is to provide a circuit for checking that the error correction circuit is operating normally. The object of the present invention is to provide a new error correction circuit for eliminating erroneous corrections and improving reliability.

The above object of the present invention is to provide a check bit generation circuit that generates a check bit from write data, a check circuit that detects an error from read data, and a check bit generated from the check circuit and a check bit read from a memory. In an error detection and correction circuit having an error check code, that is, a syndrome circuit that generates a syndrome, and a correction circuit that decodes and corrects error bits, the written data or read data is checked as described above during both writing and reading. The circuit includes a gate circuit for sending out data to the bit generation circuit and the check circuit, and a comparison circuit for comparing the outputs of the check bit generation circuit and the check circuit. This is achieved by an error correction circuit having a self-checking function.

That is, the present invention provides a check bit generation circuit that generates check bits from write data and a check bit generating circuit that generates check bits according to read data in a storage device in which check bits for error detection and correction are added to write and read data as described above. If the check circuit that generates has an equivalent circuit configuration,
When writing, the write data is sent to the check bit generation circuit and then to the check circuit, and when reading, the read data is sent to the check circuit and then to the check bit generation circuit, and the outputs of both circuits are compared to check both circuits. It is characterized by performing the following.

Next, a preferred embodiment of the present invention will be explained in more detail with reference to FIG.

FIG. 2 is a block diagram showing an embodiment of an error correction circuit having a self-checking function according to the present invention.

In the figure, CPU is a central processing unit, WDR is a write data register, AO>AI>A2>A3 is an AND circuit, 01 t 02 is an OR circuit, COR is a correction circuit, CG
is a check bit generation circuit, RDR is a read data register, RCR is a read check bit register, CK is a check circuit, SY is a syndrome circuit, DEC is a decoder,
CP is a comparison circuit, MEM is a memory, and IO is an inverter circuit.

In the present invention, the circuit IO and the register WDR are configured so that write data or read data is sent to the check bit generation circuit CG and the check circuit CK during both writing and reading.
, RDR and the correction circuit COR, an AND circuit AOt
Not only is a gate circuit consisting of AI and OR circuit 01 provided, but also an inverter circuit 0, write data register WDR1 read data register RDR, and check circuit C.
AND circuit A 2 t A 3 and OR
A gate circuit consisting of circuit 02 is provided.

Further, a comparison circuit CP is connected to the outputs of the circuits CG and CK so as to compare and check the check bit generated from the check bit generation circuit CG and the check bit generated from the check circuit CK. The output of CP is coupled to memory MEM.

During writing, the write data is held in the write data register WDR, and when II OII is input to WR, the write data is sent to the check bit via the AND circuit AO, A3, the OR circuit 01.02, and the correction circuit COR. It is sent to the generation circuit CG and check circuit CK.

The outputs of the check bit generation circuit CG and the check circuit CK are sent to the comparison circuit CP, respectively.

The check bit generation circuit CG and the check circuit CK have the same circuit configuration, and if both circuits are normal, the outputs of both circuits are equal and the comparison circuit CP determines that the memory M is normal.
Executes writing to EM.

If there is a defect in the check bit generation circuit CG or the check circuit CK, the outputs of both circuits will be different, and the comparator circuit CP will determine that it is abnormal and the comparator circuit CP will Memory MEM by output
Aborts the write operation to.

At the time of reading, the data read from the memory MEM and the check bits accompanying the data are stored in each register RDR, RC.
It is held in R.

When WR is 1111, the read data is sent to the AND circuit AI,
A2, the OR circuits 01 and 02, and the correction circuit COR are sent to the check bit generation circuit CG and the check circuit CK.

The outputs of the check bit generation circuit CG and the check circuit CK are sent to the comparison circuit CP.

The comparison circuit CP determines whether the circuit is normal or abnormal as described above.

When it is determined that it is normal, the output of the check circuit CK is sent to the syndrome circuit SY, and a syndrome is generated by the output of the read check pit register RCR.

If the syndrome is determined to be a correctable error, the syndrome is decoded by the decoder DEC and a correction signal is generated to correct the error bit.

The correction signal is sent to the correction circuit COR to correct the error bit.

The corrected data is again sent to the check bit generation circuit CG to generate a new check bit.

In this case, the judgment of the comparison circuit CP is ignored.

FIG. 3 is a detailed block diagram of the comparator circuit CP and its peripheral parts.

64 bits of data D1 to D64 are input to the check circuit CK and check pit generation circuit CG, and check bits C1 to C8 and C11 are output from those circuits.
-C8/ is shown as an example of 8 bits.

Check circuit CK and check pit generation circuit CGBAH
This is a circuit for generating an amming code, and this H
a mm i ng: For example, please refer to
BMJournal of research and
developmentJuly 1970, Vol.
14, /164'', pages 395 to 400, and these circuits are well known.

The comparison circuit CP is composed of an exclusive OR circuit XOR and an OR circuit QR.

As explained above, the present invention can check the circuit that generates check bits by simply adding a simple circuit to the conventional circuit, thereby preventing erroneous corrections and improving reliability. .

Although the present invention has been described above with respect to one preferred embodiment thereof, it goes without saying that the present invention is not limited only to the embodiment described here.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing a conventional error correction circuit, FIG. 2 is a schematic block diagram showing an embodiment of the error correction circuit according to the present invention, and FIG. 3 is a detailed block diagram of a comparison circuit. . □CPU・・・Central processing unit, MEM・
...Memory, WDR...Write data, data register, RDR...Read data register, RC
R-/shoulder/read check bit register, IO...
...Inverter circuit, AO~A3...AND circuit, 01,02...OR circuit, COR...
・・Correction circuit, CG・・・Check pit generation circuit, CK・・・Check circuit, SY・・・Syndrome circuit, CP・・・Comparison circuit, DEC・
... Decoder, XOR ... Exclusive OR circuit, OR ... Logical sum circuit.

Claims (1)

[Claims] 1. In an error detection and correction circuit that has a check bit generation circuit that generates check bits from write data, a check circuit that detects errors from read data, and a correction circuit that decodes and corrects error pits, and a gate circuit that sends write data or read data to the check bit generation circuit and the check circuit during reading, and a comparison circuit that compares the outputs of the check bit generation circuit and the check circuit. An error correction circuit having a self-checking function, characterized in that the check bit generation circuit and the check circuit are checked based on the output of the circuit.