JPS5823092A - Picture display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure and driving method of a nine-screen GII display device using liquid crystal.

A conventional image display device is shown in FIG. Figure 1 shows a display including an analog signal, which is constructed by combining a liquid crystal and an MOFIT array. In FIG. 1, MOEIf! constitutes a unit pixel. lPE7
1, a signal storage capacitor 2, and a liquid crystal cell 3. Observe this basic operation.

First, a MOB type FICT1iP channel is used, and after a negative pulse voltage as a gate signal is applied to the gate line . When the negative pulse voltage disappears, FF1T1 turns off, but since the leakage current of FIIIT and the current flowing through the liquid crystal cell 3 are usually very small, the voltage proportional to the video signal charged in the capacitor is quite large. The time is maintained and the liquid crystal cell trap continues to be applied. Then, the gate signal is changed from Xl to x++1, xi
+t...... scan line sequentially, and the video signal corresponding to that position is 73,7J+1゜7J+2-...
By applying more power, the overall discontent will be displayed. Second
The figure shows a cross-sectional view of one pixel including lFET, P channel F! l! In the case of T, 4 n-type θ1 substrates, 5 and 6 P+ diffusion I mounds are the source and drain, and the 5 sources are connected in the direction 7J in FIG. 1. C connected in 11 directions with 7 gate oxide films and 8 gate electrodes
Reference numeral 9 forms one electrical contact as a pixel electrode of the liquid crystal cell A, and forms a capacitor between it and the substrate 4 using a thin oxide WII 111. There are 12 liquid crystals and 13 counter electrodes, which are transparent electrodes and serve as a common electrode for the entire screen.

A glass base plate with a surface of 14 points is shown, and a nail film with a 10 point surface is shown.

In such a configuration, the polarity of the voltage applied to the liquid crystal is unidirectional 11, resulting in driving. Therefore, there were major drawbacks in terms of reliability, such as the short lifespan of the liquid crystal. Therefore, in order to eliminate this drawback, the common 1[pole is divided in the row direction as shown in FIG.
+l, X1+2... and common electrode line 5
! 1, X1+1, ff11+2, . . . are synchronized and line-sequentially scanned, and a video signal and a common electrode potential are rotated at the same time to perform alternating current driving. (Japanese Patent Application Laid-Open No. 55-120095). However, in such a method, when displaying, for example, 240×240 pixels, it is necessary to divide the common electrode into 240 parts and connect the circuits, which has the disadvantage that implementation is extremely difficult.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image display device that can be driven by AC and is easy to implement.

The present invention will be explained below with reference to the drawings.

FIG. 4 shows an example of the structure of the display lid of the present invention.

MO8 type FHiT1. Signal storage capacitor 2. The liquid crystal cell 5 is the same as the conventional one, but the common pole line is common to several rows, and FIG. 4 shows an example in which one common 11 pole line is provided for one gate signal line. This is an indication.

Therefore, in the example of FIG. 4, there are i/i common electrode lines equal to the number of gate lines, that is, the number of lines in the row direction of pixels.

FIG. 5 is a block diagram showing an embodiment of the present invention including a peripheral drive circuit.

15 is a vertical synchronizing signal input terminal, and 16 is a frequency dividing circuit.

17ij T-type flip-flop (JJ lower T-F
18#-i video signal input terminal, 19 a video signal inversion circuit, 20 a sample hold circuit that samples the video expansion signal and sends it to each signal line, 21 clock signal input terminal, 22Vi row direction (X direction) This is a clock input terminal for the shift register, and a horizontal synchronization signal is actually input thereto. 23\'ix direction shift register, 24
Vi horizontal synchronization signal input terminal, clock generation port for 25 common electrode shift registers.

This is a 26Vi common W pole shift register. Division number 1i
The output of F16 (D output ViT-F F17, quake clock generation circuit for common tei shift register, input to shift register 26 for common electrode fi, T-FF1) is input to video signal inversion circuit 19, and is input to video signal inversion circuit. 19
The output is input to the sample hold circuit 20. The sample and hold circuit 20 has j signal lines (y+ to 7
J) is connected. In this example, the X direction shift register 23 has 41 gate signal lines (XI to x41
) are connected.

The clock generation circuit for the common electrode shift register and the clock generation circuit 25 for the common electrode shift register include a frequency dividing circuit 1.
6 and the horizontal synchronization signal are input, the output of the common electrode shift register clock generation circuit 25 is input to the common electrode shift register 2B, and its output is connected to the divided common 11 frames M4 to z4. . In the example shown in FIG. 5, the number of divisions of the common 9L pole is 4, but the number of divisions may be any number as long as it is 2 or more.

FIG. 6 is a time chart of the circuit of FIG.
Perform the movement according to Figure 6. a is a vertical synchronization signal, and its period (JJ, abbreviated as τV below) is approximately 16.7
It is m5ec. 'b#'i frequency divider circuit 160 is a frequency divider circuit, and in the example of FIG. 6, it is a 1/4 frequency divider circuit. Therefore, one pulse for every four pulses of the vertical synchronizing signal a is output as a frequency-divided pulse. As a reminder, the number of frequency divisions can be selected completely independently of the number of divisions of the common electrode shown in FIG. For example, in the example shown in Figure 5, the number of divisions of the common electrode is 4,
The number of divisions is 2.5, 4. Any number of... is fine. However, the number of divisions of the common electrode (hereinafter abbreviated as N) and the number of frequency divisions of the vertical synchronizing signal (hereinafter abbreviated as X) are determined only by the sharpness of the screen. I will discuss this later in the article. By inputting the frequency-divided output signal to the T terminal of the T-FF 17, 1 and 0 are inverted as shown in the output signal C.

The polarity of the video signal d is not inverted, but when it passes through the video signal inversion circuit 19, the video signal is periodically inverted as shown in 8. Its control is performed by the TFF output C.

That is, the 1.0 period of the T-FF output C in FIG. 6 is a period in which the polarity of the video signal d is not inverted, and the period ts is a period in which the polarity is inverted. This periodically inverted video signal θ is input to the sample hold circuit 20 and sampled by the clock signal input from the clock input terminal 21, and the sampled signal is transmitted to the signal lines y1 to y7.
sent to j. This is a pulse that starts the operation of the 1fij direction shift register, and its period is the same as the vertical synchronization signal. It is the clock signal for the gkix direction shift register, and usually uses the horizontal synchronization signal. Therefore, its period is approximately 655 μ crown.The output of the X direction shift register is “1mxlp...” by the clock signal g.
Outputs primary pulse. “1 #”* *・ in Figure 6
The X line is selected only while the negative pulse of . This pulse is generated by the hFi common shift register clock generation circuit 25, and is generated from the clock signal g when frequency-divided and output. In the embodiment shown in FIG. 6, the common electrode is divided into four parts, and the divided output bll''j
Since it is obtained by dividing the vertical synchronization signal four times, four clock pulses are output during the first field of the edge where the pulse of the frequency division output is input, and during the fifth field after crucible. does not output pulses. Therefore, a total of four pulses f7rltl are applied during the period tH (or ts).

When the number of frequency divisions is different and the number of times of pollution 11 of the common TR bar is the same, the waveform of the clock h is different.

An example of this is shown in FIG. In Figure 7, the number of divisions is 2,
This is a case where the number of divisions of the common electrode is four. The number of divisions of the common W pole, 4, remains the same, but since the number of divisions is 2, four clock h K ld pulses are output every two fields. Now, returning to FIG. 6, since the clock h is the clock for the common w-pole shift register 26, the common electrodes (z1 to Z,) reverse their polarities every time a pulse is output to the clock h.

Here, the reason why the polarity of the common electrode is inverted in synchronization with the inversion of the contact column of the video signal will be explained with reference to FIG. Figure 8 (a
) is a method of AC single motion that has already been proposed. That is, the common electrode is set to a constant value (v).

level), and the polarity is inverted to positive and negative on both sides of the video signal 'f-Vo level. [7] However, with this method, the dynamic range of the video signal can only be obtained by less than half of that of the power supply WFE, and in order to obtain sufficient contrast, it is necessary to set the power supply voltage considerably high, which is wasteful in terms of power consumption.

Therefore, as shown in Figure 8(b), the polarity of the video signal is inverted,
Use the same dynamic range for inverted video signals and share them at the same time! One possible method is to invert the color orange between VOH and VOL. This is the reason why the common electrode is switched at the same time as the video signal is inverted.

Next, the relationship between the number of divisions (N) of the common electrode and the number of divisions (K) of the vertical synchronization signal will be described, and the minimum required number of divisions will be described. The number of divisions is determined by the image quality, and the following values can be considered as the important value of image quality.

Here, τP is the time during which the image is displayed in a positive manner, and τN is the time during which the image is displayed in a negative manner, that is, the time when black and white appear to be reversed. According to the invention the gate line (xl)
The common 11% corresponds to one for multiple lines, but according to this method, the reversal timing of the common tri,
Which gate line among multiple gate lines is O?
Depending on the timing of whether the gate line becomes N, the ratio of the time of positive display to negative display for each gate line varies. For example, if the common electrode is inverted in accordance with the timing when the gate line in the first row is turned on, when one gate line is common, the first gate line will have the highest proportion of negative display.

In the method of the present invention, in which the number of common electrodes is reduced by combining the common electrodes by the number of opposing first '#I poles, it is unavoidable that a negative display is displayed for a certain period of time, but if the positive display period is sufficiently long. There is no problem at all in terms of image quality.

The g value is a value that quantitatively evaluates the image quality, but a=
−1 digit τ = 0, that is, always negative display, α = 0 digit τP
= τN, the screen turns gray, and α=1 means τN=0
indicates that the screen is always displayed normally. Therefore, it can be said that the closer the value is to 1, the better the image quality is, but it does not have to be 1, and we have confirmed that the image quality is sufficient if it is ♂ or ♂ (19). There is. Figure 9 shows the number of common electrode divisions N using the number of frequency divisions K as a parameter.
It shows the relationship between and α. Vertical synchronization signal period” 7
Since the frequency is m (60 Hz), the period of the divided output in Figure 6 is 314 mnet (30 Hz), and the period of K = 2r and the divided output of h is 66.8 m5ec.
(This means that there is a 15 Hz bias. In other words, the larger K is, the longer the inversion period of the video signal becomes.As can be seen from Fig. 9, since a-≧α9, N=5
If: 4, if N=4 = 3. . . . This indicates that the smaller the number of divisions of the common electrode, the longer the inversion period of the video signal may be (that is, the larger the value of K). Another way to express this n' is as shown in Figure 10. Figure 10 shows N and KO where α≧[19 or more]
This is a diagram showing the quantity relationship, and the hatched area in the diagram is the area where α≧0.9 and sufficient image quality can be obtained. For example, N is an example of the practical common electrode division number.
=4 indicates that it is sufficient if the inversion period is 3≦3, that is, the frequency of the vertical synchronizing signal is divided by ⅓. The number of divisions N of the common electrode has a great influence on mounting. If the common electrode is divided into each line, approximately N=200 is required, depending on the number of images, and implementation is extremely difficult. However, as in the present invention, by inverting the video signal not every field but once every several fields, N-2~
Sufficient image quality can be obtained even with a value of about 10. If 1J=2 to 10, there will be no problem in terms of implementation.

The calculated values of it in FIGS. 9 and 10 are just examples, and the value of a varies slightly by changing the timing of reversal of the common electrode. In other words, one line of palm-f that rotates all one pair of reversal timings.
If it is set around the center of r'VII, the g value for the same value of N becomes even larger, and the image quality improves.

As described above, the present invention divides the common electrode into several parts, divides the frequency of the vertical synchronizing signal, and performs video signal switching and line-sequential inversion of the common electrode in accordance with the frequency-divided output. This has the great effect that sufficient image quality can be obtained even if the number of divisions is extremely reduced, and implementation is extremely easy.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional image display device, Fig. 2 is a cross-sectional view of a display pixel, Fig. 5 is a circuit diagram of a conventional image display device in which the common electrode is divided, and Fig. 4 is a circuit diagram showing the present invention. 5 is a block diagram of the present invention including peripheral drive circuits, FIG. 6 is a time chart of one embodiment of the present invention, and FIG. 7 is another embodiment of the present invention. 8(a) is a waveform diagram of the conventional AC drive, FIG. 8(b) is a waveform diagram of the AC drive of the present invention, and FIG. 9 is the frequency division number K of the vertical synchronization signal (i.e., FIG. 10 is a graph showing the relationship between the common electrode and α using the signal inversion period as a parameter. 5...Display pixel 4...N-type 81 substrate 5.6...1° diffusion region 7...
Gate oxide film 8...Gate electrode 9...
・10,000 pixel electrodes 10 of a liquid crystal cell...Insulating film
11... Amazing oxide film 12... Liquid crystal
15... Common electrode 14... Glass substrate 15... Vertical synchronization signal input terminal 16... Frequency divider circuit 17... T type flip-flop 18
......Video signal input terminal 19...Video signal inversion circuit 20...Sample bold circuit 21...
・Clock input terminal 22...Clock input terminal 25...Shift register 24...Horizontal synchronization signal input terminal 25...
・Clock generation circuit 26 for common electrode... Shift register for common electrode and above Applicant Daini Seikodai Co., Ltd. Agent Patent attorney Tsutomu Mogami jI3 Figure 0 ------------- -1-Figure 8 (I)
) Figure 9~-→- Figure 10-Th

Claims (1)

[Claims] Field effect transistors are formed in a matrix on a semiconductor layer formed on an insulating substrate such as glass or on a semiconductor substrate, one terminal of the field effect transistor is used as a first electrode, and a liquid crystal is placed on the second electrode. In the Kugarun display device, the transparent electrode on the transparent substrate installed through the transparent electrode is used as the second electrode.
The second electrode is divided in the row direction with a width opposite to the first electrode of the number rows, and includes means for inverting the effect of the video signal applied to the first electrode; and a circuit for frequency dividing a vertical synchronizing signal of the video signal, inverting the polarity of the video signal at a period determined by the output of the vertical synchronizing signal frequency dividing circuit, iii. The salary display device is characterized by having a means for sequentially inverting the polarity of the second electrode at the same time.