JPS58224485A - Device for recording and reproducing information of video tape recorder - Google Patents

Abstract

PURPOSE:To use control pulses to multiple purposes and to expand the function of the titled device, by recording the duty of control pulses every number of pulses corresponding to information and decoding a counted value in every number of pulses at the time of reproducing. CONSTITUTION:The duty of recording control pulses in every number of pulses corresponding to the information is changed by monostable multivibrators 13, 14 or the like and recorded in a counter 22 of which counted information can be optionally changed. At the time of reproducing, the pulse interval of the control pulses is measured by the monostable multivibrator 13 to detect the control pulses having different duty and the interval of control pulses having different duty is counted by an FF circuit 29, the counter 22, etc. to decode the counted value. Consequently, the pulse duty changing cycle information of the control pulses can be used as various information.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to an information recording and reproducing device for a video tape recorder.
It is a device that makes it possible to utilize control pulses, etc., which are used for multiple purposes. The disk servo circuit for the head motor and the capstan servo circuit for the capstan motor are designed so that the rotational frequency of the head °, the rotational frequency of the capstan that determines the tape running speed, and the synchronization signal frequency of the recording video signal have a predetermined relationship. It is provided. In the recording mode of the VTR, in the disk servo circuit, the rotational frequency of the rotating video head and the vertical synchronization signal of the recording video signal have a constant phase relationship. l: Controls the sea urchin-rad motor. Also, the capstan servo circuit now controls the capstan motor so that the running speed of the magnetic tape is constant and stable. Further, during the recording operation of the VTR, a half frequency control pulse of the vertical synchronizing signal separated from the recording video signal is recorded in R on the control track of the magnetic tape by the control head. Therefore, the rotation of the rotating video head and the running of the tape are 1. 1nlt+i phase and the control pulse phase.

- During the playback operation of the force V T 'R, the rotating video head is controlled by a disk servo circuit so as to have a stable and constant rotation frequency. The Capnutan servo circuit takes as input information the reproduced control pulse recorded on tape-E and the rotation pulse of the rotating video head, and adjusts the reproduction control pulse and the rotation pulse of the rotating video head to a desired phase. The capstan motor is controlled so that the tape speed is controlled.

As shown in item L, the control pulse is used as tape position information for the servo system during VTR playback operation, but this signal (i) is normally recorded on tape 7 with m° negative saturation. During the V']'R regeneration operation, the sound is reproduced as positive and negative pulses corresponding to the rising and falling edges, but what is used in the servo system is the city pulse that corresponds to the rising edges. Therefore, the negative pulse f corresponding to the falling edge is not used at all.

[Purpose of the invention]

This invention takes advantage of the unused portion of the control pulse signal as indicated by L, and by changing the duty of the control pulse signal, various types of information, such as recording signals, can be processed. To provide an information recording and reproducing device for a video tape recorder that creates and records channel information, date information, etc., decodes the duty information at the time of reproduction, and allows multi-purpose use of control pulse signals. With the goal.

[Summary of the invention]

In one example of the present invention, a counter 22 whose count information can be arbitrarily changed is used to set the duty of the recording control pulse for each number of monostable multivibrators 1, ? , 74, etc., and during reproduction, the monostable multivibrator 13 measures the pulse interval of the control pulses to detect control pulses with different duties, while the flip-flop circuit 29, counter 22, etc. The number of different control pulses present is counted and the counted value is decoded.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. 1st
The figure shows one embodiment of the present invention, and the operation system when the VTR is in recording operation will be explained first. A vertical synchronizing signal (Vs
ync) is input. This flip-flop circuit 11
The pulse frequency-divided by 4 is derived as a reference pulse for the servo circuit, and is input to the first monostable multivibrator circuit 13 via the NAND circuit 12a, I:lc that constitutes the gate circuit 12. , is applied to the @1 input terminal of the NAND circuit 21a constituting the gate circuit 21. The previous gate circuit 12 is a NAND circuit 12
a, 12b.

Consisting of 12C1 inverter 12d, VTR
When in the recording operation, the input level of the inverter 12d becomes low level, so the output of the flip-flop circuit 11 is outputted via the NAND circuits 12a and 12c. When the VTR is in playback operation, the input level of the inverter 12d is high level, and the NAND circuit 12b is output.

The path of 12C becomes conductive. Further, the gate circuit 2 includes NAND circuits 21a, 21b, 21c, and an inverter 21.
When the VTR is in recording operation, the input level of the inverter 21d becomes a low level, and the paths of the NAND circuits 21a and 21C become conductive.
When the VTR is in playback mode, the inverter 21d
The input level of becomes high level, and the NAND circuit 21b,
The path 21C becomes conductive.

The first monostable multivibrator circuit 13 and the second monostable multivibrator circuit 14 obtain outputs with a pulse duty of 40% and 10% of the vertical synchronization signal period, respectively, after the pulse is input. Then, this is synthesized by the NAND circuit 15 to make a 50% duty pulse,
It can be added to the pace of the transistor Tr via the resistor 16. First monostable multivibrator circuit 13
The output of is applied to one input terminal of the NAND circuit 15 and also to the input terminal of the second monostable multivibrator circuit 14. Here, the second monostable multivibrator circuit 14, after the heka pulse is applied,
It is set to obtain a pulse having a pulse width of 10% of the vertical synchronization signal period, and its output is applied to the other input terminal of the NAND circuit 15.

Further, the first monostable multivibrator circuit I3 is connected to VT
The time constant is switched between R recording operation and i raw operation poem, and during recording operation, the vertical synchronization signal period is 4
It is set to obtain a pulse having a pulse width of 0% and 105% during a reproducing operation.

Next, the counter 22, to which the output of the gate circuit 21 is added to the clock input terminal, is an up counter, and its counted number can be preset from the preset terminal 22B. The counter 22 counts pulses from the gate circuit 2J according to a preset value,
A carry CRY output is obtained, which is transferred to the flip-flop circuit 2.9 a that forms the load pulse generation circuit 23.
In addition to the above-mentioned second data input terminal,
is applied to the operation stop control terminal CD of the monostable multivibrator circuit 14.

As a result, the second monostable multivibrator circuit 14 is stopped at the repetition period of the count value of the counter 22 (corresponding to the preset value). When the second monostable multivibrator circuit 14 is stopped 17, the one-malus duty applied to the output of the NAND circuit 15 means that 10% of the pulse of 50% of the vertical synchronization signal period is reduced. Nando circuit 15
The output can turn on and off the transistor Tr constituting the control pulse recording circuit 17. 1st. Second monostable multivibrator circuit 1.9,1
4 is in normal operation, these two circuits provide a control pulse with a duty of 50% of the vertical synchronizing signal period, which is recorded by the control head 18. The fact that the operation of the monostable multi-pie break circuit 14 is stopped means that 1
Since the 0% portion is reduced, the regular period of the control pulse is recorded with a duty of 40%.

That is, this means that the carry CRY from the counter 22
When is output, it means that the pulse width of the recording control pulse has been varied.

After the signal IJ-CRY is output, the counter 22 receives a load pulse from the load pulse generation circuit 23 and starts counting the output pulses from the gate circuit 21 again. In this case, the load pulse generation circuit 2.9 is a flip-flop circuit 2.9 a, 2, ? b
, NAND circuit 23C5 inverter 2.9d, etc., create a load pulse for obtaining the next counting operation.

FIG. 2 is a timing chart showing the control pulse generation operation during the V'rR recording operation.

@2 Figure (8) shows the vertical synchronization signal (Vsync)17
, the same figure (bl indicates the output pulse θF11 of the flip-flop circuit 11. This output pulse θF71 becomes the clock of the counter 22.
$1. Second monostable multi-pie break circuit 1,?
, l 4 outputs MMIθ and MM2θ, each output is 40% of the vertical synchronization signal period.

It is 10%. FIG. 2(e) shows the transistor T
This is the base input pulse of r. In the case of this timing chart, the preset input of the counter 22 is (16
-N) This shows the case where N=10 is set.

Therefore, for one force kunta 22, six pulses θFll
When is input, the carry IJ-CRY shown in FIG. 2(f) is obtained, and when this carry CRY is obtained, the pulse width of the base human pulse of the transistor Tr is varied. In this operation, unless the preset value is changed, the pulse width will be varied every time six pulses are counted.

In other words, as shown in FIG. 2(e), the control pulse is recorded with the pulse duty varied every seventh control pulse. In this way, when recording while changing the pulse duty of the control pulse, for example, if the recorded program is for 6 channels and V channels, the counter 2
The preset value for 2 is N=10, for 8 channels, N=8, for 10 channels, N
By setting -6, it is possible to associate the recording number with the number of pulse duty takers of the control pulse being varied. Second
1q(gl, (h), (1) is a carry CRY
From when is input until the load pulse is obtained,
Flip-flop circuits 23a, 23b, NAND circuit 2
．． This is the output obtained from 9c.

Next, the case of reproducing the control pulse recorded as described above will be explained. The control pulses reproduced by the control head 18 are amplified and waveform-shaped by a regenerative amplifier 25, and are applied to a servo circuit or cueing circuit, as well as to a clock and reset pulse generation circuit 26. Furthermore, the reproduction control pulse is sent to @1 via the inverter 27 and the gate circuit I2.
monostable multivibrator circuit 13.

Here, the first monostable multivibrator circuit 13 is
During playback operation of the VTR, the time constant is changed, and from the rising edge of the input pulse to the vertical synchronizing signal period of 105
If there is an input pulse again during a period corresponding to 105%, the output MMIθ will not be obtained, and if there is no input pulse after a period of 105% or more, the output MMI
It is set to obtain Mxθ. Furthermore, when the VTR is in playback mode, the gate circuit 12 operates as a NAND circuit J, ? The paths on the b and 12c sides are set to conductive states, and in the gate circuit 21, a NAND circuit;
The paths on the llb and 21C sides are set to be conductive.

FIG. 3 is a timing chart showing the control pulse reproducing operation during the reproducing operation of the VTR. Third
The figure (red) is a result of differentiating the pulse rising edge and falling edge of the reproduction output from the control head 18. FIG. 3 (bl is the output whose waveform has been shaped by the regenerative amplifier 25, and this output is passed through the inverter 27 and the gate circuit 12 to the first monostable multi-pie break circuit 1.
3 is input. It is also input to the clock and reset pulse generation circuit 26, and is input to the flip-flop circuit 29.
In addition to creating a reset pulse for the NAND circuit 3
1. A clock is generated to be applied to the counter 22 via the inverter 32 and the gate circuit 21.

That is, this clock and reset pulse generation circuit 26 includes flip-flop circuits 26m and 26b.

26C1 NAND circuit 26d, 26e, inverter 2
6f, and from the impark 26f, a clock for the counter 22, a NAND circuit 26e
A reset pulse for the flip-flop circuit 29 (:) can be obtained from FIG. 3(C),
(di, fe) is the flip-flop circuit 26a
, 26b, 26c, each output θT"26a, θF26
bθF26c, and (f) and (g) in the figure are the outputs of the NAND circuits 26d and 26e, respectively.

When the flip-flop circuit 29 is reset by the output of the NAND circuit 26e, its reset output is
17, the NAND circuit 31 is in a conductive state, the NAND circuit 26d,
The pulses obtained through the inverter 26f and I7 are used as a clock for the counter 22.

On the other hand, for the monostable multivibrator circuit 1.1, as shown in FIG.
enters. This is to make the relationship between the rising edge and the falling edge of the pulse of the reproduction control signal to be in a phase relationship opposite to that during recording.

When adjusting the pulse duty and recording, the rising ()f phase is fixed when changing the pulse duty.1. and set the falling phase to 1.
However, during reproduction, the monostable multivibrator circuit 13 operates on both the rising and falling pulses, so the inverter 27 is used to change the rising and falling phases of the pulse.

If there is no change in the pulse duty of the pulse MMIN manually input to the first monostable multi-by-break circuit 13, this will occur because there is one rising pulse of the next pulse before 105% of one vertical period has elapsed. No output is obtained from the first monostable multiver f-breaker circuit 13. However, if the pulse duty force of the control pulse is "]'&, as shown in FIG. Therefore, the next pulse input
- 105% of one vertical synchronization signal period has elapsed by the time the signal returns, and an output pulse as shown in FIG. 3(i) is obtained. This means that it has been detected that the pulse width of the control pulse has been varied.

When an output pulse, a so-called detection pulse i4, is generated from the first monostable multi-bi break circuit I3, this detection pulse is applied to the set input terminal of the above-mentioned flip-flop circuit 29 via the inverter 28. When this flip-flop circuit 29 is set, the NAND circuit 3
1 becomes non-conductive, and no clock is input to the counter 22. Further, the set output of the flip-flop circuit 29 is applied to the decode sequence pulse generation circuit 33. The decode sequence pulse generation circuit 33 is a flip-flop circuit, 9.9 a, ? , 9 b
, 3.9 c, NAND circuit 33d.

, 9.9 e, etc., and the set output from the flip-flop circuit 29 (FIG. 3(j)) is connected to the flip-flop circuit 93a (Q data input terminal).
) is added. Decode sea 17 y pulse generation circuit, each flip-flop circuit of 73, 9.9 a,
, 9.9 b , , 9.9 c are shown in Figure 3 (1).

6n), as shown in (n), and the NAND circuit 3.
9d.

, from 93e, @ 319 (o), ip)
A -y pulse and a clear pulse as shown in the figure are obtained. The latch pulse output from the NAND circuits 3 and 9d is applied to the latch pulse input terminal of the latch circuit 35 via the inverter 34. The latch circuit 35 latches the count contents of the counter 22 when a latch pulse is input. Further, the clear pulse outputted from the NAND circuit 3, 9e is applied to the clear pulse input terminal of the counter 22 through the inverter 36, and the contents of the counter 22 are cleared. The contents of the latch circuit 35 are decoded by a decoder 97,
For example, it is added to the display means.

After the counter 22 is cleared, the NAND circuit 3
The pulses output from the NAND circuit 3 (shown in FIG. 3 (k+)) are counted.Then, the output pulses from the NAND circuit 3 are counted until the next pulse duty change detection pulse is obtained. As shown in the figure, when the counter 22 is designated as N-10, if the recording tape is played 411 times, pulses with different duties can be detected every six pulses. is set to obtain the maximum count.

” - According to this circuit, during the playback operation of the VTR, it is possible to know how many times the pulse duty is changed for the control pulses recorded on the tape, and the latch circuit By decoding the contents of the latch 35, the display means can display, for example, what channel the program is currently being played on.

The information recording/reproducing apparatus according to the present invention can use the pulse duty change cycle information of the control pulse as various types of information.

In the above embodiment, the count content of the counter 22 is set to correspond to the channel of the program, but it can also be set to correspond to the recording date. For example, counter 2
When a latch pulse is obtained when the content of 2 is 1,
If the data is decoded as the first day, if 1 niratch pulse is obtained at 2, it is the 2nd day, and if 1 niratch pulse is obtained at 3, it is the 3rd day, and so on, it can be made to correspond to the recording date. This can also be used to record a sumo wrestler's efforts from the first day to the 15th day.

〔Effect of the invention〕

As described above, according to the present invention, the control pulse used in the video tape recorder can be used for various types of information, thereby making the information recording and reproducing device for the video tape recorder multipurpose and expanding the functions of the device. Can you provide?

[Brief explanation of the drawing]

Fig. 1 is an explanation of the configuration showing one embodiment of the present invention) Fig. 2 (a) to 0) and Fig. 3 (a) to (p) are the first embodiment of the present invention.
FIG. 3 is an operation signal waveform diagram of the circuit shown in the figure. 12.21... Gate circuit 13, 74... Monostable multi-bi break circuit 17.
Control pulse recording circuit 18 Control head 22 Counter 23 Load pulse generation circuit 25 Regenerative amplifier 26 Clock and reset pulse generation circuit 29
・Flip-flop circuit

Claims (1)

[Claims] Information input means for inputting information for controlling the control pulses (11); means for changing the duty of the recording control pulses for each number corresponding to the information input by the information input means; and inter-pulse heat of the reproduction control pulses. means for measuring control pulses whose duty has been changed, and counting how many control pulses whose duty has been changed exist, and calculating the counted value corresponding to the information. 1. An information recording and reproducing device for a video tape recorder, characterized in that it is equipped with means for decoding.