JPS58222673A - Signal switching controller of television receiver - Google Patents

Signal switching controller of television receiver

Info

Publication number
JPS58222673A
JPS58222673A JP57105906A JP10590682A JPS58222673A JP S58222673 A JPS58222673 A JP S58222673A JP 57105906 A JP57105906 A JP 57105906A JP 10590682 A JP10590682 A JP 10590682A JP S58222673 A JPS58222673 A JP S58222673A
Authority
JP
Japan
Prior art keywords
signal
circuit
control signal
output
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57105906A
Other languages
Japanese (ja)
Other versions
JPH026470B2 (en
Inventor
Yutaka Miki
豊 三木
Mitsuo Okawa
光雄 大川
Toshiro Nozoe
野添 敏郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57105906A priority Critical patent/JPS58222673A/en
Publication of JPS58222673A publication Critical patent/JPS58222673A/en
Publication of JPH026470B2 publication Critical patent/JPH026470B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To decrease number of pins in circuit integration, by superimposing two signals; a gain control signal and a switching signal. CONSTITUTION:A signal inputted from a control signal input terminal 10 is separated at a control signal separating circuit 9, an output of the control signal separating circuit 9 is inputted to a gain control circuit 6 and another output is inputted to a switching circuit 3. As a result, an output obtained at an output terminal 5 is an output where the level of the television signal around characters and graphs in case of superimposing display is suppressed, allowing to make the characters and graphs easy to see on a picture played on a CRT.

Description

【発明の詳細な説明】 本発明はテレビジョン受像機の信号切換え制御装置に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal switching control device for a television receiver.

テレビジョン受像機において、複数種類の信号を切換え
て一画面に映出する場合がある。−例として文字放送受
信機の場合をとシあげる。従来のテレビジョン放送を受
信して得られる信号をテレビジョン信号、文字放送を受
信して得られるディ・ジタル信号を文字信号ということ
にする。
In some television receivers, multiple types of signals are switched and displayed on one screen. - Let's take the case of a teletext receiver as an example. The signal obtained by receiving conventional television broadcasting will be called a television signal, and the digital signal obtained by receiving text broadcasting will be called a text signal.

文字放送受信機の映出モードとして文字信号とテレビジ
ョン信号を切換えて映出するスーパー表示がある。−こ
の場合、文字信号を見やすくするために、文字信号の周
囲のテレビジョン信号のレベルを下げて映出することが
ある。すなわち、利得゛ 制御信号を入力した時のみテ
レビジョン信号のし “ベルを下げる利得制御回路を用
いてテレビジョン信号を映出する。さらに同じ文字放送
受信機において、切換信号の入力レベルによって文字信
号とテレビジョン信号を切換える切換回路が使用される
As a display mode for teletext receivers, there is a super display mode in which a text signal and a television signal are switched and displayed. - In this case, in order to make the character signal easier to see, the level of the television signal surrounding the character signal may be lowered and displayed. In other words, the television signal is displayed using a gain control circuit that lowers the level of the television signal only when the gain control signal is input.Furthermore, in the same teletext receiver, the character signal is displayed depending on the input level of the switching signal. A switching circuit is used to switch between the television signal and the television signal.

このように、利得制御信号と切換信号の2つの信号を用
いてスーパー表示を行なうと、画面に映出された文字信
号は見やすくなるが、文字放送受信機内部の回路におい
て、利得制御信号と切換信号の2信号を用いるため、利
得制御信号と切換信号のそれぞれの入力端子が必要とな
り、IC化した場合にピン数が増えてコストが上がると
いう欠点を持つ。
In this way, when super display is performed using two signals, the gain control signal and the switching signal, the character signal projected on the screen becomes easier to see, but in the circuit inside the teletext receiver, the gain control signal and the switching signal are Since two signals are used, input terminals are required for each of the gain control signal and the switching signal, and when integrated into an IC, the number of pins increases and the cost increases.

本発明は以上の点に鑑み、前記利得制御信号と切換信号
の2つの信号を重畳することにより、特にIC化の場合
に有利となるような手段を与えることを目的とするもの
である。
In view of the above points, it is an object of the present invention to provide a means that is particularly advantageous when integrated into an IC by superimposing two signals, the gain control signal and the switching signal.

第1図は従来例を示すブロック図である。第1図におい
て、1はテレビジョン信号入力端子1.2は文字信号入
力端子、3は切換回路、4は切換信号入力端子、5は出
力端子である。テレビジョン信号入力端子1から入力さ
れたテレビジョン信号と、文字信号入力端子2から入力
された文字信号とは切換信号入力端子4から入力された
切換信号により切換回路3で切換えられ、出力端子6に
出力される。第1図の構成では、スーパー表示のとき、
CRT上で文字・図形信号が見にくくなるという欠点を
持つ。
FIG. 1 is a block diagram showing a conventional example. In FIG. 1, 1 is a television signal input terminal, 2 is a character signal input terminal, 3 is a switching circuit, 4 is a switching signal input terminal, and 5 is an output terminal. The television signal inputted from the television signal input terminal 1 and the character signal inputted from the character signal input terminal 2 are switched by the switching circuit 3 by the switching signal inputted from the switching signal input terminal 4, and the output terminal 6 is output to. In the configuration shown in Figure 1, when in super display,
It has the disadvantage that text and graphic signals are difficult to see on a CRT.

第2図は第1図の回路に利得制御機能を持たせた場合の
ブロック図である。第2図において、1〜5は第1図に
おいて述べたものと同じであるので、ここでの説明は省
略する。第2図において、6は利得制御回路、7は利得
制御信号入力端子、8は利得制御回路6の出力端子であ
る。この第2図において、テレビジョン信号入力端子1
から入力されたテレビジョン信号は、利得制御信号入力
端子7から入力された利得制御信号に従ってレベルを下
げられ、切換回路3に入力される。その結果、出力端子
5に得られる出力は、スーパー表示    ゛の場合”
には、文字・図形信号の周囲のテレビジョン信号のレベ
ルが下げられた出力となるため、CRT上に映出された
画像では文字・図形が見やすくなる。
FIG. 2 is a block diagram of the circuit shown in FIG. 1 provided with a gain control function. In FIG. 2, numbers 1 to 5 are the same as those described in FIG. 1, so their explanations will be omitted here. In FIG. 2, 6 is a gain control circuit, 7 is a gain control signal input terminal, and 8 is an output terminal of the gain control circuit 6. In this figure 2, television signal input terminal 1
The level of the television signal inputted from the switch circuit 3 is lowered in accordance with the gain control signal inputted from the gain control signal input terminal 7, and then inputted to the switching circuit 3. As a result, the output obtained at output terminal 5 is super display.
In this case, the level of the television signal surrounding the text/figure signal is lowered, so the text/figure becomes easier to see in the image projected on the CRT.

しかし、この第2図の構成では、切換信号入力端子4と
利得制御信号端子7の2つの異なる端子が必要であるた
め、例えばIC化を行なう場合には、ピン数が2個必要
となり、コストが高くなるという欠点を持つ 本発明は上記の欠点を除去することを目的としたもので
ある。
However, in the configuration shown in FIG. 2, two different terminals, the switching signal input terminal 4 and the gain control signal terminal 7, are required, so when converting to an IC, for example, two pins are required, which increases the cost. The present invention, which has the disadvantage of high energy consumption, is aimed at eliminating the above-mentioned disadvantage.

第3図に本発明の一実施例のブロック図を示す。FIG. 3 shows a block diagram of an embodiment of the present invention.

同図において、1〜7は第1図および第2図と同じもの
である。9は制御信号分離回路、10は制御信号入力端
子である。制御信号入力端子1oから入力された制御信
号は、制御信号分離回路9で分離され、制御信号分離回
路9の出力は、一つは利得制御回路6に入力され、もう
一つは切換回路3に入力される。その結果、出力端子6
に得られる出力は、スーパー表示の場合には、文字・図
形′ 信号の周囲のテレビジョン信号のレベルが抑圧さ
れた出力となり、CRT上に映出された画像において、
文字・図形が見やすくなるという優れた点を持つのは、
第2図の場合と同様である。
In the figure, numerals 1 to 7 are the same as in FIGS. 1 and 2. 9 is a control signal separation circuit, and 10 is a control signal input terminal. The control signal input from the control signal input terminal 1o is separated by the control signal separation circuit 9, and one output of the control signal separation circuit 9 is input to the gain control circuit 6, and the other is input to the switching circuit 3. is input. As a result, output terminal 6
In the case of super display, the output obtained is an output in which the level of the television signal surrounding the character/figure signal is suppressed, and in the image projected on the CRT,
It has the advantage of making characters and figures easier to see.
This is the same as the case in FIG.

次に、第3図の制御信号入力端子1oに入力される制御
信号の具体的な一例を第4図に示す。第4図において、
制御信号レベルが0からvlの間はテレビジョン信号は
そのまま伝送されて出力端子5に出力され、制御信号レ
ベルがv1〜v2の間はテレビジョン信号のレベルが下
げられて出力端子6に出力され、制御信号レベルが72
以上の場合は文字信号が出力端子5に出力されることを
示す。制御信号レベルが72以上の場合には、出力端子
5に文字信号が出力されるだめ、テレビジョン信号の利
得制御はどのようであってもかまわない。
Next, FIG. 4 shows a specific example of the control signal input to the control signal input terminal 1o of FIG. 3. In Figure 4,
When the control signal level is between 0 and vl, the television signal is transmitted as is and outputted to the output terminal 5, and when the control signal level is between v1 and v2, the level of the television signal is lowered and outputted to the output terminal 6. , the control signal level is 72
The above case indicates that the character signal is output to the output terminal 5. If the control signal level is 72 or higher, as long as a character signal is output to the output terminal 5, the gain control of the television signal may be controlled in any manner.

第4図における制御信号の一例を生成する具体的な回路
の一例を第5図に示す。第5図において、11ν 12
は入力端子、13はオープンコレクタ出力のNAND回
路、14はオープンコレクタ出力のインバータ回路、1
6は抵抗、16はコンデンサ、1°7は抵抗、18は出
力端子である。
An example of a specific circuit for generating an example of the control signal in FIG. 4 is shown in FIG. In Figure 5, 11ν 12
is an input terminal, 13 is an open collector output NAND circuit, 14 is an open collector output inverter circuit, 1
6 is a resistor, 16 is a capacitor, 1°7 is a resistor, and 18 is an output terminal.

入力端子11には利得制御信号が与えられる。A gain control signal is applied to the input terminal 11.

入力される利得制御信号がHレベルのときは、テレビジ
ョン信号をそのまま伝送し、Lレベルのときはテレビジ
ョン信号のレベルを下げることを意味する。また、入力
端子12には切換信号が与えられる。入力される切換信
号がHレベルのときは、テレビジョン信号を出力するよ
う切換え、Lレベルのときは文字信号を出力するよう切
換えることを意味する。コンデンサ16は出力端子18
に得られるパルス波形を改善するために用いるものであ
る。
When the input gain control signal is at H level, the television signal is transmitted as is, and when it is at L level, it means that the level of the television signal is lowered. Further, a switching signal is applied to the input terminal 12. When the input switching signal is at H level, it means switching to output a television signal, and when it is at L level, it means switching to output a character signal. Capacitor 16 is connected to output terminal 18
This is used to improve the pulse waveform obtained.

第6図に示す回路例を用いて第4図に示す制御信号が得
られる。
Using the circuit example shown in FIG. 6, the control signal shown in FIG. 4 is obtained.

次に、第3図における制御信号分離回路9の具体的な回
路の一例を第6図に示す。第6図において、21は制御
信号入力端子、22は電流源、23はPNP トランジ
スタ、24は電流源、26はi’NP)ランジスタ、2
6は電流源、27.28はPNP トランジスタ、29
.30は抵抗1.31は電流源、32はPNPトランジ
スタ、33は直流電圧源、34.35は出力端子、36
は電流源、37.38はPNP)ランジスタ、39.4
0は抵抗、41は電流源、42はPNP)ランジスタ、
43は直流電圧源、44.45は出力端子、46は直流
電源である。
Next, a specific circuit example of the control signal separation circuit 9 in FIG. 3 is shown in FIG. 6. In FIG. 6, 21 is a control signal input terminal, 22 is a current source, 23 is a PNP transistor, 24 is a current source, 26 is an i'NP) transistor, 2
6 is a current source, 27.28 is a PNP transistor, 29
.. 30 is a resistor, 31 is a current source, 32 is a PNP transistor, 33 is a DC voltage source, 34.35 is an output terminal, 36
is a current source, 37.38 is a PNP) transistor, 39.4
0 is a resistor, 41 is a current source, 42 is a PNP) transistor,
43 is a DC voltage source, 44.45 is an output terminal, and 46 is a DC power source.

制御信号入力端子21から入力された制御信号は、1つ
はトランジスタ23のエミッタフォロアを通してトラン
ジスタ27.28の差動増幅器で電圧比較が行なわれ、
出力が出力端子34.36に得られる。また、もう1つ
はトランジスタ26のエミッタフォロアを通してトラン
ジスタ37゜38の差動増幅器で電圧比較が行なわれ、
出力が出力端子44F 45に得られる。いま、直流電
圧源33.43の電圧値をそれぞれ’V1.  V2と
すると、出力端子34.35には利得制御信号が得られ
、出力端子44145には切換信号が得られる。
One of the control signals inputted from the control signal input terminal 21 is subjected to voltage comparison through the emitter follower of the transistor 23 and the differential amplifier of the transistors 27 and 28.
Output is available at output terminals 34.36. The other voltage comparison is performed by the differential amplifier of transistors 37 and 38 through the emitter follower of transistor 26.
Output is available at output terminals 44F 45. Now, the voltage values of the DC voltage sources 33 and 43 are set to 'V1. V2, a gain control signal is obtained at the output terminals 34,35, and a switching signal is obtained at the output terminal 44145.

第6図に示すような回路例を用いることによって、利得
制御信号と切換信号とを重畳して1つの入力端子に入力
することができ、特にIC化の場合には有効となり、ピ
ン数が減るためにコストを下げられるという利点を持つ
By using the circuit example shown in Figure 6, the gain control signal and switching signal can be superimposed and input to one input terminal, which is particularly effective when integrated into an IC, and the number of pins can be reduced. This has the advantage of reducing costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示すブロック図、第2図は第1図の回
路に利得制御機能を付加した場合のブロック図、第3図
は本発明の一実施例のブロック図、第4図は制御信号の
一例を示す波形図、第5図は本発明における制御信号を
生成する具体回路の一例を示す回路図、第6図は本発明
における制御信号分離回路の具体例を示す回路図である
。 3・・・・・・切換回路、6・・・・・・利得制御回路
、9・・・・・・制御信号分離回路、15.17.29
730139゜4o・・・・・・抵抗、16・・・・・
・コンデンサ、23,25p27s  28+  32
p  37t  38t  42・・・・・・トランジ
スタ、33y 43y 46・・・・・・直流電圧源、
22゜24y 26y  31 g 36)  41・
・・・・・電流源、13・・・・・・NARD回路、1
4・・・・・・インバータ。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第3図 3 第4図
Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a block diagram when a gain control function is added to the circuit of Fig. 1, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is a block diagram showing a conventional example. FIG. 5 is a waveform diagram showing an example of a control signal, FIG. 5 is a circuit diagram showing an example of a specific circuit for generating a control signal in the present invention, and FIG. 6 is a circuit diagram showing a specific example of a control signal separation circuit in the present invention. . 3...Switching circuit, 6...Gain control circuit, 9...Control signal separation circuit, 15.17.29
730139゜4o...Resistance, 16...
・Capacitor, 23, 25p27s 28+ 32
p 37t 38t 42...transistor, 33y 43y 46...DC voltage source,
22゜24y 26y 31 g 36) 41・
...Current source, 13...NARD circuit, 1
4...Inverter. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 制御信号入力端子を持つ制御信号分離回路と、前記制御
信号分離回路に接続され、第1の信号入力端子を持つ利
得制御回路と、前記制御信号分離回路と前記利得制御回
路に接続され第2の信号入力端子を持つ切換回路を具備
してなることを特徴とするテレビジョン受像機の信号切
換え制御装置。
a control signal separation circuit having a control signal input terminal; a gain control circuit connected to the control signal separation circuit and having a first signal input terminal; a second gain control circuit connected to the control signal separation circuit and the gain control circuit; A signal switching control device for a television receiver, comprising a switching circuit having a signal input terminal.
JP57105906A 1982-06-18 1982-06-18 Signal switching controller of television receiver Granted JPS58222673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57105906A JPS58222673A (en) 1982-06-18 1982-06-18 Signal switching controller of television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57105906A JPS58222673A (en) 1982-06-18 1982-06-18 Signal switching controller of television receiver

Publications (2)

Publication Number Publication Date
JPS58222673A true JPS58222673A (en) 1983-12-24
JPH026470B2 JPH026470B2 (en) 1990-02-09

Family

ID=14419910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57105906A Granted JPS58222673A (en) 1982-06-18 1982-06-18 Signal switching controller of television receiver

Country Status (1)

Country Link
JP (1) JPS58222673A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62105669U (en) * 1985-12-20 1987-07-06
JPS6387876A (en) * 1986-10-01 1988-04-19 Matsushita Electric Ind Co Ltd Digital video signal synthesis circuit
JPS6387877A (en) * 1986-10-01 1988-04-19 Matsushita Electric Ind Co Ltd Digital video synthesis circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489803U (en) * 1977-12-06 1979-06-25
JPS568360U (en) * 1979-06-29 1981-01-24
JPS5637572U (en) * 1979-08-29 1981-04-09

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS568360B2 (en) * 1973-04-14 1981-02-23
US4177513A (en) * 1977-07-08 1979-12-04 International Business Machines Corporation Task handling apparatus for a computer system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489803U (en) * 1977-12-06 1979-06-25
JPS568360U (en) * 1979-06-29 1981-01-24
JPS5637572U (en) * 1979-08-29 1981-04-09

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62105669U (en) * 1985-12-20 1987-07-06
JPS6387876A (en) * 1986-10-01 1988-04-19 Matsushita Electric Ind Co Ltd Digital video signal synthesis circuit
JPS6387877A (en) * 1986-10-01 1988-04-19 Matsushita Electric Ind Co Ltd Digital video synthesis circuit

Also Published As

Publication number Publication date
JPH026470B2 (en) 1990-02-09

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