JPS5821980B2 - Facsimile transmission method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a facsimile transmission system.

In facsimile transmission, sampling (skip sampling) transmission of pixel signals, pair mode transmission of a plurality of pixels, run-length encoding transmission, etc. are performed in order to shorten the usage time of a communication line.

Sampling transmission is a process in which the original image is divided into several pixels on the horizontal and vertical axes, and pixel signals are extracted at intervals of one pixel or several pixels. There are some that skip or zigzag sampling.

Run-length encoded transmission encodes and transmits the black pixel length and white pixel length.

Furthermore, in pair mode transmission, two or three pixels are made into one pair, and a code representing the contents of the pair is transmitted.

Each of these transmission methods is effective in shortening the usage time of a communication line.

However, recently, a sampling coding transmission method that combines sampling and run-length coding has been proposed for the purpose of further shortening the usage time of communication lines (Japanese Patent Application Laid-open No. 51
Furthermore, a method has been proposed in which pair mode codes or transition codes are transmitted in run length by combining pair mode transmission and run length encoding (Japanese Patent Application Laid-open No. 85913/1982).

The present invention has been made for the purpose of providing a facsimile transmission system that has higher communication line utilization efficiency than these conventionally known facsimile transmission systems.

To achieve the above object, the present invention combines sampling transmission, pair mode transmission and run length encoding.

In sampling the image information, zigzag sampling is used to reduce the amount of missing information.

The zigzag sampling in the present invention is the zigzag sampling shown in FIG. 1b when a high-density image is targeted.

That is, as shown in Figure 1a, the image is divided along each of the horizontal axis At this time, as shown in FIG. 1b, pixel signals of pixels indicated by diagonal lines are extracted.

Also, when the image density is low relative to the pixel area, the first
Zigzag sampling with one line skip can also be used, as shown in Figure c.

Such sampling of pixel signals is carried out by, for example, assuming that the number of pixels in the
1゜3.5,7. ) of odd numbers (X=1, 3, 5,
7°...), input the even-numbered pixel signals of the even-numbered lines to the other shift register, store the pixel signals of the two lines in two sets of shift registers, and then store them at the same time. Shift the readout and press Y when the readout is finished.
This is achieved by applying an axial scanning motion.

This results in the sampling shown in FIG. 1b.

When performing the sampling shown in FIG. 1c, odd-numbered and even-numbered pixel signals may be input alternately to two sets of registers.

The mode pairs of sampling pixel signals are shown in Figures 2a to 2.
It can be created in the manner shown in Figure c.

FIG. 2a shows a mode in which pairs are formed between odd-numbered lines and even-numbered lines, and the pairs are extracted in the direction of the solid line arrow, and then the pairs are extracted in the direction of the dotted line arrow.

In addition, in FIG. 2b, the combination of pairs is the same as in FIG. 2a, but the pairs are extracted in a zigzag pattern as shown by solid arrows.

Furthermore, in FIG. 2c, pairs are taken on odd numbered lines and even numbered lines, and the pairs are extracted in the direction of the solid line arrow.

Pair extraction can be performed in several ways as described above.

However, according to the present inventor's confirmation of the transmission efficiency of a standard document through computer simulation, the transmission efficiency is highest in a mode in which extracted pixel signals located at the farthest distance are paired.

The simulation results are shown in FIG. In Figure 3, the numbers on the horizontal axis are those of the international organization CCITT (Commu TT).
nication Comm1ttee onInte
rnational Telephone & Tel
egraph), where ■ is for correspondence letters (English type), 2 is for electric circuit diagrams, 3 is for alphabetical tables, 4 is for technical English, and 5 is for technical English with a mixture of goofs and blocks. , 6 has an image of a graph, and 7 has an image of an explanatory sentence in Japanese written vertically.

The numbers on the vertical axis in FIG. 3 indicate the compression rate, and this compression rate indicates how many pixel signals (bits; signals) can be expressed by one bit during transmission.

As shown in FIG. 3, the pairing method shown in FIG. 2c has the highest efficiency.

Therefore, in the present invention, extracted pixel signals are paired with pixels located at the farthest distance.

This has the effect that pair extraction is easier to create than other methods, and demodulation from the pair mode to pixel signals on the receiving side is easy.

In the present invention, a pair mode signal is extracted as described above, and its mode or mode transition is further run-length encoded.

This run-length encoding may be a conventionally known method such as that described in Japanese Patent Laid-Open No. 49-85913.

FIG. 4 shows the configuration of a facsimile machine implementing the present invention.

In FIG. 4, reference numeral 1 denotes a scanner that scans an image in the X-axis direction and the Y-axis direction and sequentially outputs pixel signals.

The pixel signal is subjected to zigzag pair sampling in the sampling circuit 2 in the manner shown in FIG. It is converted into a frequency signal and sent out.

On the receiving side, a communication signal is received and demodulated into a run-length code by a demodulator 5, and the run-length code is converted into a pair mode code by an expander 6 to obtain an extracted pixel signal of the form shown in FIG. 2c. Then, the interpolator 7 fills the pixels between the extracted pixel signals in accordance with the white and black ratios of the peripheral pixels, and the recording device 8 records the pixels with the pixel distribution shown in FIG. 1a.

The scanner 1, modulator 4, demodulator 5, and recorder 8 are already known in the public domain, and their configurations and operations are well known. It is disclosed in detail in Japanese Patent No. 49-85913.

Therefore, the sampling circuit 2 and the inner sacred treasure 7 will be described below.
will be explained in detail.

FIG. 5 shows an example configuration of the sampling circuit 2.

This embodiment differs from the above description in that it has a configuration in which even-numbered pixel signals on odd-numbered lines and odd-numbered pixel signals on even-numbered lines are sampled.

This sampling circuit 2 is a flip-flop FF'l.

FF2, Antgame) AND1 to AND3, buffer register BR1, OR gate OR1 and inverter IN
Consists of V1.

Flip-flops FFI and FF2 produce an output at the Q terminal when a clock pulse arrives while there is an input at the input terminal, and are reset by the clock pulse when there is no input at the input terminal.

A synchronizing pulse Xin synchronized with scanning in the X-axis direction is input to the clock pulse input terminal of the flip-flop FF1 at a rate of one pulse per pixel interval in the X-axis direction (Fig. 1a), and the clock pulse of the flip-flop FF2 is inputted to the clock pulse input terminal of the flip-flop FF1. A pulse Yin synchronization pulse synchronized with scanning in the Y-axis direction is input to the input terminal.

The buffer register BR1 has m/2 shift stages when the number of pixels in the X-axis direction is m, and as shown in FIG. 2c, when extracting m/2 pixel signals in the line It has a recording capacity of 1947 minutes.

FIG. 6 shows the signal timing of each part of the sampling circuit.

In FIG. 6, FFIQS and FFIQS indicate the Q output and Q output of flip-flop FF1, and F
2 QS and FF2QS are flip-flop FF2
The Q output and Q output of are shown.

Similarly, ANDI 5-AND3S indicate the outputs of AND gates AND1 to AND3, respectively.

The input of Antogame-1-ANDl is FFIQS. FF2
Since it is a QS and Xin synchronization pulse, its output corresponds to the even number (X axis) pixel of the odd number (Y axis) line
A pulse with twice the period of the in synchronization pulse.

It is

Since this output pulse is applied to the shift clock input terminal of buffer register BRI, buffer register BR1
At this time, the image signals of even-numbered pixels are stored.

The inputs of the AND gate AND2 are FFIQS, .

Since they are FF2QS and Xin synchronization pulses, their outputs are pulses with twice the period of the Xin synchronization pulses corresponding to odd numbered pixels of even numbered lines.

Since this output pulse is applied to the shift clock input terminal of buffer register BR1, buffer register BR1
At this time, the image signals of the odd-numbered pixels are stored.

In this way, the buffer register BR1 alternately stores pixel signals of even-numbered pixels on odd-numbered lines and pixel signals of odd-numbered pixels on even-numbered lines.

The output AND2S of the AND gate AND2 is output as is as an X-axis synchronization pulse Xout for signal processing.

As shown in FIG. 6, this output point is a period T0. T2. T3. ...is...

On the other hand, the output AND3S of the AND gate 4ND3 is Yin
This pulse has a period twice that of the synchronization pulse, and is output as the Y-axis synchronization pulse Yout for signal processing.

The 2-line compressor 3 after the sampling circuit 2 (
4), the pixel signal 2 in the form of the input pixel signal as it is and the pixel signal 1 which is the output pixel signal of the buffer register BR1 are simultaneously taken in in synchronization with the Xout synchronization pulse.
Take in the Yout synchronization pulse as a line synchronization signal.

Therefore, the signals encoded by the two-line compressor 3 are a pixel signal of an even-numbered pixel on an odd-numbered line and a pixel signal of an odd-numbered pixel on an even-numbered line at the same time.
This results in run-length encoding of mode pairs or mode transitions in the manner shown in FIG. 2C.

FIG. 7 shows an example configuration of the interpolator 7.

The interpolator 7 includes a pixel signal reproduction section 7 that decomposes the mode pair demodulated by the decompressor 6 into image signals for each line, and an interpolation section 72.

The reproduction unit 71 includes four buffer registers BR2 to BR5, and the number of shift stages of each of these registers is m/2.

Buffer registers BR2 and BH3 store and read out the pixel signals of odd-numbered pixels on even-numbered lines, and two are used so that when one is being read, the other is being read.

Similarly, buffer registers BR4 and BH3 store and read out pixel signals of even-numbered pixels on odd-numbered lines.

The Yout synchronization pulse is applied to the clock pulse input terminal of flip-flop FF3, the Q output of flip-flop FF3 is applied to AND gates AND4 and AND6, and the Q output is applied to AND gates AND5 and AND7.

Therefore, when pixel signals 2 and 1 are input to buffer registers BR2 and BR4, registers BR3 and BR
5 is not given pixel signals 2 and 1, and during this time register B
A read shift pulse is applied to R3 and BH3.

The Xout synchronization pulse is converted into a Xin synchronization pulse with a double cycle FMUL1, and the odd numbered pulses of the Xin synchronization pulse are sent to registers BR2 and 3, and the even numbered pulses are sent to registers BR4 and BR4.
5 as a read shift pulse.

In this way, the image signal of the diagonally shaded pixel shown in FIG. 1b is obtained from the reproduction section 71 and inputted to the interpolation section 7□.

The interpolation unit 72 adds three surrounding pixels (
When the image signals indicated by diagonal lines) are all black, a black image signal is assigned to obtain the pixel signals having the overall pixel distribution shown in FIG. 1a. Pixel signals are output in the pixel order l, 2°3, . . .
The pixel signal of the line (Y=1) is from the OR gate 1-0R7, and the pixel signal of the second line (Y=2) is from the OR gate O.
Obtained from R6.

Flip-flops FF6 and FF7 and FF8 and FF
9 constitute a two-stage shift register, and for example, when the OR gate OR7 outputs the pixel signal /i65 in FIG. 8, the output of the flip-flop FF8 becomes /1.
The output of FF9 outputs the image signal of 63 pixels and 41 pixels.

Similarly, the flip-flop FF5 is an OR gate,
When FF 6 outputs a pixel signal of /i66, it outputs a pixel signal of waterfall 4, and FF7 outputs a pixel signal of /62.

The output time of the OR gate OR6 is shifted from that of the OR gate OR7 by the period of the Xin synchronization pulse.

In this way, in response to the output of the OR gates OR6 and OR7, the pixel signal four pulses before the Xin synchronization pulse is sent from the flip-flops FF7 and FF9 to the buffer register BR through the OR gates OR10 and OR11, respectively.
6 and BH3.

Buffer registers BR5 and BH3 have m+4 shift stages and are shifted by the Xin synchronization pulse.

Now, when the output of flip-flop FF7 is a /164 pixel signal and this is given to buffer register BR6, flip-flops FF9 and FF8
The outputs are pixel signals of /16.3 and /165, respectively, and are applied to the AND gate AND17.

Therefore, if all of those pixel signals are black, a memory output appears in the AND gate AND17, and the buffer register BR
7 is given.

In this way, when the pixel signal of /164 is given to the register BR6, the AND of the pixel signals of A3, 4, and 5 is b
is applied to the register BR7 as a pixel signal.

Similarly, when inputting a pixel signal of /16.5 to register BR7 (the output of FF7 is A5), the AND of the pixel signals of /164°5.6 is input to register BR6 as a pixel signal of i. It will be done.

In the above manner, the first line of Al is stored in the register BR7.
, a) A3.

While the pixel signals of bl, %4, . . .
The pixel signals of 4゜11... are input, and each
Input for one line is completed during one period of n synchronization pulses.

In the next cycle, the buffer register BR6 reads the first line, and in the next cycle, the register BR6 only reads the third line, and the register BR7 reads the fourth line and the second line.

This reading timing is shown in FIG.

In the above manner, as shown in FIG. 9, the pixel signals are sequentially generated from the first line with the pixel distribution shown in FIG. is output.

Furthermore, from the frequency multiplier FMUL1, the AND gate AND19,
If a delay of four group X synchronization pulses is given to the pulse path to 20.21 after the arrival of the Yin synchronization pulse, the number of shift stages of buffer registers BR6 and BR7 will be m.
Deyo G).

As described above in detail, according to the present invention, when zigzag sampling and run-length encoding are combined, or when two-line mode run-length encoding is performed,
The compression ratio increases by a factor of 0 to 20.

[Brief explanation of drawings]

Figure 1a is a plan view showing the pixel units in which the image is decomposed;
FIG. b and FIG. 1c are plan views showing sampling pixels in the present invention. FIGS. 2a to 2c are plan views showing mode pairs of sampling pixels, and FIG. 2C shows the mode pairs extracted in the present invention. FIG. 3 is a graph showing the shrinkage ratio of each mode pair shown in FIGS. 2a to 2c. FIG. 4 is a block diagram showing the transmitting and receiving configuration of a facsimile machine implementing the present invention. FIG. 5 is a block diagram showing an example of the configuration of the sampling circuit 2 shown in FIG. 4, and FIG. 6 is a time chart showing the signal output timing of each part thereof. FIG. 7 is a block diagram showing an example of the configuration of the interpolator 7 shown in FIG. 4, and FIG. 9 is a time chart showing the signal output timing of each part thereof. FIG. 8 is a plan view showing the distribution of pixel signals obtained by the interpolator 7 shown in FIG. 1...Scanner, 2...Sampling circuit, 3...2 line compressor, 4...
...Modulator, 5...Demodulator, 6...Content generator, 7...Interpolator, 8...Record i,
FF1~FF9...Flip-flop, BR1
~BR7...Buffer register, AND1~A
ND21...And gate, OR1~0R13
・・・・・・ORGATE, FMULI, FMUL2・
・・・・・・Doubler.

Claims (1)

[Claims] 1. A transmission original image is divided into horizontal and vertical directions, divided into matrices each consisting of a large number of pixels, and the pixel signals of these pixels are regularly and sequentially extracted and encoded and compressed. In the facsimile transmission method, the receiving side decodes the encoded and compressed signal to reproduce the image signal, and the recording device reproduces the image on the recording surface.In the facsimile transmission method, the transmitting side samples the matrix pixels in a zigzag pattern. At the same time, the mode code or mode transition code of each pair is encoded and compressed using an encoding compressor, with the image signals of the two sampling pixels that are closest to each other as one pair, and the encoding and compression are performed on the receiving side. The obtained signal is decoded to restore the mode code or mode transition code, and this is used to
A facsimile transmission method characterized by restoring the image signals of two sampling pixels, and allocating image information determined by the image signals of peripheral sampling pixels to the skip pixels between the sampling pixels, and restoring the transmitted image on the recording surface. .