JPS58219639A - Buffer memory device for picture processing - Google Patents

Abstract

PURPOSE:To simplify the constitution of a device and to shorten the processing time of a binary-coded picture, by composing the device of a matrix-shaped buffer memory wherein data is transferred upward and downward, and left and right, shift register buffers surrounding the memory, and a control circuit. CONSTITUTION:A buffer memory device for picture processing is provided with the matrix-shaped buffer memory 5 of M rows by N columns wherein data is transferred in any direction, i.e. upward and downward, and left and right. Further, four shift register buffers 6-9 are arranged surrounding four sides of the memory 5, and a lateral read memory 10 and a longitudinal read memory 11 are connected to the memories 6-9, and controlled by a transfer control circuit 18. The memories 8 and 9 operate as buffers in charge of the lateral writing of parallel data and the memories 6 and 7 operate as buffers in charge of the vertical writing of the parallel data. Thus, the constitution of the device is simplified and the processing time of the binary-coded picture is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory device for high-speed data processing for an image processing apparatus that performs processing such as feature extraction, measurement, and recognition of a binarized image.

Early image processing was carried out by storing image data in memory and processing it using a computer, but since image data is originally two-dimensional data, it required a lot of time to process. That was a big problem. Recently, due to the need for high-speed data processing and the reduction in the cost of memory and electronic circuits, methods have been developed to implement some processing in hardware using dedicated hardware.

FIG. 1 is a block diagram showing an example of the configuration of a typical conventional image processing device. In the example shown in the figure, a video signal from a camera 1 is converted into a binarized image signal 3 by a binarization processing circuit 2, and is added to a shift register 4 having a number of bits corresponding to the number of dots in one line.

This shift register 4 has 3 rows connected in series, and 3 dots x 3 in the image according to the rask scan of the video signal.
The matrix portions of the rows are sequentially cut out to form a matrix image as shown in FIG. 2, which is then subjected to certain processing such as smoothing, filtering, enlargement, and reduction. However, the biggest problem with this conventional device is that the order and timing of image extraction is completely dependent on the rask scan of the video signal. It is impossible to perform line tracing, vertical differential processing, etc. by changing the scanning order, or partial high-speed processing.

There is still a central processing unit (CPU) dedicated to image processing,
A high-speed buffer memory is provided as a data register accompanying this, and any area in the image memory is sequentially cut out to this high-speed buffer 7 memory according to a control signal.
Devices that perform processing using the PU have also been developed, but for simple processing such as filtering, the access time required to read the image memory and transfer the data to the buffer memory becomes a problem compared to the time required for processing. It cannot be said that the system is suitable for such things as pretreatment.

SUMMARY OF THE INVENTION In view of the above-mentioned problems with conventional image processing buffer memories, it is an object of the present invention to provide a high-speed and flexible buffer memory device suitable for image processing of binarized images. It is something to do.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The basic configuration of the buffer memory device of this device is, as shown in FIG. It consists of four sets of shift register buffers 6.7°8.9 arranged around the four sides of a matrix buffer memory and a transfer control circuit 18''.

Here, the shift register buffers 6 and 7 located at the upper and lower ends of the matrix buffer memory 6 operate as buffers in charge of writing parallel data from the upper and lower directions, respectively, and have data input terminals from the horizontal reading memory 10. parallel data 12 are connected. The shift register buffers 8 and 9 located at the left and right ends of the matrix buffer memory +75 operate as buffers in charge of parallel data writing from the left and right directions, respectively, and the vertical reading memory 11 is connected to the data input terminals of the shift register buffers 8 and 9, respectively. Parallel data 13 from is connected. The matrix panzer memory 6 receives control signals "U", "D", which instruct four data transfer directions (up, down, left, and right) via the transfer control circuit 18.
L″ and “R” (14, 16, 16, 17) are connected to control the transfer direction of parallel data transfer.

FIG. 4 is a diagram showing an example of the configuration of the matrix buffer memory 6 when n==3. In the example shown in the figure, the matrix buffer memory 5 has storage elements 1 arranged in 3 rows and 3 columns.
9 are arranged, and data is transferred in parallel according to the memory elements 19 adjacent to each other vertically and horizontally or to an external shift register, and the matrix image is shifted every time a certain process is completed for the 3×3 matrix image. Cut out images sequentially.

A specific method of configuring the matrix buffer memory 5 will be explained in detail later, but here, the operation of the third buffer memory device will be explained using boundary line tracing as shown in FIG. 6 as an example.

Consider the case where tracking is performed using a 3×3 matrix image along the boundary line of the black and white area of a binarized image as shown in FIG. 6a. The tracking direction is determined by the dot located at the center of the matrix (indicated by an x in Figure 6).
This is done using a dot pattern of 8 points around the area. Now, if there is a 3x3 matrix image at the position shown in Figure 6 and you want to track it from the top of the screen to the bottom, the next boundary line position is directly below (the arrow in the figure ). This determination can be made by analyzing the dot pattern of the matrix image using a CPU, or can be accomplished by using only a logic circuit.

Therefore, as the next step in tracking, the matrix image is shifted in the direction of the arrow to move the dot directly below to the center of the matrix (FIG. 5C). At this time, the actual operation is to shift the image data upward instead of shifting the cutting matrix downward. However, when the processing of the pattern shown in FIG. 6 is completed, a control signal "U" indicating the data transfer direction is output together with an end signal.In the buffer memory device shown in FIG.
14, the next row of parallel pattern data 12 is read out from the horizontal reading memo IJ 10 by the action of the starting speed control circuit 18, and the data is once loaded into the shift register buffer 7. , as shown in Fig. 6, pattern data of a binarized image, for example pattern data for 8 consecutive bits in the horizontal direction, is stored in sequence as 1-byte data. Data for 8 bits of direction can be updated.

However, since the position of the cutout matrix in the image is free, the horizontal positional relationship between the pattern data loaded into the shift register buffer and the matrix image is generally incorrect, as shown in Figure γ a. It is true.

Therefore, the shift register buffer 7 shifts the parallel pattern data to an appropriate position according to the center position (coordinates detected as the boundary) of the matrix image.

In the example of FIG. 7a, the shift is made to the left by 2 bits. Since this data shift can be performed using a high-speed clock, it can be made sufficiently smaller than the memory access time.

When the data position correction is completed in this way and the next row of data is prepared as shown in Figure 7, the pattern data of the matrix image is shifted upward in parallel all at once, and the The downward shift of the extraction matrix is completed according to the constraints.

In addition, as shown in FIG. 7C, the shift register buffer 7
If a type 7 capable of bidirectional shifting is used and the connection to the matrix buffer memory is made near the center, the number of shifts required for data position correction can be reduced.

A new problem arises when updating parallel data using the shift register buffer 7 described above occurs when the data to be updated spans two bytes of the horizontal reading memory 1Q.

One possible solution to this problem is to use two shift registers 7.20 connected in series as shown in FIG. 8d. At this time, the shift register 2o operates as an auxiliary register. 2 data to update
If the data spans two bytes, the data at consecutive addresses is loaded in parallel from the horizontal reading memory 1o in the order of shift register, tough, and 20, and then shifted to the left by 6 bits, as shown in Figure 8. The following data can be prepared. In this case, it is necessary to access the horizontal reading memory twice, and the access time becomes longer than in the normal case.

Furthermore, a configuration in which data is not loaded in parallel to the shift register 20 but is used as a stack may also be considered. In this case, the parallel data once loaded into the shift register 7 is shifted to the right by 8 bits and saved in the shift register 2o, and the shift register 7 has a horizontal reading memory 1o as shown in FIG. 8a. Reload the data at the previous address. With such a configuration, the number of data shifts required for position correction increases, but the shift register 20 does not necessarily require 8 bits. It is also conceivable to connect the serial output of one shift register to the serial input terminal of the other shift register to form a so-called ring-shaped configuration.

However, if the configuration of the horizontal reading memo 10 is configured so that 2 bytes of consecutive addresses can be read simultaneously as 1 word, it will be possible to read out 2 bytes of consecutive addresses as 1 word. It also becomes possible to always prepare the next data with just one memory access.

Now, when the data is updated in the above order, the extraction matrix moves to the position shown in FIG. 6C. Next, from the pattern of the matrix image in the same figure, the lower left direction of the center dot (x mark) (indicated by the arrow in the figure) is selected as the next boundary line position, and the data is transferred with the pattern processing end signal. Control signals “U++” and “R++” indicating the direction
is output.

By shifting the data of the matrix image upward and to the right in parallel in accordance with this, it is possible to relatively move the center dot of the next matrix to the lower left dot (Fig. 6 d). .

In the buffer memory device shown in FIG. 3, the transfer order at this time is the end signal 2o, the transfer control signals "U" 14, and "R".
17, the next row of parallel pattern data 12 is read from the horizontal reading memory 10, and the next column of parallel pattern data 13 is read from the vertical reading memory 11, and the shift register buffer 7.8 Load each into

The vertical reading memory 11 stores the same pattern data as the image stored in the horizontal reading memory as shown in FIG. Data for 8 dots in the vertical direction can be updated with one access, just like in the horizontal direction.

The function of the vertical shift register 8 is exactly the same as that of the shift register 7, and it shifts data individually to correct the position of the data.

Now, when the data for the next row and column are prepared in the shift registers 7 and 8, the data in the row direction is first shifted upward in parallel. After that, the data in the column direction is shifted all at once to the right in parallel.

However, the data position of the shift register 8 must be corrected in advance in consideration of the previous upward data shift. A series of these transfers and transfers is controlled under the control of the transfer control circuit 18.

With the above-described procedure, the shift of the extraction matrix toward the lower left is completed, resulting in the state shown in FIG. 6d. Thereafter, by repeating the same operation, the boundary line can be traced while shifting the position of the extraction matrix in any direction.

Next, a specific method of configuring the matrix buffer memory 6 will be explained. The basic structure of the IJ box-shaped buffer memory 6 is as shown in FIG. 4, and memory elements 19 having four sets of input/output terminals may be connected in a matrix.

FIG. 9a shows one embodiment of constructing such a memory element. Each of the four AND gates 21 to 24 receives a control signal "U" specifying a transfer direction.

"'D'", "Rn" and the output signal of the adjacent memory element 19 in the transfer direction are connected as bare. For example, the AND gate 21 receives the upward transfer control signal "U". "14 and the output signal 30 of another memory element adjacent to the lower side are connected.

The output signal of each AND gate 21 to 24 is output to an OR gate 26.
connected to the input terminal of Here, transfer control signal “U”
, "D"tlt", and "R" are on ('1"), it becomes bare and A
The output signal of the other storage element 19 connected to the ND gate is obtained as the output signal of the OR gate 26. The output signal of the OR gate is connected to the flip-flop 26, and when the clock 28 for parallel transfer is applied, the storage element 19 is bare with the transfer control signal that is in the on state.
The data is transferred from the D-7 lip 70 to the D-7 lip 26.

The output signal 29 of the D-7 lip-flop 26 is respectively connected to one of the AND gates 21 to 24 of the other storage elements 19 that are vertically, horizontally and horizontally adjacent to each other. For example, the storage element 19 is located in the bottom row of the matrix buffer memory 6 (
(Mth row), one of the parallel outputs of the shift register buffer 7 is used as the input signal 30 from below.
Just connect one.

Here, as shown in the example in Figure 6C,
IJ shift, that is, control signals “U” and “R”
are simultaneously output as the next transfer control signal, will the two AND gates be on at the same time? This will result in incorrect data transfer. Therefore, the transfer control signal tt Usr.

-D”, “L” 91 R71 is temporarily connected to the transfer control circuit 18
The transfer control circuit controls the data to be applied to the AND gate of each storage element in accordance with the timing of actual parallel data transfer.

FIG. 9 shows a second embodiment of the memory elements constituting the matrix buffer memory 6. In FIG. In the example shown in the figure, instead of four AND gates and one OR gate, a multiplexer 31 is used that selects and outputs one of the four gates. The signal input terminals of the multiplexer 31 are connected to the output signals of the memory elements adjacent vertically and horizontally, respectively.

Still, at least a part of the transfer control signals IIU", "D", L", and °R" is input as a control signal to the multiplexer 31, and four-man power selection is performed.

The output signal of the multiplexer 31 is assumed to be the input signal of the D-flip-flop 26 as in the case of FIG. 9a. The subsequent operations are the same as in the case of FIG. 9a.

Next, as a third embodiment, an example in which the matrix buffer memory 6 is constructed using shift registers is shown in FIG. In other words, 32 is 4 which can shift data in both directions.
This is a bit-structured shift register, and in the example shown in the figure, two of these are connected in series to form a buffer memory in the row direction. Therefore, the maximum horizontal size of the matrix is
Sizes up to 8" are possible. The vertical size of the matrix is determined by the number of rows in the shift register 32.

Parallel output signal groups 34 and 35 of an external vertical shift register buffer 8.9 are connected to the left and right ends of the shift register 32 in each row, respectively. In order to shift the extraction matrix from the left to the right, the contents of all shift registers 32 may be shifted one bit at a time in the corresponding direction. Data to be updated is transferred from an external shift register buffer.

Next, the procedure for parallel transfer in the vertical direction will be explained.

For this purpose, the parallel inputs of the shift register 32 are utilized. Data multiplexers 33 for each row are provided corresponding to the shift registers 32 for each row. The output signal of the multiplexer 33 in the i-th row is connected to the parallel input terminal of the shift register 32 in the i-th row. On the other hand, the parallel output signal groups of the shift registers 32 in the i-1th row and the i+1th row are connected to the input terminal of the multiplexer 330, respectively. Multiplexer 33
is given at least one of the upward and downward transfer control signals ``U''ttD'' as a control signal, whereby one set of the two input signal groups is selected and transferred to the i-th row shift register. becomes the parallel input signal. That is,
When data is transferred from top to bottom, the data in the i-1st row is transferred to the i-th row, and when data is transferred from bottom to top, the data in the i+1st row is transferred to the shift register 32 in the i-th row. Parallel lonided.

For example, if one of the input signal groups of the multiplexer 330 corresponding to the shift register 32 in the first row is connected to the parallel output signal group 36 of the external shift register 6, the data from above can be Can be updated. For the Mth row, the parallel output signal group of the shift register buffer 7 may be connected.

Other operations are basically 1. This is the same as in the second embodiment.

In the above description, only a configuration example in which a shift register is used as a memory in the row direction has been mentioned, but it is a matter of course that the shift register can be used as a memory in the column direction to configure a matrix-like buffer memory similar to that of a cell.

Now, as explained above, the Lehaffa memory device according to the present invention provides high-speed memory access and freedom in image extraction position by providing a shift register buffer between the image memory and the matrix buffer memory. It also realizes important functions in image processing, such as the degree of freedom in the order of image extraction (the moving direction of the cropping matrix).

Furthermore, as is clear from the above explanation, by using the buffer memory device according to the present invention, adaptive image processing including judgment functions such as boundary line tracking, which was difficult to implement with conventional hardware, can be easily performed. You can realize the name.

In addition, in order to operate this buffer memory device efficiently, it is necessary to prepare two image memories, a horizontal reading memory and a vertical reading memory, to store the same image data, and the memory is twice as large as the image memory. Capacity is required. However, with this buffer memory device, the number of accesses to the image memory is always one or two times.
Low-cost memory with relatively long access times can be used, and the cost burden is small. On the other hand, conventional methods use so-called bit-plane memory (stores one dot's worth of data per address), which is often used as memory for binarized images. In order to update the IJ storage data, at least six memory accesses are required, resulting in a long access time. In order to shorten the access time, it is necessary to use expensive high-speed access memory, which may actually cause cost problems.

Another major feature of the buffer memory device according to the present invention is that there is almost no increase in access time even when the size of the extraction matrix increases. In a buffer memory using a conventional bit-plane image memory, the number of memory accesses, that is, the access time increases in proportion to the size of the matrix. on the other hand,
In the buffer memory device according to the present invention, even if the size of the matrix becomes large, only one of the horizontal reading and vertical reading memories can be used.
If the number of bits per word is increased according to the matrix size, there is almost no increase in access time. Rather, the larger the size of the matrix, the more effective it is.

It goes without saying that this buffer memory device can also be used when filtering, convolution, etc. are performed uniformly over the entire image memory.

As described above, the image processing buffer memory device of the present invention is useful because it has a simple circuit configuration and can realize many very important functions in performing binarized image processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a typical conventional image extraction buffer memory device, FIG. 2 is a schematic diagram showing a extracted matrix image, and FIG. 3 is an image in an embodiment of the present invention. A block diagram of the processing buffer memory device, FIG. 4 is a block diagram showing the basic configuration of the matrix buffer memory, and FIG. 6 is a schematic diagram explaining the procedure for boundary line tracing using the buffer memory device. , FIG. 6 is a schematic diagram illustrating the data structure of the horizontal reading and vertical reading memories that store the image data, and FIGS. 7 and 8 are schematic diagrams illustrating position correction of updated data using the shift register buffer. 9 is a circuit diagram showing each storage element constituting the matrix buffer memory,
FIG. 10 is a block diagram of a matrix buffer memory constructed using the shift register. 6...Matrix buffer memory, 6,7.
8.9.20...Shift register buffer, 10°11...Image memory, 14,1
6,16.17... Transfer control signal, 18...
...Transfer control circuit, 19...Storage element, 21
, 22, 23. 24...AND gate, 26.
...OR gate, 26...D-flip frog, 31...Multiplexer, 32...
...Bidirectional shift register, 33...Multiplexer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure 5 ar (41 (Cn td) Figure 6 Figure 7, BelC) Figure 9 Figure 8

Claims (4)

[Claims] (1) 1-bit memory elements having four sets of data input/output terminals are arranged in a matrix of M rows and N columns (%, N≧1), and the four sets are arranged between the memory elements adjacent to each other in the vertical and horizontal directions. A matrix-like buffer memory is provided which is connected to enable data transfer to each other through data input/output terminals, and a matrix-like buffer memory having a number of bits of at least N bits is provided outside the first row and the M-th row of the buffer memory in the row direction. A first shift register buffer of a parallel input/parallel output type is provided for shifting data along the column direction, and the external appearance of the first side column and the Nth column of the buffer memory has a bit number of at least M bits in the column direction. A second shift register buffer with parallel input and parallel output is provided for shifting data along the matrix, and the parallel outputs of each of the shift register buffers are connected to respective storage elements located outside of the matrix buffer, and each of the The parallel inputs of the shift register buffer are connected to the data bus of the memory storing the binarized image, and a transfer control signal instructing data transfer in the vertical and horizontal directions is transmitted to the buffer memory and the shift register in accordance with the transfer control signal. 1. A backup memory device for image processing, comprising a transfer control circuit that controls the contents of a buffer to be transferred simultaneously in parallel in a row direction or a column direction. (2) As a matrix buffer memory, a memory element formed by connecting the outputs of four AND circuits to the input terminals of an OR circuit, and connecting the outputs of the OR circuits to the data input terminals of a flip-flop circuit in M rows and N columns. The input terminals of the four AND circuits each receive one of the four transfer control signals that instruct data transfer in the up, down, left, and right directions, and adjacent signals corresponding to each transfer direction are arranged in a matrix structure. The image processing buffer memory device according to claim 1, characterized in that the output terminal of a flip-flop circuit of another memory element or the corresponding output terminal of an outer shift register buffer is connected. too. (3) As a matrix buffer memory, a matrix structure is formed by arranging memory elements in M rows and N columns in which the output of a multiplexer circuit that selects one out of four inputs is connected to the data input terminal of a flip-flop circuit; The four data input terminals of the multiplexer circuit are connected to the output terminals of flip-flop circuits of other storage elements adjacent to each other vertically and horizontally, or the corresponding output terminals of the outer shift register (sofa), and input selection of the multiplexer circuit is performed. 2. The image processing buffer memory device according to claim 1, wherein at least a portion of four transfer control signals instructing data transfer in the vertical, horizontal, and horizontal directions are connected as signals. (4) As a matrix buffer memory, serial and parallel input/parallel output type shift registers that can shift data in both directions are connected in series so as to have at least N bits, and the memory in the row direction is The memory is arranged in M rows to form a matrix structure, and other adjacent memories above and below the memory in the row direction are connected to each other through a multiplexer circuit that selects data in accordance with a transfer control signal in the vertical direction to the parallel input terminal of the memory in each row direction. 2. The memory device for image processing according to claim 1, characterized in that the corresponding parallel outputs of the memory t in the row direction or the outer shift register are connected.