JPS58218229A - Selecting circuit of delay time - Google Patents
Selecting circuit of delay timeInfo
- Publication number
- JPS58218229A JPS58218229A JP57100430A JP10043082A JPS58218229A JP S58218229 A JPS58218229 A JP S58218229A JP 57100430 A JP57100430 A JP 57100430A JP 10043082 A JP10043082 A JP 10043082A JP S58218229 A JPS58218229 A JP S58218229A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- package
- delay
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
Abstract
Description
【発明の詳細な説明】
(1)技術の背景
本発明は、情報処理装置におけるクロック調整や、その
他広く信号を遅延させる必要のある一般の回路に用いる
遅延時間付与回路に係シ、特に複数の遅延時間のうちか
ら任意の遅延時間を選択することのできる遅延時間選定
回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Background of the Technology The present invention relates to a delay time providing circuit used for clock adjustment in information processing devices and other general circuits that require a wide range of signal delays, and particularly relates to The present invention relates to a delay time selection circuit that can select an arbitrary delay time from among delay times.
(2)従来技術の問題点
従来の遅延時間付与回路は、インダクタンス−キャパシ
タなどから構成されるディレーラインや、第1図に示す
ようなディレーライン1と、波形整形用のバッファゲー
ト2を同一パッケージ已に内蔵したディレー回路などが
知られている。(2) Problems with the conventional technology In the conventional delay time imparting circuit, a delay line composed of an inductance-capacitor, etc., or a delay line 1 as shown in Fig. 1, and a buffer gate 2 for waveform shaping are packaged in the same package. A built-in delay circuit is well known.
このようなディレー回路は、一つの入力端子4に対し、
それぞれ遅延時間を異にした複数の出力5が得られるよ
う構成され、使用に際しては適当な遅延時間をもつ出力
端子を選び、これを短絡回路や、切替スイッチを用める
などの方法で各デバイスに接続することが行われていた
。しかしながら、このような方法ではディレー回路のパ
ッケージの他に、短絡回路のパッケージや切替スイッチ
の占有するスペースが必要で、今日の大規模な集積化の
傾向に反する。また、ディレー回路の入出力端子数も、
例えば8種の遅延時間を選択できるようにするためには
、咳8個の出力端子と入力端子、アース端子、電源端子
の計11個の端子が必要でパッケージそのものの小型化
にも限度があり、選択しうる遅延時間の種類を増やそう
とすれば、出力端子を増加せざるを得す、必然的に大型
化してしまう欠点があった。また、遅延時間の選定も、
短絡回路のハンダ付等に手間がかがシ、機器の調整には
不便であった。本発明はこのような欠点を解消し、パッ
ケージの出力端子数を減少して小型化を可能にしたうえ
、異なる遅延時間を任意に選定でき、しかも選定後も自
由にその変更をすることもできる遅延時間選定回路を提
供するものである。For one input terminal 4, such a delay circuit
It is configured to provide multiple outputs 5 with different delay times, and when used, select an output terminal with an appropriate delay time and connect it to each device by short circuiting or using a changeover switch. It was done to connect to. However, in addition to the delay circuit package, this method requires space occupied by the short circuit package and the transfer switch, which runs counter to today's trend toward large-scale integration. Also, the number of input and output terminals of the delay circuit is
For example, in order to be able to select 8 types of delay times, a total of 11 terminals, including 8 output terminals, an input terminal, a ground terminal, and a power supply terminal, are required, and there is a limit to the miniaturization of the package itself. However, if one were to increase the number of selectable delay times, the number of output terminals would have to be increased, which would inevitably result in an increase in size. Also, the selection of delay time is
It was time-consuming to solder short circuits, etc., and it was inconvenient to adjust the equipment. The present invention eliminates these drawbacks, reduces the number of output terminals of the package, enables miniaturization, and allows for different delay times to be arbitrarily selected, and can be changed freely even after selection. A delay time selection circuit is provided.
(3)発明の構成
本発明の構成は、特許請求の範囲に記載のとおシであシ
、遅延回路に1選択回路を同−P“
パッケージ内に装着して成り、遅延回路から出力される
複数の出力のうちの一つを、上記選択回路が外部から入
力j′・れる選択信号に従って選択し出力端子に出力す
るようになっている。(3) Structure of the Invention The structure of the present invention is as described in the claims, and comprises a delay circuit and a one-selection circuit mounted in the same package, and output from the delay circuit. The selection circuit selects one of the plurality of outputs according to a selection signal input from the outside and outputs it to the output terminal.
(4) 発明の実施例 第2図に本発明の二つの実施例を示す。(4) Examples of the invention FIG. 2 shows two embodiments of the invention.
同図において、8はディレー回路、9はその出力信号線
であり、この例では8種の遅延時間を選択できるように
なっている。1oはマルチプレクサであシ、9の出力信
号線のうちの一つを選択して出力端子14に出力する。In the figure, 8 is a delay circuit, 9 is its output signal line, and in this example eight types of delay times can be selected. A multiplexer 1o selects one of the nine output signal lines and outputs it to the output terminal 14.
該選択は、セレクト信号入力端子13からの信号によっ
て制御され、該セレクト信号はロジックレベルの信号で
あって選択は極めて容易である。該端子13は本例の8
本の信号出力の切替のためには3個あればよく、パッケ
ージ11全体の端子数はその個入力端子12が1個、出
力端子14が1個、アース端子16と電源端子15が各
1個の合計7個となυ、戸・
第1図の従来の例、に比して大巾に端子数が減少するの
で、パッケージ全体を小型化でき、′1・
しかも出力端子を早択するための短絡回路等は不要であ
るから、実質的な実装スペースは一層少くて済む。The selection is controlled by a signal from the select signal input terminal 13, and since the select signal is a logic level signal, the selection is extremely easy. The terminal 13 is 8 in this example.
In order to switch the signal output of a book, only three terminals are required, and the total number of terminals in the package 11 is one input terminal 12, one output terminal 14, one each of ground terminal 16 and power terminal 15. Since the number of terminals is greatly reduced compared to the conventional example shown in Figure 1, the entire package can be made smaller, and the output terminal can be selected quickly. Since short circuits and the like are not required, the actual mounting space can be further reduced.
(5)発明の詳細
な説明したとおシ、本発明の遅延時間選定回路は極めて
小型であるうえ、遅延時間選択のため他の短絡回路等を
必要としないので、実装スペースは一層小さくなシ、゛
遅延時間の設定、変更が任意にできるうえ、その変更は
極めて容易であるので、機器の調整等も手間が省け、ま
た回路への装着も短絡回路のハンダ付は等が不要となる
ため簡便になるなど多くの利点がある。(5) As described in detail of the invention, the delay time selection circuit of the present invention is extremely compact and does not require any other short circuit for delay time selection, so the mounting space is even smaller.゛The delay time can be set and changed as desired, and it is extremely easy to change, so it saves time and effort in adjusting equipment, and it is easy to attach to the circuit because there is no need to solder short circuits. There are many advantages such as:
第1図は従来のディレー回路の例を示す図、第2図は本
発明の一実施例を示す図である。
1・・・・・・ディレーライン、2・・・・・・バッフ
ァケート、S・・・・・・パッケージ、4・曲・入力端
子、5・・・・・・出力端子、6・・・・・・電源端子
、7・・・・・・アース端子、8・・・・・・ディレー
回路、9・・曲ディレー回路の出力信号線、10・・遥
・・・マルチプレクサ、11・・・・・・パッケージ、
12・・四入力端子、13・・・・・・セレクト信号入
力端子、14・曲・出力端子、15・・・・・・電源端
子、16・・・・・・アース端子、17・・・・・・バ
ッファゲート。FIG. 1 is a diagram showing an example of a conventional delay circuit, and FIG. 2 is a diagram showing an embodiment of the present invention. 1...Delay line, 2...Buffer Kate, S...Package, 4.Song/input terminal, 5...Output terminal, 6... ...Power supply terminal, 7...Ground terminal, 8...Delay circuit, 9...Output signal line of music delay circuit, 10...Haruka...Multiplexer, 11... ···package,
12... Four input terminals, 13... Select signal input terminal, 14... Song/output terminal, 15... Power supply terminal, 16... Earth terminal, 17... ...Buffer Gate.
Claims (1)
遅延時間を与えて出力する遅延回路と、選択信号によっ
て前記複数の遅延回路の出力の一つを選択して出力端子
に出力する選択回路を同一パッケージ内に装着して成る
遅延時間選定回路A delay circuit that applies a plurality of different delay times to an input signal input from an input terminal and outputs the same, and a selection circuit that selects one of the outputs of the plurality of delay circuits according to a selection signal and outputs it to the output terminal. Delay time selection circuit installed in the same package
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57100430A JPS58218229A (en) | 1982-06-11 | 1982-06-11 | Selecting circuit of delay time |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57100430A JPS58218229A (en) | 1982-06-11 | 1982-06-11 | Selecting circuit of delay time |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58218229A true JPS58218229A (en) | 1983-12-19 |
Family
ID=14273734
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57100430A Pending JPS58218229A (en) | 1982-06-11 | 1982-06-11 | Selecting circuit of delay time |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58218229A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1987001479A1 (en) * | 1985-09-04 | 1987-03-12 | Fujitsu Limited | System for adjusting clock phase |
JPH01106518A (en) * | 1987-10-20 | 1989-04-24 | Olympus Optical Co Ltd | Timing signal generating circuit |
-
1982
- 1982-06-11 JP JP57100430A patent/JPS58218229A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1987001479A1 (en) * | 1985-09-04 | 1987-03-12 | Fujitsu Limited | System for adjusting clock phase |
JPH01106518A (en) * | 1987-10-20 | 1989-04-24 | Olympus Optical Co Ltd | Timing signal generating circuit |
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