JPS58213371A - Data processing system - Google Patents

Abstract

PURPOSE:To decrease the transfer time without using a bus, to prevent the processing speed from being lowered and to reduce the hardware, by operating a desired processing within the extension of addresses of a main memory of a CPU. CONSTITUTION:Specific addresses of the main memory 42 are assigned to an operation command register 1, an operation status register 2, argument registers 3a, 3b for operation command, and an operation resulting register 4a. In writing a data to the register 1, it is detected at a command circuit 21 and the operation command is given to a data processor 41 depending on the content of the operation command register 1 and the argument registers 3a, 3b. On the other hand, the operating state and the operating result from the data processor 41 are written to the operating state register 2 and the operating resulting register 4a with a storage control circuit 22.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to data processing systems.

[Technical background of the invention and problems with the background art] Separately from the central processing unit (CPU) of a certain data processing device,
When connecting another data processing device that performs local processing to perform various processing, this data processing device usually uses a bus for the input/output device of the CPU or a direct memory access (DMA) bus. connected to.

However, when connected to an input/output bus, there is a problem in that it takes time to start up the data processing device, grasp its status, and transfer processing results, resulting in a decrease in processing speed. Also, D
When connected to the MA bus, there is a problem in that the amount of hardware for the entire system increases.

[Purpose of the invention]

The present invention has been made based on the above circumstances, and by adding some hardware and operating the desired processing on an extension of the address of the main memory of the CPU, processing using the bus is not required. The purpose is to provide a data processing system with

[Summary of the invention]

The data processing system of the present invention allocates specific addresses in the main memory to an operation command register, an operation status register, an argument register for operation commands, and an operation result register, and when writing is performed to the operation command register. The instruction circuit detects and gives an operation instruction to the data processing device according to the contents of the operation command register and argument register, while the operation state and operation result from the data processing device are stored in the operation state register and operation result register by the storage control circuit. This is so that it can be written to.

[Embodiments of the invention]

The drawing shows an embodiment of a data processing system according to the present invention. In the figure, reference numeral 41 denotes a data processing device, such as a controller for equipment intended to be controlled from an electronic computer, a signal processing device, an image processing device, etc.
An image memory etc. can be considered, but the case of image memory will be explained below. Image memory generally uses two-dimensional addressing. That is, access is performed using a combination of an address in the X direction and an address in the Y direction.

The mind is the main memory of a computer, and its specific address, e.g. 0
Addresses ~4 are operation command register 1, status register 2,
It is allocated to argument registers 3a, 3b and result register 4a. The value of operation command register 1 is r 0001
When it is J, it means that the operation command "image memory read" is given.

r 0001 J in the status register 2 is defined as "processing in progress" and r 0000 J as "processing completed". The argument registers 3a, 3b respectively store an X address and an X address.

43 is a central processing unit (CPU) of the computer, which is connected to the main memory core.

Reference numeral 21 denotes an instruction circuit which receives the operation command written in the operation command register 1 and arguments in the argument registers 3a and 3b via signal lines 11.13a and 13b, respectively, and also receives the address to the main memory core. and a write signal via the address signal line 15, detects that a write has been made to a specific address in the main memory 42, and based on these, sends an operation instruction to the data processing device 41 via the signal line 31. give.

Reference numeral 22 denotes a storage control circuit which receives signals indicating operating states and operation (processing) results from the data processing device 41 via signal lines 32 and 34a, and applies them to the registers 2 and 4a via signal lines 12 and 14a, respectively.

Data processing device (image memo IJ) from CPU 43
An example of accessing X=010 and Y=001 of 41 will be explained.

ii', from the CPU 43 to main memo I+ 42 address 2 (
Write r 010 to register 3a), write J, and "001" to address 3 (register 4a). Next, write r 0001 J to address 0 (register 1). Then, the instruction circuit 21 detects that the data at address 0 has been written via the signal line 15, and indicates via the signal line 11 that the data at address 0 is 0001, that is, the command for "image memory read" is issued. I know that the sake is stale. And signal @ 13a,
13b, the contents of addresses 2 and 3, that is, X = 0
10 and Y=OO1, and instructs to read data at this address via the signal line 31. Data processing device 41
outputs a signal to the signal line 32 indicating that the read operation is in progress. Also, the specified address (X=010,
When the data Y=001> is read out, the signal is outputted to the signal line 34a, and a signal indicating the completion of reading is outputted to the signal line n. The storage control circuit 22 receives a signal on the signal line 32 and generates a code 0 indicating that reading is in progress.
Write 001 to address 1 (register 2) of main memory. When read data is received via the signal line 34a, the data is transferred to the main memory IJ 42-4 via the signal line 14a.
Write to address (register 4a). Along with this, a signal?
Upon receiving the read completion signal via a32, the main memory IJ
Write roooOJ to address 1 of 42. The CPU 43 reads r 0000 J at address 1 of the main memo IJ 42, learns that the data processing device 41 has completed reading, and reads the contents at address 4, thereby reading the data from the data processing device 41. obtain.

In the above example, there are n argument address registers and one result register, but these numbers vary depending on the purpose.

〔Effect of the invention〕

As described above, according to the present invention, the time required for transfer is short without using an input/output bus, and the processing speed does not decrease.

Furthermore, since the DMA bus is not used, the amount of hardware can be reduced. Further, when the data processing device is an image memory, the degree of freedom is increased in that the image memory, which has a relatively large address space, can be accessed as an extension of the main memory, which has a relatively small address space.

[Brief explanation of drawings]

The drawing is a block diagram showing a data processing system according to an embodiment of the present invention. 1...Operation command register, 2...Status register, 3
a, 3b...Argument register, 4a...Result register, 21...Instruction circuit, 22...Storage control circuit, 41
...Data processing device, 42...Main memory, 43...
・Central processing unit.

Claims (1)

[Claims] It detects that the operation command register, operation status register, argument register for operation command, and operation result register are assigned a specific address in the main memory, and the operation command register is written to, and then commands the operation command register. An instruction circuit that reads the contents of registers and argument registers and generates operation instructions; and a data processing device that operates in accordance with the operation instructions issued from the instruction circuit and outputs signals indicating the operation status and operation results. , a storage control circuit that receives a signal indicating an operating state and an operating result obtained from the data processing device and stores the operating state and operating result in the operating state register and the operating result register.