JPS58211207A - Sequency control device - Google Patents

Sequency control device

Info

Publication number
JPS58211207A
JPS58211207A JP9351382A JP9351382A JPS58211207A JP S58211207 A JPS58211207 A JP S58211207A JP 9351382 A JP9351382 A JP 9351382A JP 9351382 A JP9351382 A JP 9351382A JP S58211207 A JPS58211207 A JP S58211207A
Authority
JP
Japan
Prior art keywords
output
input
memory device
circuit
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9351382A
Other languages
Japanese (ja)
Inventor
Kenichi Yoda
与田 健一
Michihiro Inamori
稲森 満弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP9351382A priority Critical patent/JPS58211207A/en
Publication of JPS58211207A publication Critical patent/JPS58211207A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/045Programme control other than numerical control, i.e. in sequence controllers or logic controllers using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers

Abstract

PURPOSE:To improve remarkably a use function, by feeding back a data terminal output of a memory device to an address terminal input through a three state buffer, and controlling this buffer by a data terminal output of other memory device. CONSTITUTION:When feeding back data terminal D1, D2-Dn outputs of a memory device 3 to an address terminal, each data terminal output is inputted to the address terminal through three state buffers 41, 42-4n, respectively, by which a feedback circuit 5 is constituted. Also, a memory device 6 for storing a data regarding whether an output of an inputting circuit 1 is self-held or not, at every said output is provided, and by data terminal D1-Dn outputs this device 6, on- and-off operations of the buffers 41-4n are controlled.

Description

【発明の詳細な説明】 本発明はマイクロプロセッサを有することなくメモリ装
置を中心とした簡印な構成で実現されるシーケシス制伽
装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence creation device that is realized with a simple configuration centered on a memory device without having a microprocessor.

とより構成され、検数の入力?有する入力回路(+)の
複数の出力をメtり装置(3)のアドレス端子A1・・
An  に入力するとともに検数の外部機器(図示せず
)を制御する出力回路(2)の検数の入力端子にメモリ
装置(3)の複数のデータ端子D1・・Dm  出力を
接絖し、メ℃すi lfl +3+に各アトしス喘子A
1・・・An  入力に対するデータ端子D1・・・D
rn  出力の状態として入力回路の各入力に対応する
出力回路の出力状態のデータを記憶設定し、このメモリ
装置(3)の記憶データに基き入力回路の各入力に対応
して出力画1111+2+による各外部機器の制御状態
を変更するようにしてあり、これによυシーケシス制御
動作が得られるよう傾していた。
And more composed of input of tally? The address terminal A1 of the metering device (3) is connected to the multiple outputs of the input circuit (+) having the input circuit (+).
Connecting the outputs of a plurality of data terminals D1...Dm of the memory device (3) to the input terminal of the output circuit (2) for inputting data to An and controlling an external device for counting (not shown), Me C Su I lfl +3+ Each Atsushiko A
1...An Data terminal D1...D for input
rn The data of the output state of the output circuit corresponding to each input of the input circuit is stored and set as the output state, and each output image 1111+2+ is set corresponding to each input of the input circuit based on the data stored in the memory device (3). It was designed to change the control state of external equipment, and this was intended to provide υ sequence control operation.

ところがかかる従来例においては、自己保持動作が必要
なときメモリ装置(3)のデータ端子り、・・・Dm出
力の一部をその対応するアドレス端子にフィードバック
入力してこれを実現しているため、メモリ装置(3)の
全ての入出力についてフィードバックを施すとメモリ装
置のアトしス入力が使用不可となる。このためかかる従
来例ではフィードバック回路を形成して自己保持機能を
具備するように構成する端子へ〜ハ〜の数を制限する他
なく、自在な回路機#!牙得ることが困難である問題が
あった本発明は上述の点に鑑みて提供したものであって
、メtり装置の任意の入出力端子間で自己保持機能を皐
備させることができ、しかも入力回路の各出力に対して
メモリ装置の各データ出力の出力状態を自己保持すべき
か否かのデータを第2のメモリ装置に予めづロタラムし
て2くことが、できるようKしたシーケシス制御装置を
柳供すること金目的とするものである。
However, in such a conventional example, when self-holding operation is required, this is achieved by feeding back a part of the Dm output from the data terminal of the memory device (3) to its corresponding address terminal. , when feedback is applied to all inputs and outputs of the memory device (3), the atmos input of the memory device becomes unusable. For this reason, in such conventional examples, there is no choice but to limit the number of terminals configured to form a feedback circuit and provide a self-holding function, and the circuit device #! The present invention has been provided in view of the above-mentioned problems, and it is possible to provide a self-holding function between arbitrary input and output terminals of the metering device. Moreover, the sequence control is such that data indicating whether or not the output state of each data output of the memory device should be self-maintained for each output of the input circuit can be rotoramed in advance to the second memory device. The purpose is to provide the equipment for financial gain.

以下本発明の一実施例を図面により詳述する。An embodiment of the present invention will be described in detail below with reference to the drawings.

第2図は本発明の一実施例回路を示すものであって、前
述の第1図従来例のものにおいて、メtり装置(3)の
データ端子のDl・・Dn  出力をアドレス端子に帰
還するに際し、各データ端子出力毎忙夫々スリーステー
トバッファ(41)・・(4n)(r介しアドレス端子
に入力するようにしてフィードバック回路(5)?構成
し、さらに入力回路(1)の各出力毎にそれ?自−己保
持するか否かのデータを記憶する第2のメモリ装(2)
′(6)を設け、このメtり装置(6)のデータ端子D
1・・dカにより上記スリーステートバッファ(4□)
−〇オシ、オフ動作を制御するようにしである。ここで
第1のメモリ装置(3)には第1図従来例のものと同様
なアドレス端子A1−入力に対するデータ端子D1〜出
力の関係としてのシーケシスプログラムデータが書き込
まれているものであり、第2のメtり装置(6)には、
入力回路(1)のどの出力が生じたときにどのデータ端
子D1〜出力を自己保持するかのデータが書き込まれて
いる。
FIG. 2 shows a circuit according to an embodiment of the present invention, and in the conventional circuit shown in FIG. In doing so, a feedback circuit (5) is configured so that each data terminal output is input to the address terminal via three-state buffers (41)...(4n) (r), and each output of the input circuit (1) is A second memory device (2) that stores data on whether it is self-retaining or not.
'(6) is provided, and the data terminal D of this metering device (6) is provided.
1. The above three-state buffer (4□) is created by d.
−〇Oshi, it is designed to control the off operation. Here, sequence program data is written in the first memory device (3) as the relationship between the data terminal D1 and the output with respect to the address terminal A1 and the input, similar to that of the conventional example shown in FIG. The second metering device (6) includes:
Data is written indicating which data terminal D1 to which output is self-held when the output of the input circuit (1) is generated.

かくて上記実施例にあっては、通常は全てのスリーステ
ートバッファ(4□)〜が遮断状態となり、入力回路i
t)とメモリ’1ii−置t31と出力回路(2)とよ
りなる第1図従来例と同様の回路でシーケシス制商1動
作が行なわれる。次に令弟2のメtり装置(6)におり
て自己保持すべきことが書き込まれている入力回路(]
)出力に出力が生じたとすると、その出力信号がメtり
装置(3)のアドレス端子A、に入力するこ(6〕のア
ドレス端子A、に入力することによりデータ端子り、V
C出力を生じ、これによりスリーステートバッファ(4
ρがオシになり、メモリ装置(3)のデータ出力がアド
レス入力側にフィードバックされ、自己保持可能、が得
られることになる。
Thus, in the above embodiment, normally all three-state buffers (4□) ~ are in the cut-off state, and the input circuit i
The sequence calculation quotient 1 operation is carried out in a circuit similar to that of the conventional example shown in FIG. Next, the input circuit (] where the information to be self-maintained is written in the measuring device (6) of younger brother 2
) If an output occurs at the output, the output signal is input to the address terminal A of the metering device (3), and by inputting it to the address terminal A of (6), the data terminal is changed to V.
C output, which causes a three-state buffer (4
ρ becomes positive, the data output of the memory device (3) is fed back to the address input side, and self-holding is achieved.

第3図は本発明の他の実施例回路を示すものであって、
上記第2図実施例のものに2いてさらK、CR内部リレ
ーの一部をも自己保持可能、としたものである。ここT
CR内那リレーは、゛タイマ機能を得る目的でメモリ装
b(3)内に形成されている飽飽要素であり、このCR
内部リレーに対応するメE ’J装置轡1:l)のアド
レス端”子ン、1〜に入力を与えることにより、CR内
部リレーの機能動作の制aを行うこさができるようにし
である。χパ<てこの第3図実施例のものにあっては、
第2図実施例のものと同様に、メモリ装置(3)のデー
タ端子D1〜の各出力をスリースチートノ5ツフア(4
1)〜と介して入力側のアドレス端子ん〜にフィードバ
ックするとともに、メモリ装置(3)OCR内部リレー
に対応するアドレス端子Ak?に第2のメtす%#i’
+6+の一部のデータ端子Dk、’j=の出力2人力し
、第2のメtり装置tlt6)の他の一部のデータ端子
D1〜Dk出力(図示の例で8進のデータ)をヂ]−ダ
(7)でデコードしてそのデコード出力により各スリー
ステートバッファ(4□9〜を別画するようにしである
。従ってこの実施例のものにあっては、自己保持機能が
出力点数さ同数だけ得られ、−!たCPU合有していな
いため安価かつ小型であるという前記第2図実施例のも
のと1鴨等の効果が得られる他、内部すし−の一部をも
自己保持可能とすることかできる効果を有するものであ
る。
FIG. 3 shows another embodiment circuit of the present invention,
In addition to the embodiment shown in FIG. 2, a part of the CR internal relay can also be self-maintained. Here T
The CR internal relay is a saturation element formed in the memory device b (3) for the purpose of obtaining a timer function.
The functional operation of the CR internal relay can be controlled by applying an input to the address terminals 1 to 1 of the main E'J device 1:1 corresponding to the internal relay. In the example of FIG. 3 of the χ lever,
Similarly to the embodiment in FIG. 2, each output from the data terminals D1 to D1 of the memory device (3) is
1) Feedback to the address terminal on the input side via ~, and the address terminal Ak? corresponding to the memory device (3) OCR internal relay. Second method%#i'
The outputs of some data terminals Dk and 'j= of +6+ are inputted, and the outputs of some other data terminals D1 to Dk (octal data in the illustrated example) of the second metering device tlt6) areヂ]-da (7) and decodes each three-state buffer (4□9~) according to the decoded output.Therefore, in this embodiment, the self-holding function depends on the number of output points. In addition to obtaining the same number of chips as in the embodiment shown in FIG. It has the effect of being able to be retained.

本発明は上述のように、メtり装置のデータ端子出力を
スリーステートバッファを介してアドレス端子入力にフ
ィードバックし、このスリーステートバッファ?%2の
メモリ装置のデータ端子出力で制御するようにしたので
CPU1に有さすメモリ装置だけで構成されて安価かつ
小型のものである2にもかかわらず、出力点数と同数の
自己保持機能が得られ、使用機能が大巾に向上する効果
を有するものである。
As described above, the present invention feeds back the data terminal output of the metering device to the address terminal input via the three-state buffer, and the three-state buffer? Since it is controlled by the data terminal output of the memory device of %2, it is possible to obtain the same number of self-holding functions as the number of output points, even though it is made up of only the memory device included in the CPU 1 and is inexpensive and small. This has the effect of greatly improving the usable functions.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の回路図、第2図は本発明の第1の実施
例の回路図、第3図は本発明の第2の実施例の回路図で
あり、(1)は入力回路、(2)は出力回路、(3)は
メモリ装置、(4□)〜はスリーステートバッファ、(
5)はフィードバック回路、(6)は第2のメモリ装置
、(7)はヂコータである。 代理人 弁理士  石 1)長 七
Fig. 1 is a circuit diagram of a conventional example, Fig. 2 is a circuit diagram of a first embodiment of the present invention, Fig. 3 is a circuit diagram of a second embodiment of the present invention, and (1) is an input circuit. , (2) is an output circuit, (3) is a memory device, (4□) ~ is a three-state buffer, (
5) is a feedback circuit, (6) is a second memory device, and (7) is a decoder. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

【特許請求の範囲】 Fl+  複数の入力信号を取込む入力回路と、複数個
の負荷機器を夫々制御する出力回路と、上記入力回路の
複数の出力?アドレス端子に入力するとともにデータ端
子出力を上記出力回路の入力としたメモリ装置と?具備
し、各アドレス端子入力に対するデータ端子出力の状態
として出力回路の制御条件をメモリ装置にづロタラム設
定したシーケシ′ス制御装隆において、上記メモリ装置
の各データ端子出力を夫々スリーステートバッファを介
して各対応するアトしス端子にフィードバックするフィ
ードバック回路と、前記入力回路の各出力を夫々アドレ
ス端子に入力し自己保持の有無に関するデータを記憶す
る第2のメモリ装置とを設け、−へック回昂の各スリー
ステトハツファの動作tム           △ 制御するようにして成ることを特徴とするシーケシス制
御装置。 (2)  第2のメ七り装置の一部の出力端子の出力を
ヂコータでデコードした出力により各スリーステートバ
ッファの動作を制御するとともに、第2のメモリ装置の
他の一部の出力端子の出力をメtり装置のアドレス端子
に入力して成ることを特徴とする特許請求の範囲第1項
記載のシーケシス制御装置。
[Claims] Fl+ An input circuit that receives a plurality of input signals, an output circuit that respectively controls a plurality of load devices, and a plurality of outputs of the input circuit? What is a memory device in which input is input to the address terminal and data terminal output is input to the above output circuit? In the sequence control system, the control conditions of the output circuit are set in rotoram based on the memory device as the state of the data terminal output for each address terminal input. and a second memory device that inputs each output of the input circuit to the address terminal and stores data regarding the presence or absence of self-holding. A sequence control device characterized in that it is configured to control the operation of each of the three stages of regeneration. (2) The operation of each three-state buffer is controlled by the output of some output terminals of the second memory device decoded by a decoder, and the output of some other output terminals of the second memory device is 2. The sequence control device according to claim 1, wherein the output is input to an address terminal of a metering device.
JP9351382A 1982-05-31 1982-05-31 Sequency control device Pending JPS58211207A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9351382A JPS58211207A (en) 1982-05-31 1982-05-31 Sequency control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9351382A JPS58211207A (en) 1982-05-31 1982-05-31 Sequency control device

Publications (1)

Publication Number Publication Date
JPS58211207A true JPS58211207A (en) 1983-12-08

Family

ID=14084423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9351382A Pending JPS58211207A (en) 1982-05-31 1982-05-31 Sequency control device

Country Status (1)

Country Link
JP (1) JPS58211207A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0499695A2 (en) * 1991-02-22 1992-08-26 Siemens Aktiengesellschaft Programmable logic controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0499695A2 (en) * 1991-02-22 1992-08-26 Siemens Aktiengesellschaft Programmable logic controller
US5475583A (en) * 1991-02-22 1995-12-12 Siemens Aktiengesellschaft Programmable control system including a logic module and a method for programming

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