JPS58206220A - Variable attenuating circuit - Google Patents

Variable attenuating circuit

Info

Publication number
JPS58206220A
JPS58206220A JP9075082A JP9075082A JPS58206220A JP S58206220 A JPS58206220 A JP S58206220A JP 9075082 A JP9075082 A JP 9075082A JP 9075082 A JP9075082 A JP 9075082A JP S58206220 A JPS58206220 A JP S58206220A
Authority
JP
Japan
Prior art keywords
resistance
resistor
value
train
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9075082A
Other languages
Japanese (ja)
Inventor
Shinya Sano
信哉 佐野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9075082A priority Critical patent/JPS58206220A/en
Publication of JPS58206220A publication Critical patent/JPS58206220A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/24Frequency- independent attenuators
    • H03H7/25Frequency- independent attenuators comprising an element controlled by an electric or magnetic variable

Landscapes

  • Attenuators (AREA)

Abstract

PURPOSE:To reduce greatly the overall resistance value and to reduce greatly the area needed for the resistance on an IC, by reducing the value of each resistance train down to half successively until a certain place from the input side and setting the value of each resistance of the 1st resistance train so that a current is branched into half at the branching point of each resistance. CONSTITUTION:The values of resistances of the 2nd resistance train 3 are set at 2R, R, R/2, R/4, R/4... from the input side; while the resistances of the 1st resistance of the the 1st resistance train 2 are set at 3R/2, 3R/4, 3R/8, R/8, R/8...R/8, respectively. Such a ladder resistance circuit is applied to an IC to reduce greatly the resistance area on the IC. In addition, extreme cost reduction is attained.

Description

【発明の詳細な説明】 本発明は、ラダー抵抗回路によるディジタル制従来のR
−21ラダ一抵抗回路による可変減衰回路の例を第1図
に示す。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a digital system using a ladder resistance circuit.
An example of a variable attenuation circuit using a -21 ladder-resistance circuit is shown in FIG.

第1図において、1は入力端、2は抵抗値Rの複数の抵
抗を寵列釦接続した第1の抵抗列、3は抵抗値2Rの複
数の抵抗を並列に接続した第2の抵抗列、4は第2の抵
抗列3の各抵抗を接地または出力端に切換えるための複
数のスイッチで構成されたスイッチ列、6は出力端であ
る。
In Figure 1, 1 is an input terminal, 2 is a first resistor string in which a plurality of resistors with a resistance value R are connected in parallel, and 3 is a second resistor string in which a plurality of resistors with a resistance value 2R are connected in parallel. , 4 is a switch array composed of a plurality of switches for switching each resistor of the second resistor array 3 to ground or an output terminal, and 6 is an output terminal.

通常、第1図に示すR−2Rラダ一抵抗回路の出力端6
は、オペアンプの反転入力端で受けられ、電流が電圧に
変臭される。
Usually, the output terminal 6 of the R-2R ladder-resistance circuit shown in FIG.
is received at the inverting input of the operational amplifier, converting the current into a voltage.

君1図に示すR−2Rラダ一抵抗回路では、入力端1に
流入する電流工は第2の抵抗列3へ入力側から順に−1
,−I、−I、・山・・ずつ分流して行2   4  
 8 く。
In the R-2R ladder-resistance circuit shown in Figure 1, the current flowing into the input terminal 1 is -1 in order from the input side to the second resistor string 3.
, -I, -I,・mountain・・divide each row 2 4
8.

そこで、スイッチ列4をある組合せで動作させることに
より、出力端5側に切換えられたスイッチに対応する分
流電流の和が出力端5へ流れ、そこで電圧に変臭される
ため、スイッチ列4の組合このようなR−2Rラダ一抵
抗回路の入力インピーダンスは、スイッチ列4の各スイ
ッチの状態に無関係に常に一定で、その値はRとなる。
Therefore, by operating the switch row 4 in a certain combination, the sum of the shunt currents corresponding to the switches switched to the output end 5 side flows to the output end 5, where it is converted into voltage. The input impedance of such a combined R-2R ladder-resistance circuit is always constant regardless of the state of each switch in the switch array 4, and its value is R.

ところで、このような可変減衰器をオーディオアンプの
音量制御等に用いる場合、入力側に接続される機器の出
力インピーダンスの関係から、入力インピーダンスをか
なり高く設定しなければならない。
By the way, when such a variable attenuator is used for controlling the volume of an audio amplifier, the input impedance must be set quite high due to the output impedance of the equipment connected to the input side.

しかし、このようなR−2)1抵抗回格は普通ICで構
成されるが、ICで通常用いられる抵抗は拡散抵抗の場
合でも多結晶シリコン抵抗の場合でも、その直はかなり
低いため、入力インピーダンスを高くしようとすれば、
かなり広い面積を必要とし、コスト高になってしまうと
いう問題があった。
However, such an R-2)1 resistor circuit is usually constructed with an IC, but the resistance normally used in an IC, whether it is a diffused resistor or a polycrystalline silicon resistor, is quite low in resistance, so the input If you try to increase the impedance,
This has the problem of requiring a fairly large area and resulting in high costs.

本発明は、R−2Rラダ一抵抗回路の性質を維持しなが
ら、同じ入力インピーダンスに対して、IC上の抵抗の
ための必要面1を大幅に減少させ千 ることのできる可変減衰回路を提供するものであ分流さ
れるように、君1の抵抗列の各抵抗の値を3   3 
  3 入力端から順に、−R、−R、−R・・・・・と設定す
2   4   8 ることにより、全抵抗直を大巾項に減少させるようにし
たものである。
The present invention provides a variable attenuation circuit that can significantly reduce the surface requirements for resistors on the IC for the same input impedance while maintaining the properties of an R-2R ladder resistor circuit. The value of each resistor in the resistor string of you 1 is 3 3
3 By setting -R, -R, -R, .

第2図に本発明の一実施例を示す、。第2図において第
1図と対応する部分には第1図と同一の符号を付してい
る。
FIG. 2 shows an embodiment of the present invention. In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals as in FIG. 1.

第2図の実施例でf’l: 、第2の抵抗列3の各抵抗
−Rとなるように設定したものである。
In the embodiment shown in FIG. 2, f'l: and each resistance of the second resistor array 3 are set to -R.

このように抵抗値を設ポした場合でも、スイッチ列4に
流入する電流値は、第1図の場合と同様可変減衰器とし
ての動作は、第1図の場合と全く同じである。
Even when the resistance value is set in this way, the current value flowing into the switch array 4 is the same as in the case of FIG. 1, and the operation as a variable attenuator is exactly the same as in the case of FIG.

また入力インピーダンスの値もRとなり、第1図の場合
と全く同じである。
Further, the value of the input impedance is also R, which is exactly the same as in the case of FIG.

例えば、スイッチ列4のスイッチ個数を16個(16ビ
ツト)とすると、第1図の例では、全抵抗値が491と
なるのに対し、第2図の実施例では、11 、3751
 となり□に減少させられる。
For example, if the number of switches in the switch row 4 is 16 (16 bits), the total resistance value is 491 in the example of FIG. 1, while it is 11,3751 in the example of FIG.
Therefore, it is reduced to □.

4.3 したがって、本発明によるラダー抵抗回路をICに用い
れば、IC上の抵抗面積を大幅に減少させることができ
、大幅なコストダウンができるという効果がある。
4.3 Therefore, if the ladder resistance circuit according to the present invention is used in an IC, the resistance area on the IC can be significantly reduced, resulting in a significant cost reduction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の回路図、第2図は本発明の一実、施例
の回路図である。 1・・・・・・入力端、2・・・・・・第1の抵抗列、
3・・・・・第2の抵抗列、4・・・・・・スイッチ列
、5・・・・・・出力端。
FIG. 1 is a circuit diagram of a conventional example, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 1...Input end, 2...First resistor string,
3... Second resistor string, 4... Switch string, 5... Output end.

Claims (1)

【特許請求の範囲】[Claims] 複数個の抵抗が直列接続されて成る第1の抵抗から成る
第2の抵抗列と、上記第2の抵抗列の各抵抗の他端を接
地および出力端に切換え接続する複数のスイッチから成
るスイッチ列とで構成され、上記第1の抵抗列の入力側
からN(但しNは整数)(但しRは単位抵抗値)、それ
以降の各抵抗の値を特徴とする可変減衰回路。
A switch consisting of a second resistor string consisting of a first resistor made up of a plurality of resistors connected in series, and a plurality of switches that switch and connect the other end of each resistor of the second resistor string to ground and an output terminal. N (where N is an integer) (where R is a unit resistance value) from the input side of the first resistor array, and the variable attenuation circuit is characterized by a value of each resistor thereafter.
JP9075082A 1982-05-27 1982-05-27 Variable attenuating circuit Pending JPS58206220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9075082A JPS58206220A (en) 1982-05-27 1982-05-27 Variable attenuating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9075082A JPS58206220A (en) 1982-05-27 1982-05-27 Variable attenuating circuit

Publications (1)

Publication Number Publication Date
JPS58206220A true JPS58206220A (en) 1983-12-01

Family

ID=14007272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9075082A Pending JPS58206220A (en) 1982-05-27 1982-05-27 Variable attenuating circuit

Country Status (1)

Country Link
JP (1) JPS58206220A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897599A (en) * 1985-03-27 1990-01-30 Createc Gesellschaft Fur Elektrotechnik Mbh Signal processing device with a level adapter circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897599A (en) * 1985-03-27 1990-01-30 Createc Gesellschaft Fur Elektrotechnik Mbh Signal processing device with a level adapter circuit

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