JPS58204654A - Composite loop transmitting system of multiple information including traffic control - Google Patents

Abstract

PURPOSE:To match and transmit a real time signal and a packet of data, by observing the traffic passing through a terminal during the transmission repetitive period of the packet of real time signal in advance, and controlling the transmission of the real time signal with the obtained passing traffic quantity. CONSTITUTION:A pulse is obtained from a signal on a signal line 958 at every period of the transmission of sound packet, and counters 905, 906 counts the number of the sound packet and data packet passing through the terminal during the period of the sound packet transmission. The signal on signal lines 959, 950 is transmitted to a latch 907, the value is kept during the period of sound packet transmission and outputted on a signal line 961. The signal representing the amount of traffic passing on the signal line 961 is inputted to a discriminating circuit 908, and from the amount of passing traffic detected, then whether or not the sound signal is transmittable is discriminated, and the result of discrimination is outputted from a signal line 762.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a loop transmission method for performing packet communication between terminals in a loop transmission system having a plurality of transmitting/receiving terminals and one control terminal connected in a loop.

Conventionally, a time-division multiplexing method that adopts a frame structure has been known as the RJ method for networks where voice terminals and data terminals coexist.This method guarantees real-time performance for voice. However, for the data,
It is not suitable because it cannot easily accommodate data terminals of various speeds and cannot accommodate high-speed data terminals. As a proposed method, a packet multiplexing method focusing on data has been proposed. For data, this method is compatible with various speed terminals and allows flexible system configurations, but for voice, there is a delay that depends on line activity, and real-time performance is not possible. Not very suitable as it is not guaranteed. Note that another example of a signal having real-time characteristics is a moving image signal. In the following description, unless otherwise specified, real-time signal packets and voice packets will be treated as synonyms. As a method to improve these two methods, one frame 100 is divided into two subframes by setting a boundary as shown in FIG. Use as frame and other subframe 1
A method has been proposed in which 02 is used as a subframe for packet multiplexing. 1. However, this method is
It has the disadvantage that efficiency decreases when data traffic is biased to one side. That is, for example, in a situation where voice traffic is high and data traffic is low,
Even if there is free space in the data subframe, voice cannot use it, resulting in low efficiency. In order to overcome this drawback, a method of adaptively moving the boundary of the F frame 100 according to the traffic condition is proposed by I-Triple E Transactions, On-Fist Communications, Volume C0M-2Q, Number 6, June.

1981 (IEEE Transactions o
n Communi-cations June 19
81 YOU, 00M-29ffi6) 1Performance Evaluation Spring of I Triple E-M Multiplexer by B. Maglaris (B. Maglaris) and M. Schwartz (M. Schwartz) "Integrated Switched Networks"("Per
formance kvaluatiorLof aV
ariableFrameλmultiplexer
for Inte-grated 5w1tched
However, the method described in this document requires a central control terminal that monitors the traffic status, so it has the disadvantage that control becomes extremely complicated. .

Furthermore, as a method for efficiently transmitting and receiving voice and data signals via a loop-shaped transmission path, I-Triple E Transaction Zoo On Communications Volume 00M-22, Number 6, June, 1
974 (IFiEE 'I'transactions
on Communications VOL, 00
M-22NQ6 June 1974) 1Azo 4 Digital Lube Communication System by E.R. Hafer (B, R, Hafer) etc. on JIM''
(”A DigitalLoop Ommunic
The register insertion method shown in the sentence entitled atio, n System @) is known. Each terminal to which this register insertion method is used basically consists of transmitting/receiving registers 202, 203 and a switch 204, as shown in FIG.

This register insertion method has the characteristics that it is possible to transmit packets with almost no waiting time, regardless of the degree of loop congestion, and that exchange control can be completely distributed. Also,
Data transfer time, including waiting time at the terminal, is short and throughput characteristics are good. However, the transfer time of this register insertion method depends on the congestion of the loop and has a drawback that it is not suitable for voice communication because of large variations.

SUMMARY OF THE INVENTION An object of the present invention is to provide a loop transmission system capable of transmitting real-time signals and data with good consistency by eliminating the drawbacks of the conventional system described above and with efficient and easy control.

According to the present invention, real-time signal buckets are given high priority, data packets are given low priority, and packets with high priority are prioritized so that there is no delay when passing through each transmitting and receiving terminal. Controls the communication path within the sending and receiving terminals. Furthermore, in order to prevent the number of data packets from increasing excessively, when transmitting a real-time signal, the transmission repetition period of the high-priority real-time signal (word packet) must be adjusted prior to transmission. Observing the traffic passing through the terminal,
By fully controlling the transmission of real-time signals according to the amount of passing traffic obtained, a multi-source 1a signal complex loop transmission system including traffic control that fully matches the real-time signal bout and data bucket can be obtained. The principle of the present invention will be explained with reference to FIG. 3-c.

In FIG. 3, the transmitting/receiving terminal includes a human buffer memory 302, an output buffer memory 303, a block 304 having a circuit for decoding a computer address, a priority 11j determination circuit, a receiving circuit, and As shown in the figure, 1.2.3 is connected to each terminal of the switch 305 which selects the communication path and the detector 306 which detects the passing traffic 9k. number has been assigned.

The number 1 on the signal line 352 indicates the control number 14 that controls the switch 305. , a priority control method for a data terminal will be described.The control method when a data packet is input to the output buffer memory 303 and a transmission request occurs is as follows.

l) When a packet with a higher priority than the data packet requested to be sent is input from the transmission path 300 or is about to be output from the input buffer memo 'J302: The data packet requested to be sent remains stored in the output buffer memory 303 and is not output to the transmission line.

The switch 305 operates to pass one packet having a higher priority between the packet input from the transmission path 300 and the packet about to be output from the manual buffer memory 302. If the two packets have the same priority, the packet output from the input buffer memory 302 has priority.

2) When a packet with a priority lower than the data packet requested to be transmitted is input from the input transmission path 300 or is about to be output from the input buffer memory: The data packet requested to be transmitted is Output buffer memo IJ 3 (input bucket sent from 13 to output transmission path 301 and input from input transmission path 300) t:1 4Iλ notes are saved in manual buffer memory 302.

Next, the control after the transmission of the transmission data packet is completed is as follows.

l) When the priority is higher than the packet input from the input transmission path 300 or the packet stored in the input buffer memory 302 (packet waiting for output): The packet waiting for output that has been accumulated in the input buffer memory 302 The switch 305 is controlled so that the packets remain stored and the manually inputted packets are sent out to the output transmission path 301 from the transmission path.

2) When the priority of the next packet input from the transmission path is lower than the priority of the packet waiting for output in the input buffer memory 302: The packet waiting for output stored in the manual buffer memory 302 is sent to the transmission path 301. Input packets sent out and input from the transmission path 300 are stored in the input buffer memory 302.
is accumulated in

, to Ll! The same control is applied to input packets from subsequent transmission paths, and in extreme cases, voice bucket B
! If "high priority" continues in succession, the data packets 11 stored in the manual buffer memory 302 are stored in the manual buffer memory 302, but voice packets have the highest priority. Therefore, there is no need to save it in the input buffer memory in the terminal. In this way, since voice packets are not saved in the human buffer f memory in the r1 terminal, as voice packet activity and f increase, data packets will be delayed more, leading to unfairness between different types of packets. become. Something like this f
i comb! A passing traffic amount detection circuit 306 is provided to accommodate audio and data packets in a well-matched manner. This passing tiger hinge lid detection circuit 306 detects the number of voice pitches and the number of data packets that pass during the transmission repetition period of the sound %f bout, and detects the number of data packets through the signal line 353. 7. Informs whether or not audio packets can be sent to the news source. The control means for the switch 305 in the circuit shown in FIG. 3 will be explained with reference to the two νs in FIGS. 4 and 5-1.

In FIG. 4, a rectangular box 1j indicates one packet, and alphanumeric characters within the rectangular box indicate the packet name. The alphabet V indicates a voice packet, and the letter D indicates a data packet.
-Show it. Here, it is assumed that the stj voice packet has a higher priority than the data bound, and all data packets have the same priority as the ICIj. Now, arrow 11 in Figure 4(a)
At the hit point I)! Assuming that a packet sending Lf request occurs, ■), t: t7, and the packets have the same priority and there are 10, so D, the packet is input buffer memo +) 3 o 2 (Fig. 3 ), the volume is evacuated to 〃・
Instead, 1) the switch 305 is selected so that the pow note is output to the transmission line 301; FIG. 4(b) is a diagram showing the state of the output transmission path at the time when l packet time has elapsed from FIG. 4(a).
The packet D1 stored in the input buffer memory 302 remains stored in the input buffer memory 302 because the next packet manually input from the transmission path 300 is voice pound v, and the voice packet v2 has a higher priority. Switch 305 is controlled so that packet v2 is sent to output transmission path 301. Next, Fig. 4(c) after one bucket time has passed.
2, the packet DI stored in the manual buffer memory 302 remains stored in the manual buffer memory 302 because the next packet input from the transmission line 300 is the combined packet vI. packet v1
switch 305 so that the signal is sent to the output transmission line 301.
is controlled. In FIG. 4(d), one bucket time has elapsed since "'<C" in FIG. The switch 305 is controlled so that the packet D, which is present in the packet D, is sent to the output transmission path 301. In FIG. 4 (7).

Packet D is output to the transmission path 301 and the packet input from the transmission path 300 is an empty packet, and there are no transmission request packets or packets stored in the human-powered buffer memory 302 waiting to be output. Switch 305 is controlled to directly connect the output transmission line.

The control procedure of the circuit shown in FIG. 3 will be explained using the example shown in FIG. now,
Suppose that a request to send packet D occurs at the time indicated by the arrow in FIG. The switch 305 is controlled so that the packet is stored and saved, and the packet is output to the transmission path instead. In FIG. 5(b), since the packet manually inputted from the transmission path 300 is an empty bound, the switch 305 is activated so that the packet D1 stacked in the input buffer memory 302 is sent to the output transmission path 301. is controlled. In FIG. 5(c), since the signal inputted from the transmission path 300 is a voice packet (■), the switch is controlled to directly connect the input transmission path 300 and the output transmission path 301, and the data packet 1 is ), and the voice packet vI are continuous packets as shown in the figure. As is clear from the examples in FIGS. 4 and 5, data packets may be preceded by voice packets, increasing the delay, but voice packets are not delayed at the terminal. In other words, the voice packet once sent to the transmission path will thereafter arrive at the other party's terminal without any delay caused by the buffer memory.

Next, the transmission control based on the traffic of voice packets passing through the transmitting and receiving terminals will be explained. Now, assume that the transmission path speed is 7 seconds for C packets. If the transmission repetition period of voice packets is T seconds, the transmission path has the ability to transmit OT packets for T seconds. Let the number of data packets passing through the transmitting and receiving terminal during T seconds be ND+the number of voice packets be Nv. At this time, for example, if the following conditions are met, audio transmission is possible. .

■ When Nn + Nv < C.

1 ■ For Nn -1-Nv = CT, ND<20
When T, the above example condition is only 11? IJ, which varies from Condition 1 depending on the number of voice terminals, the number of data terminals, the call loss rate required of the voice terminals, the maximum amount of data delay, etc.

Changes in conditions due to these external factors are included in this method.

Hereinafter, an embodiment τ for implementing the method of the present invention will be shown with reference to FIG. 1m.

FIG. 10 is a diagram showing the basic configuration of the system.

In the figure, signals flow in the direction indicated by the arrow on transmission line 1000. The control terminal toot has each transmission/reception-Song 1002 (1
) to 1002 (to), a signal indicating the head position of the packet is periodically sent out, and loop synchronization is established kQ so that the loop-to-circuit transmission line delay is an integral multiple of the packet length. cormorant. Six pieces of equipment are connected to each transmitter/receiver 14i tree.

, PA:1 FIG. 6 shows an example of the packet structure used in the system of FIG. In the figure, Ml indicates a marker bit, 911 indicates a used packet, and 70'' indicates an empty packet. P indicates a priority report, and a numerical value corresponding to the priority type of the information source accommodated in the system is assigned. ■ is a bit indicating whether it is a voice packet or a data bucket, and is 11°
(sound μ packet), and “Q” indicates a data packet. In this example, a bit indicating whether a snoring packet or a data bucket is provided separately from the priority information, but it is also possible to determine whether the priority is a voice packet or a data bucket. ADI is transmission address T# information, and M D2 is reception address information. The field indicated by D indicates an information field.

FIG. 7 shows an embodiment of a transmitting/receiving terminal used in the system of FIG. 10. In FIG. 7, an input packet from an input & transmission M701 is given to a shift register 703. Shift register 703 #j serial input terminal and
It has two types of output terminals in parallel, and has the same length as the packet header length. The header ↑η information of shift register 7 (13) is output from the parallel output terminal as parallel 11 information to signal Ij; A751. The received address of the header information is given to the address matching circuit 705, and the marker bit and priority information is manually input to the priority selection circuit 704. When the manual packet passes through the shift register 703, it is subjected to a delay corresponding to the header formation.Address matching circuit 70
5 is easily constituted by an exclusive-ground gate, which compares the received address of the manual packet with the address of the terminal and outputs a match/mismatch signal to the signal line 755. When the receiving address and the terminal address match, the input packet t is a packet that is received by the terminal (a), so the marker bit of the manually-operated packet must be erased to make it an empty packet.

For this reason, the address verification circuit 705 outputs the service marker eraser i number a to (i4 &!752).

The marker bit in the header information stored in the shift register is erased by the marker erase signal of the signal IM7s2. Point F! IA! R circuit 704 receives signal 4Q7
The marker bit and priority 1*@i of the input packet given through 51, the marker bit and priority 1# information of the output waiting packet accumulated and saved in the manual buffer memory 706, and the signal given from the output buffer memory 708. A signal for selecting the highest priority packet based on the marker bit and priority information of the packet to be sent out and a status signal representing a control signal for the input/output buffer memory, etc. are output to the signal line 756. A conversion circuit 707 converts the packetized signal into an information signal suitable for various devices connected to the terminal. The input packet from the C=number line 750 is input to the na-otchi conversion circuit 707, and if the output signal of the address matching circuit on the signal line 755 is a match signal, a signal is sent to the denomination device connected to the data terminal. 11757 to send out information signals. Reference numeral 711 is a passing traffic amount detection circuit, which counts data buckets and audio packets from the header information coming from the signal 8751 and the audio packet transmission period, and detects the amount of traffic passing through the transmitting and receiving terminals (
M issue, 1illi! The detection result is output to 762 and notified to the 8-voice terminal. From various devices connected to this sending/receiving terminal (7) 1ik 'di Gi ``y ri, '
= s"t N 758 k Intermediately, the -C data is sent manually to the packet conversion circuit 709, where it is given header information and converted into a packet with a fixed size of lfT.
It is output to line t 759. Shinkoto Line 7.・The signal 759 is accumulated in the output buffer memory 708 and sent to the signal line 760.
Waits for transmission to the transmission path via. Whether or not the transmission line can be transmitted via the signal line 760 is controlled by the status signal of the signal line 756. Marker bits and priority information are outputted to a signal line 754 among the header ↑n information of the outgoing packet stored in the output buffer memory 708 and waiting to be sent out next to the transmission line. The input buffer memory 706 temporarily accumulates and saves packets that are not sent to the output transmission path by the switch 710 among the human-powered packets from the signal line 750. Accumulation in the manual buffer memory 706
Whether or not it can be saved and whether it can be sent from the manual buffer memory 706 to the output transmission line 702 is controlled by the status signal on the signal line 756. Marker bits and priority information among the delayed packets stored in the input pan 7 memory 706 are output to the signal line ÷53.

The switch 71O is controlled by a state signal from the signal fii 756 to select the packet with the highest priority among the manual packet from the signal line 750, the delayed packet from the signal line 761, and the sent packet from the signal My 760.

I: FIG. 8 is a detailed circuit diagram of the priority selection circuit 704 shown in FIG. 7. In the figure, signal lines 850 and 851 are the seventh
The signal output from the output buffer memory 708 in the figure!
Similarly, signals i 852 and 853 indicate the marker bit and priority information output from the input buffer memory 706, and signals M854 and 855 indicate the marker bits and priority information expressed by the input buffer memory 706. Indicates marker bits and priority information for input packets. AND gate circuits 801 and 802 take the id product of the input marker bit and each bit of priority information, and output the result as signals [856 and 857, respectively. For example, if the marker bit is 111, the output signal of the AND gate circuit is the same as the input priority information, and if the marker bit is @0@, the output signal of the AND gate circuit is all O. In addition to the marker bit and the priority information, the AND gate circuit 803 receives an address match signal from the signal line 755, and performs a logical product of the address match signal, the marker bit, and each bit of the priority ↑N information. For example, if the γ address match signal on the signal line 755 is 1'' (1aI, the receiving address of the manual packet and the terminal address do not match) and the marker bit is 11'', the signal on the signal line 858 is the input iron tip 1a information. If they are the same and the address matching signal is "0" (that is, the received address of the manual packet and the terminal address match) or the marker bit is 106, all ft4 of the signal line 858 becomes O. Signals #j 856, 857, and 858 are manually input to the highest priority detecting circuit 804, and a code indicating the highest priority is output as a 2-bit signal to a signal line 859 while maintaining the same state for l bucket time. The fd edge line 859 signal becomes a control signal for the switch 710 in FIG. 7 and an output control signal for the input/output buffer notes IJ 706 and 707. The signal indicating the marker bit of the manually-powered packet on the signal line 854 and the signal on the signal line 859 are manually sent to the gate circuit 805.
Marker via of signal line 854 (signal line 854 marker via)
If the signal 1Illi 1859 does not select the switch to send the manual packet to the output transmission path, it is output to the input packet storage command signal line 860 in the manual buffer memory 706 in FIG. signal line 85
Signals 9 and 860 correspond to signal 11M756 in FIG.

FIG. 9 shows an example of the circuit configuration of the passing traffic amount detection circuit shown at 711 in FIG. The marker bit in the header information manually entered from the signal line 950 is 4g m951
The sound hpat bit in the header information input from the AND gate 901 is ANDed and the signal l11j95
4 is output. The signal line 952 is a packet period clock signal °, which is connected to the signal #j 954 and the AND gate 90.
3 is ANDed and output to signal line 956. That is,
One clock signal is output from the fa line 56 when a voice packet arrives. Similarly, signal 4! The audio packet bit of a951 is inverted by an inverter 900 and output to line 14 953.

Furthermore, the signal on the signal line 953 and the signal on the signal line 950 are 9
The AND gate of 02 performs a logical product, and the signal line 957
is output to. That is, one clock is output when a data packet reaches the signal t on the signal line 957. The signals on signal lines 956 and 957 are 9, respectively.
05 and 906 are manually operated, the counter 905 increments the counter value each time a voice bucket arrives, and the counter 906 increments the counter value each time a data bucket arrives, and signal lines 959 and 9 respectively
The counter value is output to 60. Also, a signal from a signal line 958 is input manually as a reset input for the 905°9060 counter. The signal on the signal line 958 generates a pulse every audio bucket transmission period, and the counters 905 and 906 count the number of audio packets and data packets passing through the terminal during the audio bucket transmission period.

The signals on the signal lines 959 and 960 are inputted manually at the launch of the signal line 907 and are output to the signal line 961 while maintaining the open chain of the 14th period of voice packet transmission. The signal representing the passing traffic of signal [961] is inputted to the determination circuit 908, which determines whether or not an audio signal can be transmitted from the detected passing traffic cover, and outputs the determination result to signal 411762.
Notify the connected audio terminal.

As described above, in the present invention, voice packets receive high priority I! By giving 7L and giving low priority to data packets, voice packets with high priority can be sent without delay. Also, according to the invention, control is completely decentralized. Furthermore, by controlling the transmission of audio signals based on the amount of traffic passing through the terminal, both data packets and audio packets can be accommodated in the system with good consistency.

Note that although the above explanation has focused on buckets with two types of priorities: voice packets and data packets, the present invention also includes further subdivision of priorities depending on the nature of the information source. Of course.

[Brief explanation of drawings]

Figure 1 is a frame configuration diagram in which one frame is divided into a time division subframe and a bucket multiplexing subframe.
The figure shows a timing chart of transmitting/receiving end transmission method 6 using a register insertion method. Fig. 6 shows a configuration example of the bucket 7) used in the present invention. Fig. 7 shows an example of the configuration of the bucket 7) used in the present invention. 8 is a diagram showing an embodiment of the priority selection circuit used in FIG. 7, and FIG. 9 is an example of the passing traffic amount detection circuit used in FIG. 7. FIG. 10 is a block diagram showing a system configuration to which the present invention is applied. In the figure, 200... input transmission line, 201... output transmission line, 202... receiving register, 203... transmitting register, 204... switch, 300... input transmission line, 301... Output transmission path, 302... Input buffer memory IJ, 303 - Output buffer memory, 304... Priority determination circuit, 305... Switch,
306... Passing traffic detection circuit, 701...
Manual transmission line, 702... Output transmission line, 703 Shift register, 704... Priority selection circuit, 705...
Address verification circuit, 706...input buffer memory,
707°...conversion circuit, 708...output buffer memory L709'' bucketing circuit, 710...switch, 711...passing traffic violet detection circuit, 801,80
2゜803-.°AND circuit, 805...gate circuit, 804...highest priority detection circuit, 901,902,90
3゜904... Ant game), 900... Inverter, 905.906... Counter, 907... Latch, 908... Judgment circuit, 1001... Control terminal,
1000...Transmission path, 1002(1) to 1002(N
)...Sending and receiving Iha Duan Song. Agent No ``・111, 1 sect 1゛1゛,
7 Special 1 Figure Pier 2 Figure 30θ

Claims (1)

[Claims] In a loop transmission method in which a plurality of transmitting/receiving terminals and one control terminal are connected in a loop and packet communication is performed between each transmitting/receiving terminal, the control terminal periodically transmits a signal indicating the leading position of a packet. Establishing loop synchronization so that the transmission path delay when transmitting the packet and going around the loop is an integral multiple of the length of the packet and node,
Among the information packets from the transmitting/receiving terminal, real-time information packets that require real-time characteristics are given a first high priority, and information packets that do not require real-time characteristics are given a second, low priority; Each of the transmitting/receiving terminals includes a first storage means for storing and saving human-powered packets from the human-powered transmission path, and a second storage means for storing packets sent from an information generating device connected to the transmitting/receiving terminal. The priority of the manual packet, the transport packet which is the output packet from the first storage means, and the outgoing packet is compared, and the packet with the highest priority is sent out to the output transmission path. When transmitting a real-time message consisting of a collection of multiple real-time ↑d message buckets with the first highest priority from the sending/receiving terminal of the , detecting the respective traffic amounts of real-time information packets and data packets from the number of real-time information packets and data packets passing through the first transmitting/receiving terminal during the repetition period of the real-time information packet transmission, and A multiple information complex loop transmission system including traffic control, characterized in that the transmission of the real-time information message is started when the detected traffic amount exceeds a predetermined condition tf8.