JPS58197962A - Synchronizing device - Google Patents

Abstract

PURPOSE:To discriminate the optimum phase, to reduce the generation of disturbance, and to easily execute conversion to IC, without frequency-dividing a clock pulse, by a delay of an oscillating output and discrimination of the optimum phase by detecting a sampling state due to each delay output. CONSTITUTION:A clock pulse of a repeating period of 1/2 is generated from an oscillating circuit 32, to a phase synchronizing signal of a repeating signal of a fixed period in a transmitting binary signal, its pulse is delayed by a time of 1/n each of the repeating period, and a clock pulse of (n) phases is generated. By use of this generated pulse, the phase synchronizing signal is sampled for a period of each prescribed bit number, and when its prescribed bit is sampled correctly, an output is generated from detecting circuits 37A-37H. In accordance with the output of these circuits 37A-37H, a clock pulse of phase suitable for the binary signal is discriminated from the clock pulse of (n) phases by discriminating circuits 48, 49. Subsequently, by an output of the circuits 48, 49, a pulse of prescribed phases out of the pulse of (n) phases is outputted from a clock pulse selecting circuit 51.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention optimizes the phase of a clock pulse for sampling a binary signal at a position where the binary signal transmitted including a phase synchronized signal consisting of a repetitive signal of a constant period is received. The purpose of this is to provide something that can be synchronized and has less interference.

2. Description of the Related Art So-called teletext broadcasting has been proposed as a means of multiplexing and transmitting separate new image information using television broadcast signals. This is additional image information that uses the vertical blanking period of a normal television broadcast signal to decompose and transmit additional image information such as characters or graphics during an arbitrary horizontal scanning period (for example, the 20th H). The signal is superimposed on a binary digital signal and transmitted. This additional image information signal is composed of a group of digital signals (called a data packet) having a certain number of bits (for example, 260 bits), and its contents consist of a header section and an information data section. There are different types of packets, such as page control packets, color code packets, and pattern data packets, depending on the content of the information contained in the data portion.

Page system (2) A packet is transmitted prior to transmitting one screen of additional image information, and its data portion includes page control code signals such as program number, page number, and code for warning screen deletion or screen update. It is. The color code packet is transmitted following the page control packet, and contains a color code indicating the color in which each character or unit segment of the additional image information is to be displayed. Furthermore, the pattern data packets are then transmitted continuously for one screen at a time (other packets may be inserted in the middle),
In the data portion, pattern data for each line is transmitted when the additional image information to be displayed is scanned in the horizontal direction. Note that there are several other types of data packets, but their explanation will be omitted here.

In addition, the header part of every data packet contains a clock line signal for synchronizing the data sampling clock on the receiving side, a framing code signal for frame synchronization, a service identification/interrupt control signal, and
A data identification signal indicating which type of data packet the data packet is is transmitted. Here, a signal capable of correcting a 1-bit error is used as the framing code signal, and a Hamming code capable of correcting a 1-bit error and removing a 2-bit error is used for each of the other signals.

Therefore, the receiving device receives the transmitted television signal on which such an additional image information signal is superimposed, and
Take out the additional image information signal among them, select only the signal of the desired program to be received using the page control packet, and store the color code data in the color code packet and pattern data in the pattern data packet of that program in memory.
The image information can be displayed on the screen by accumulating information for a screen, reading it out in synchronization with the screen scanning of the cathode ray tube, and converting it into an image signal for display. Generally, a normal television receiver is also used to receive additional image information, and a circuit for processing the additional image information signal is added, and when displaying the received image information, a cathode ray Image information such as character information is displayed on the tube screen by superimposing the received image (moving image) of a normal television broadcast program, or by erasing the received image.

By the way, in such a receiving device, in order to accurately receive the transmitted binary code, it is necessary to correctly sample each pit of the received signal using a clock pulse (hereinafter referred to as a sampling clock) for sampling the received signal. It is necessary to control the phase so that it can be controlled. Conventionally, for this purpose, a pulse with a frequency multiple times that of the binary code was created, the frequency of this pulse was divided to create several phases of sampling clocks, and one of them was selected and used. However, in this case, it was necessary to divide high-frequency pulses, and the frequency dividing circuit generated a high-level interference signal, which was inconvenient.

Therefore, the present invention provides a device free from such inconvenience, which oscillates a clock pulse having a repetition period that is half of the repetition period of the phase synchronization signal in binary coding, and 1/n of the repetition period
(n is an integer greater than or equal to 2) to create n-phase clock pulses, sample the phase synchronization signal with the n-phase clock pulses, and clock pulses that can correctly sample the phase synchronization signal of a predetermined number of pits. It is characterized by detecting which of the n phases the clock is in, determining the clock pulse of the optimum phase according to the detection output, and outputting the clock pulse as a binary coded sampling clock. . In this way, since it can be carried out by oscillation at a predetermined sampling frequency and delay, there is less interference, and since detection and discrimination can be performed by a digital processing circuit, it is possible to obtain something suitable for IC implementation. I can do it.

FIG. 3 shows a circuit diagram of a synchronizing device according to an embodiment of the present invention, and FIG.
The explanation will be given by showing waveform diagrams for explaining the operation in the figures.

First, in Fig. 3, 31 is the received television program = 1'
A PLL oscillation circuit that oscillates a clock pulse A having a repetition period of one half of the repetition period of the phase synchronization signal in the binary code in synchronization with the color subcarrier signal in the 7-signal,
Here, 815 f. An oscillation circuit 32 using a (-s, 73M) crystal oscillator, and a phase detection circuit 3 that compares the phases of the oscillation output and the color subcarrier signal to synchronize them.
3, and supplies the invention clock pulse A via a buffer amplifier 34. On the other hand, each of 36 is 1/n of the repetition period of clock pulse A (here, n;
8) A delay amplifier se having a delay time of 8)
A delay circuit configured by cascade-connecting clock pulse A to 36H is used to delay clock pulse A for one-eighth of its repetition period (approximately 2
A total of eight phases of clock pulses A to H are created by delaying the clock pulses by 2 n sec). Then, eight sets of detection circuits 37A to 37A to
At 37H, the phase synchronization signal with a constant repetition and period in the received signal as shown in FIG. 4A is sampled, and 8
It is detected which of the phase clock pulses can correctly sample the phase synchronization signal. Here, it is assumed that the phase synchronization signal, which is originally desirable to be received with a duty ratio of 60% like OR, has a narrow pulse width like CR/.

That is, in the detection circuit 37A, the supplied clock pulse A drives an 8-bit shift register asA to sequentially sample the received binary signal CR'. Then, the outputs of the 2nd, 4th, and 6.8th bits are applied to the NAND gate 39A, and the outputs of the 1st, 3rd, and 5.7th bits are applied to the negative logic NAND gate 39A. However, it is assumed that the shift register is reset in advance by a horizontal synchronization signal. Therefore, by clock pulse A, each
For each bit, the high level part (hereinafter referred to as "1") and the low level part (hereinafter referred to as '0') of the phase synchronization signal CR or CR/
''), the output IA of the gate 39A becomes "0" when the 7th bit of the phase period signals CR, CR/ is sampled, and from then on, sampling is performed every pit. '1'', l each time
On the other hand, the output IA of the Goo) 40A is the phase synchronization signal CR when sampling is performed correctly.

“1” every time sampling from the 1st pit of CR’.

0'', ``1'', etc. Then, add these 30A, 40AO outputs IA and IA to the T and N terminals of the 7 flip-flop 41A, and horizontally synchronize this flip-flop 41A. If it is reset by a signal, the Q terminal output KA of the flip-flop 41A will be reset at the time of the 7th bit sampling only when the phase synchronization signals CR, CR/ are correctly sampled by the clock pulse A in a predetermined horizontal period. From'1
``After the interpretation, every other pit is ``0'', 11m,...
...and reversed. And this flip-flop 41A
Q terminal output KA and ◇terminal output gA are added to the S terminals of flip-flops 42A and 43A, respectively, and Q terminal output LA of flip-flop 42A is added to flip-flop 43.
In addition to one terminal of A, these are also reset by a horizontal synchronizing signal.

Then, when the clock pulse A is correctly sampling, the output LA of the flip-flop 42A is
becomes 11" from the sampling of the 9th bit of the phase synchronization signals CR and CR', causing a free rough state.

The output MA of the flop 43A becomes "1" from the sampling of the 11th bit. If sampling is not performed correctly by clock A, both outputs LA and MA remain at "o".

The detection circuits 37B to 37H are also similar circuits, and sample the received phase synchronization signals CR and OR' using clock pulses BH whose phases are slightly shifted from each other.
Detection output LB=LH, MB-MH is output.

In the operation example shown in FIG. 4, when the phase synchronization signal OR' received in a distorted form is sampled by the detection circuits syA to 37H using eight phase clock pulses A-H, one of the clock pulses A -D can only correctly sample the phase synchronization signal OR' and detect the output LA-LD.

MA-MD is output, and sampling cannot be performed correctly depending on the clock pulse E-H of another phase (the phase of the clock pulse E-H is "1" of the phase synchronization signal OR').
# out of the period), so the detection outputs LE, L
H, MA-MH are not output. Of course, depending on the pulse width and phase of the received phase synchronization signal OR', the detection output LA-LH1MA-MH is generated in other detection conditions, for example, which can only be correctly sampled by the clock pulse CG. do. Also, like the phase synchronization signal CR, a predetermined duty ratio of 50
In this case, all detection outputs LA-LH can be correctly sampled by all of the clock pulses A-H.

MA=MH is generated. Here, each detection output L
A-LH, MA-MH are each sampling clock A to H
The timing of occurrence differs slightly depending on the phase of

Next, the detection outputs LA-LH of these detection circuits 37A-37Hf)h are added to the 8-bit back-end circuit 44, and the detection outputs MA-MH are applied to the 8-bit back-end circuit 44.
Add to 6. Then, the detection output MA-MH is set to negative logic NO.
In addition to the R gate 46, one of the phase synchronization signals OR, CR'
When the first of these detection outputs 'A = MH is generated at the 1st bit, it generates an output N, which is inverted at -47 and delayed slightly, and then output as a latch output. (The latch circuits 44 and 45 are reset in advance by the horizontal synchronizing signal.In this way, in the latch circuit 44, one of the detection outputs LA-LH of the detection circuits 37A to ayH ″
The latch circuit 45 can latch only the one that becomes "1" first among the detection outputs Mp and -MH of the detection circuits 37A to 37H.

That is, in the latch circuit 44, clock pulses A-H
The latch circuit 46 latches which of them can correctly sample the phase synchronization signals CR and CR', and the latch circuit 46 outputs the clock pulse A-
, , H that can correctly sample the phase synchronization signals CR, CR', which one has the earliest phase is latched.

In the operation example shown in FIG. 4, the latch circuit 44 outputs the detection output L.
A, LB, Lc, and LD are latched, and the latch circuit 46 latches the detection output MA.

Therefore, the latch output of this latch circuit 44 is
8, the determination circuit 48 determines which clock pulse is most suitable for sampling the phase synchronized signals CR and CR'. A type of memory addressed by Lp, -LH, and the detection output LA-
Depending on which of the LHs is at the "1" output, select the phase that is located in the center of the clock pulses A-H corresponding to the detection output that is the "1" output. It determines that it is the optimum clock pulse and outputs a 3-bit code signal "abc" indicating it.

However, if there is an even number of "1" outputs, the one with the earlier phase among the two in the center is output. For example, in the case of FIG. 4 mentioned above, the detection output LA-
Out of the clock pulses A to D corresponding to LD, clock pulse B is determined to be the optimal one and the code signal "001" is output.
If the detection output CG is 11", the clock pulse E is determined to be the optimum one and the code 100" is output. Furthermore, the detection output LA-LH
When all are "1" outputs, the switching output X is output regardless of the above code signal.

On the other hand, the latch circuit 46. In addition to the latch output of the discrimination circuit 49, when the detection outputs LA-LH are all "1" outputs, the latch output of is determined to be the optimal one, and outputs a 3-bit code signal "abc" representing it. When all detection outputs LA to LH are 11" outputs, the determination circuit 48 is unable to determine the optimal phase. Since this is not possible, the determination circuit 49 determines the optimum phase using the earliest phase as a reference.

Therefore, the optimal phase discrimination outputs from these discrimination circuits 48 and 49 are respectively applied to the selector 6o, and the switching output I from the discrimination circuit 48 switches and outputs them. That is, when all the detection outputs LA to LH are ``1'' outputs, the discrimination output from the discrimination circuit 49 is switched, and in other cases, the discrimination output from the discrimination circuit 48 is switched and outputted, and the clock pulse selection circuit outputs the discrimination output. 51. In accordance with the discrimination output from the selector 60, the clock pulse selection circuit 61 selects the optimum clock pulse corresponding to the discrimination output from among the eight phase clock pulses A to H, and outputs it to the output terminal 62. .

For example, in the case of FIG. 4 described above, the selector 6o is switched to the discrimination circuit 48 side, and the discrimination circuit/48 code signal "
When the clock pulse B is received according to 'Oo1', the selector 6o is switched to the discrimination circuit 49 side, and the clock pulse E is selected and outputted according to the code signal '100' from the discrimination circuit 49.

Therefore, by using the clock pulse from the output terminal 52 as a sampling clock to sample the digital signal received following the above-mentioned phase synchronization signal, it is possible to accurately receive the digital signal at the most suitable phase.

In this way, in this device, the clock pulse is not divided into stations, but the optimum phase is determined by delaying the oscillation output and detecting the sampling state by each delayed output, thereby reducing the occurrence of interference and using a digital processing circuit. Detection and discrimination can be performed, and useful effects can be obtained that are suitable for IC implementation.

In the above embodiment, eight pits worth of reference phase signals are sampled using each delayed clock pulse, but the number of sampled bits may be increased or decreased as desired.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a synchronization device in an embodiment of the present invention,
FIG. 2 is a waveform diagram of each part. 31... Clock pulse oscillation circuit, 32...
... Oscillation circuit, 33 ... Phase detection circuit, 34
・・・・・・ノ(Tuffa amplifier, 35...delay circuit, 36B~aeH...delay amplifier, 37A
~37H...Detection circuit, 38A...Shift register, 39A...NAND gate, 4
oA...Negative logic NAND gate, 41A, 42
A. 43A...Flip-flop, 44, 45...
... Latch circuit, 46 ... Negative logic NOR gate, 47 ... Inverter, 48.49 ...
...Discrimination circuit, 60-...Selector, 61...
. . . Clock pulse selection circuit, 62 . . . Output terminal.

Claims (1)

[Claims] A clock oscillation circuit that oscillates a clock pulse t having a repetition period of 1/2 of a phase synchronization signal consisting of a repeating signal with a constant period in the binary signal being transmitted, and 1/0 (n is 2
a delay circuit that generates n-phase clock pulses by delaying the clock pulses by an integer equal to or more than n sampling detection circuits that generate an output only when sampling; A discrimination circuit that discriminates a phase suitable for sampling the binary signal, and an output of the discrimination circuit outputs a clock pulse of a predetermined phase from among the n-phase clock pulses for sampling the binary signal. A synchronizing device comprising a switching circuit.