JPS58195336A - Communication system - Google Patents

Communication system

Info

Publication number
JPS58195336A
JPS58195336A JP57078699A JP7869982A JPS58195336A JP S58195336 A JPS58195336 A JP S58195336A JP 57078699 A JP57078699 A JP 57078699A JP 7869982 A JP7869982 A JP 7869982A JP S58195336 A JPS58195336 A JP S58195336A
Authority
JP
Japan
Prior art keywords
signal
digital signal
analog signal
circuit
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57078699A
Other languages
Japanese (ja)
Inventor
Kenji Ogami
大上 健二
Kohei Otake
大竹 孝平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57078699A priority Critical patent/JPS58195336A/en
Publication of JPS58195336A publication Critical patent/JPS58195336A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J99/00Subject matter not provided for in other groups of this subclass

Abstract

PURPOSE:To transmit an input digital signal on the same line at the same time, by adding an amplitude to an input analog signal, multiplying and modulating the result by a digital signal where the maximum value of consecutive zeros is limited, and designating the digital signal as a carrier. CONSTITUTION:The input analog signal 20 is added with a prescribed amplitude generated at a DC generating circuit 22 from an addition circuit 23. The input digital signal 21 is converted into a binary digital code series where the maximum value of consecutive zeros is limited to a prescribed value at a code conversion circuit 24, multiplied and modulated at a multiplication circuit 25 by the said analog signal and transmitted to a transmission line 26. A reception signal is line-equalized at a line equalizer 27 and an output signal 33 is obtained at an analog signal extracting circuit 28. The ditital signal is shaped at a waveform equalizer 29 and discriminated at a discrimination circuit 30 by using the timing wave of a timing extraction circuit 31. This signal series is inverted for the code conversion at the transmission side with a code conversion circuit 32 and an output signal 34 is obtained.

Description

【発明の詳細な説明】 発明の技術分野 本発明鉱アナログ信号とディジタル信号を同一線路で同
時に伝送する通信方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a communication system for simultaneously transmitting analog signals and digital signals over the same line.

技術の背景 第1図は、アナログ信号とディジタル信号を同一線路で
同時に伝送する代表的な通信方式の構成図でおる。(た
とえは梶原、笹用:[データオーバボイス加入者線伝送
方式の一検討」昭和57年度電子通信学、会総合全国大
会、N111738)送信側において、入力ディジタル
信号2は直流分抑圧符号変換回路5によシ直流分抑圧の
ための符号変換を行う九彼、入力アナログ信号1と分波
器4で周波数分割多重され伝送線路5に送出される。受
信側では、等化量6で線路等化を行い分波器7でアナロ
グ信号とディジタル信号を周波数分離し出力アナログ信
号12を得る。一方デイジタル信号は波形尋化量8で波
形整形され、波形整形されたパルス列からタイミング抽
出回路11によシタイミング信号を生成する。波形整形
され九パルスはタイミング信号を用いて識別器9により
識別される。
Background of the Technology FIG. 1 is a block diagram of a typical communication system that simultaneously transmits analog signals and digital signals on the same line. (For example, Kajiwara, Sasayo: [A Study of Data Over Voice Subscriber Line Transmission System] 1985 National Conference of Electronics and Communication Studies, N111738) On the transmitting side, the input digital signal 2 is passed through a DC component suppression code conversion circuit. The input analog signal 1 is frequency-division multiplexed by the demultiplexer 4 and sent to the transmission line 5. On the receiving side, line equalization is performed using an equalization amount of 6, and a branching filter 7 separates the frequency of the analog signal and the digital signal to obtain an output analog signal 12. On the other hand, the digital signal is waveform-shaped by a waveform modification amount of 8, and a timing signal is generated by a timing extraction circuit 11 from the waveform-shaped pulse train. The nine waveform-shaped pulses are identified by a discriminator 9 using a timing signal.

識別され再生された信号系列を符号変換回路10により
直流分抑圧のための符号変換の逆変換を行い出力ディジ
タル信号13を得る。
The identified and reproduced signal sequence is subjected to an inverse code conversion for DC component suppression by a code conversion circuit 10 to obtain an output digital signal 13.

第2図は第1図で示した周波数分側条1方式のアナログ
信号およびディジタル信号の使用周波数帯域をあられし
たものでおる。Sa及びSdは線路等化ムロの出力端子
におけるアナログ信号及びディジタル信号の電力スペク
トラム特性、ygpFdtiそれぞれアナログ信号帯域
及びディジタル信号帯域でおる。
FIG. 2 shows the frequency bands used for analog signals and digital signals of the frequency division side strip 1 method shown in FIG. 1. Sa and Sd are the power spectrum characteristics of the analog signal and digital signal at the output terminal of the line equalization unevenness, and ygpFdti are the analog signal band and digital signal band, respectively.

従来技術と問題点 上に述べたように従来のむの種通信方式においではアナ
ログ信号をディジタ、ル信号のクロック周波数の10〜
20Ls程度の低域J1!l、技数帯域に挿入する、D
−、、、J、l□、5、ヶbtu、’、誓ヮ、。□、イ
ジタル波形伝送において祉、送ffi側で直流分抑圧の
ための符号変換を行ったとしても低域遮断による波形歪
が大きくなる欠点がおった。一方低域遮断による波形歪
の影響を小さくするためにディジタル信号のクロック周
波数を大きくすると雑音量が増大しSN比が著しく劣化
する。またアナログ信号の品質を保証するために祉、周
波数多重分離を行う分波器に祉安定でかつ高精度な特性
が要求される。さらに、受信装置はアナログ信号とディ
ジタル信号を分離し良状態で等化量を調整する必要があ
る丸めその調整が複雑となる欠点があった。
Prior Art and Problems As mentioned above, in the conventional communication system, analog signals are converted into digital signals, and the clock frequency is 10 to 10 times higher than that of digital signals.
Low range J1 of about 20Ls! l, insert into skill band, D
-,,,J,l□,5,gabtu,',swear,. □In digital waveform transmission, even if code conversion is performed to suppress the DC component on the sending ffi side, there is a drawback that waveform distortion due to low frequency cutoff becomes large. On the other hand, if the clock frequency of the digital signal is increased in order to reduce the influence of waveform distortion due to low-frequency cutoff, the amount of noise increases and the S/N ratio deteriorates significantly. Furthermore, in order to guarantee the quality of analog signals, a duplexer that performs frequency multiplexing and demultiplexing is required to have stable and highly accurate characteristics. Furthermore, the receiving apparatus has the disadvantage that rounding requires separating the analog signal and digital signal and adjusting the equalization amount under good conditions, making the adjustment complicated.

発明の目的 本発明はこれらの欠点を除去するために、入力アナログ
信号に一定の振幅値を加算し、零連続の最大値を一定に
制限し九2値ディジタル信号系列で乗算変調し、2値デ
ィジタル信号系列をアナログ係号の搬送波として使用す
ることによシアナロ;、 グ信号とディジタル信号を同一の線路で同時に伝1、′
Purpose of the Invention In order to eliminate these drawbacks, the present invention adds a constant amplitude value to an input analog signal, limits the maximum value of consecutive zeros to a constant value, performs multiplication modulation with a 92-level digital signal sequence, and generates a binary signal. By using a digital signal sequence as a carrier wave for analog coding, a cyanaloid signal and a digital signal can be transmitted simultaneously on the same line.
.

送できるように毛たもので以下図面について本発明の詳
細な説明1″′:′1″る。
A detailed description of the invention is provided below with reference to the drawings.

11 発明の実施例 第6図は本発明の一実施例の通信方式構成図で  1あ
る。入力アナログ信号20(j(t))は加算回路23
によシ直流発生回路22で発生した一定振幅値A0を加
算される。一方入カディジタル信号21は符号変換回路
24によシ零連続の最大値を一定に制限した2社ディジ
タル符号系列に変換され、前記一定の振幅値為を加算さ
れたアナログ信号と乗算回路25により乗算変調され伝
送線路26に送出される。(なお符号変換回路24およ
び後述する受@側の符号変換回路32は、九とえば加藤
、中用、伊藤:「高速ディジタル光伝送方式の伝送路符
号栴成について」電子通信学会論文誌、 1981年1
2月Va1.164−E、 Na、12. p、146
9/1470 )受信信号は線路等化量27で線路醇化
され、アナログ信号抽出回路28(たとえばS、スタイ
ン。
11 Embodiment of the Invention FIG. 6 is a block diagram of a communication system according to an embodiment of the present invention. The input analog signal 20 (j(t)) is sent to the adder circuit 23
A constant amplitude value A0 generated by the DC generating circuit 22 is added to the constant amplitude value A0. On the other hand, the input digital signal 21 is converted by the code conversion circuit 24 into a two-company digital code sequence in which the maximum value of consecutive zeros is limited to a certain value, and is then converted to an analog signal with the above-mentioned constant amplitude value added by the multiplication circuit 25. The signal is multiplied and modulated and sent to the transmission line 26. (The code conversion circuit 24 and the code conversion circuit 32 on the receiving side, which will be described later, are connected to nine, for example, Kato, Nakayo, Ito: "On Transmission Line Code Formation of High-Speed Digital Optical Transmission System," Transactions of the Institute of Electronics and Communication Engineers, 1981. Year 1
February Va1.164-E, Na, 12. p, 146
9/1470) The received signal is line-equalized by a line equalization amount 27, and the analog signal extraction circuit 28 (for example, S, Stein.

J、J、ジョーンズ共著、関英男完訳:現代の通信目線
理論;190〜194頁、森北出版、昭和45年10月
)によりアナログ信号を抽出し出力アナログ信号55を
得る。一方デイジタル信号は、妓形咎化量29によ多波
形整形されタイミング抽出回路51により生成された夕
・1はング波を用いて識別回路50によりm別され、再
生される。仁のディジタル信号系列に、零連続の最大値
を制限する符号変換の逆変換を行う符号変換回路52に
よ〕送信稠で行つ九零連続の最大値を保証する符号変換
の逆変換を行い、出力ディジタル信号34を得る。なお
第6図で35.36.37.38,39.40はそれぞ
れ出力端子である。
(Co-authored by J. J. Jones, complete translation by Hideo Seki: Modern Communication Perspective Theory; pp. 190-194, Morikita Publishing, October 1970), the analog signal is extracted and an output analog signal 55 is obtained. On the other hand, the digital signal is subjected to multi-waveform shaping according to the amount of distortion 29, and is divided into m groups by the identification circuit 50 using the evening and first wave waves generated by the timing extraction circuit 51 and reproduced. A code conversion circuit 52 performs an inverse code conversion of the code conversion that limits the maximum value of consecutive zeros on the digital signal sequence of 900. , an output digital signal 34 is obtained. In FIG. 6, 35, 36, 37, 38, and 39.40 are output terminals, respectively.

第4図(娼(6)、(6)、(力及び(#)は第6図に
示す本発明の通信方式の各出力端子における動作波形を
示した4のである。第4図−)祉出力端子35ての入力
アナログ信号A(t)に一定振幅値A、が加算されたア
ナログ信号波形j(t)+j、であル、第4図(6)は
出力路子56での零連続の最大値が一定に制限された2
値ディジタル信号波形である。第4図((+)は出力端
子57での第4図(−のアナログ信号波形を第4図(6
)の2値ディジタル信号波形で乗算変調した波形である
。第4図−は出力端子58での受信側で抽出されたアナ
ログ信号波形である。第・4図(−)は出力端子69で
の受信側の識別再生され九2値ディジタル信号波形であ
る。
Figure 4 (6), (6), (power and #) indicate the operating waveforms at each output terminal of the communication system of the present invention shown in Figure 6.Figure 4-) The analog signal waveform j(t)+j is obtained by adding a constant amplitude value A to the input analog signal A(t) at the output terminal 35. FIG. Maximum value is limited to a certain value 2
Value digital signal waveform. Figure 4 ((+) is the analog signal waveform of Figure 4 (-) at the output terminal 57.
) is a waveform obtained by multiplying and modulating the binary digital signal waveform. FIG. 4 shows the analog signal waveform extracted on the receiving side at the output terminal 58. FIG. 4 (-) shows the waveform of the 92-value digital signal which is identified and reproduced on the receiving side at the output terminal 69.

このように入力アナログ信号Act)に一定の振幅値A
0を加算し、2値ディジタル信号系列で乗j!変調して
いるので人力アナログ信号Act>が零の場合でも2値
ディジタルtF1gが−1”のとき、そのパルス振幅値
をAoとして確保できるので、2値ディジタル伯号を伝
送する仁とができる。またアナログ信号の搬送波として
用いられる2値ディジタル信号系列U零連続の最大値N
が保証されているので、2値ディジタル信号系列には、
そのクロック網期を10秒とすると少なくとも(N+1
)T0秒周期以内に必ず′1”が存在する。したがって
サンプリング定理によシ少なくとも /、、 = 1/ l 2 (jV+ 1 ) T61
 CHx)の周波数帯域を有するアナログ信号を伝送す
ることができる。
In this way, a constant amplitude value A is applied to the input analog signal Act).
Add 0 and multiply by a binary digital signal sequence j! Since it is modulated, even when the human input analog signal Act> is zero, when the binary digital signal tF1g is -1'', the pulse amplitude value can be secured as Ao, so it is possible to transmit the binary digital signal. Also, the maximum value N of a binary digital signal sequence U of consecutive zeros used as a carrier wave of an analog signal.
is guaranteed, so for a binary digital signal sequence,
If the clock network period is 10 seconds, at least (N+1
) There is always '1' within the period of T0 seconds. Therefore, according to the sampling theorem, at least /,, = 1/ l 2 (jV+ 1 ) T61
It is possible to transmit an analog signal having a frequency band of CHx).

第5図は第6図の線路醇化−:出力端子40での等化波
形のアイダイアゲラムチY=例を示したものである。ア
イダイアグラムの  および下部にアナログ信号(p、
α)とディジタル信号(2値)がそれぞれわられされる
。し九がって、仁のアイダイアグラムを観測しながら線
路尋化二27の特性を級整することによシ、アナログ信
号系列とディジタル信号系列の等化波形を同時に最適に
調整することができる。
FIG. 5 shows an example of the equalized waveform at the output terminal 40 shown in FIG. The analog signals (p,
α) and a digital signal (binary) are respectively divided. Therefore, by grading the characteristics of the line width conversion while observing the eye diagram, it is possible to optimally adjust the equalization waveforms of the analog signal series and digital signal series at the same time. .

また、ディジタル信号系列は零連続の最大値が保証され
ているのでタイiング波の消失を防止できる。したがっ
て入力ディジタル信号になんら制約を課さない伝送路の
BSI (Bit Saqma*eg I*dapa亀
−devhea )  化が可能となる。
Further, since the digital signal sequence is guaranteed to have a maximum value of consecutive zeros, it is possible to prevent the timing wave from disappearing. Therefore, it becomes possible to convert the transmission path to BSI (Bit Saqma*eg I*dapa turtle-devhea) without imposing any restrictions on the input digital signal.

第6図で示した片方向伝送のほかに、両端局で交互に時
分割的に本発明の符号構成信号を伝送することによシ、
同一の伝送線路でアナログ信号とディジタル信号を双方
向伝送することができる。
In addition to the unidirectional transmission shown in FIG.
Analog and digital signals can be transmitted bidirectionally on the same transmission line.

発明の詳細 な説明したように、本発明の通信方式はディジタル信号
をアナログ信号の搬送波として用いており、従来。。−
一8割側条Eカよ。ようよ、ア。
DETAILED DESCRIPTION OF THE INVENTION As described above, the communication system of the present invention uses a digital signal as a carrier wave for an analog signal, which is different from the conventional method. . −
180% side stripe Eka. Hey there, a.

器を用い九周波数盆離多重や直流分抑圧を行う必要がな
いので、波形劣化が小さく、装置の調整が   1簡単
でibかつ高能率にアナログ信号とディジタル信号を同
時に伝送できる利点を有しその効果大である。
Since there is no need to perform nine-frequency multiplexing or DC component suppression using a device, it has the advantage that waveform deterioration is small, equipment adjustment is easy, and analog and digital signals can be transmitted simultaneously with high efficiency. It is highly effective.

【図面の簡単な説明】 第1図及び第2図は従来の周波数分割多重によるアナロ
グ信号とディジタル信号同時伝送方式の構成図及び使用
周波数帯域、第3図及び第4図(−乃至(e) Id本
発明による通信方式の一実施例の構成図とその動作波形
、第5図は本発明の等化波形のアイダイアグラムである
。 1.20・・・入力アナログ信号、2.21−・・入力
ディジタル信号、6・・・直流分抑圧符号変換回路、4
,7・・・分波器、5,26・・・伝送線路、6.27
−・・線路等化器、8.29・・・波形等化器、9.5
0−・・識別回路、10・・・直流分抑圧逆符号変換回
路、11.31・・・タイミング抽出回路、12.55
・・・出力アナログ信号、13.34・・・出力ディジ
タル信号、22−・・直流発生回路、2S・・・加算回
路、24・・・零連続の最大値を制限する符号変換回路
、25・・・乗算回路、28・・・アナログ信号抽出回
路、 32・・・零連続の最大値を制限する符号変換の
逆変換を行う符号変換回路、55,36,37,58.
.59,40・・・出力端子、Fα・・・アナログ信号
帯域、Ft−・・ディジタル信号帯域、Sm、5ト=線
路等化器6の出力端子におけるアナログ信号及びディジ
タル信号の電力スペクトラム。 特許出願人  日本電信電話公社 代理人 弁理士 玉蟲久五部 (外6名)第20 第50 第4図 n
[Brief Description of the Drawings] Figures 1 and 2 are block diagrams and used frequency bands of a conventional simultaneous transmission system for analog and digital signals using frequency division multiplexing, and Figures 3 and 4 (- to (e) Id A block diagram of an embodiment of the communication system according to the present invention and its operating waveforms. Fig. 5 is an eye diagram of the equalized waveform according to the present invention. 1.20...Input analog signal, 2.21-... Input digital signal, 6... DC component suppression code conversion circuit, 4
, 7... Duplexer, 5, 26... Transmission line, 6.27
--- Line equalizer, 8.29 --- Waveform equalizer, 9.5
0--identification circuit, 10--DC component suppression inverse code conversion circuit, 11.31--timing extraction circuit, 12.55
. . . Output analog signal, 13. 34 . . . . Multiplication circuit, 28 .
.. 59, 40...output terminal, Fα...analog signal band, Ft-...digital signal band, Sm, 5t=power spectrum of the analog signal and digital signal at the output terminal of the line equalizer 6. Patent applicant Nippon Telegraph and Telephone Public Corporation agent Patent attorney Gobe Tamamushi (6 others) No. 20 No. 50 Figure 4 n

Claims (1)

【特許請求の範囲】[Claims] アナログ信号とディジタル信号の2人力伯号を伝送する
通信方式において、送信側では入力アナログ信号に一定
の振幅値を加算し、一方入力デイジタル信号を最大塔連
続数を一定に制限したディジタル信号系列に変換し、前
記一定の振幅値を加算したアナログ信号を前記零連続の
最大値を一定に制限したディジタル信号に1乗算変調し
て伝送し、受信側では受信した信号を等化し、該等化波
形を振幅軸方向でアナログ信号とディジタル信号とに分
離し、該分離したアナログ信号を前記入力アナログ信号
に復元し、該分離したディジタル信号を識別して前記零
連続の最大値を一定に制限する符号変換の逆変換を行い
前記入カデイジタル恰号に昏元することを特徴とする通
信方式。
In a communication system that transmits two signals, an analog signal and a digital signal, the transmitting side adds a certain amplitude value to the input analog signal, while converting the input digital signal into a digital signal series with a limited maximum number of consecutive signals. The analog signal obtained by adding the constant amplitude value is multiplied by 1 and modulated into the digital signal in which the maximum value of consecutive zeros is limited to a constant value, and then transmitted.The receiving side equalizes the received signal and creates the equalized waveform. a code that separates the signal into an analog signal and a digital signal in the amplitude axis direction, restores the separated analog signal to the input analog signal, identifies the separated digital signal, and limits the maximum value of the series of zeros to a constant value. A communication method characterized by performing an inverse transformation of the conversion and converting it to the input digital code.
JP57078699A 1982-05-11 1982-05-11 Communication system Pending JPS58195336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57078699A JPS58195336A (en) 1982-05-11 1982-05-11 Communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57078699A JPS58195336A (en) 1982-05-11 1982-05-11 Communication system

Publications (1)

Publication Number Publication Date
JPS58195336A true JPS58195336A (en) 1983-11-14

Family

ID=13669112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57078699A Pending JPS58195336A (en) 1982-05-11 1982-05-11 Communication system

Country Status (1)

Country Link
JP (1) JPS58195336A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170827A (en) * 1984-09-14 1986-04-11 Yamatake Honeywell Co Ltd Communication method
JP2012060283A (en) * 2010-09-07 2012-03-22 Miura Co Ltd Signal multiplexing method and signal multiplexing circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170827A (en) * 1984-09-14 1986-04-11 Yamatake Honeywell Co Ltd Communication method
JPH0467817B2 (en) * 1984-09-14 1992-10-29 Yamatake Honeywell Co Ltd
JP2012060283A (en) * 2010-09-07 2012-03-22 Miura Co Ltd Signal multiplexing method and signal multiplexing circuit

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