JPS58191453A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58191453A JPS58191453A JP57074868A JP7486882A JPS58191453A JP S58191453 A JPS58191453 A JP S58191453A JP 57074868 A JP57074868 A JP 57074868A JP 7486882 A JP7486882 A JP 7486882A JP S58191453 A JPS58191453 A JP S58191453A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- metal electrode
- width
- electrode part
- case
- Prior art date
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- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は配線インダクタンス成分を有する半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a wiring inductance component.
高い周波数で用いられる半導体装置は、装置自体のもつ
接合容量、IE列低抵抗インダクタンス。Semiconductor devices used at high frequencies have their own junction capacitance and IE string low resistance inductance.
浮遊容量、寄生抵抗、ケース容量などをできるだけ低減
する必要があり、その大めに種々の万策がとられている
。この中でと〈Kインダクタンスは、サブストレート層
上に動作層および動作層上面の金属電極部を有するペレ
ットの金属電極部と、金属部および絶縁体部で構成され
るケースとの電気的接触をとる目的のために用いられる
金属線あるいは金属テープ等の配線部によって主として
決定される。第1図は、従来型半導体装置の横断面図を
示したもので、サブストレート層1上に動作層2と動作
112上面の金属電極部3とを有するペレットと、金属
部4と絶縁体部5(ただし、絶縁体部5の金属部4との
接触面およびその反対面は通常。It is necessary to reduce stray capacitance, parasitic resistance, case capacitance, etc. as much as possible, and various measures are being taken to achieve this. Among these, the <K inductance is the electrical contact between the metal electrode part of the pellet, which has an active layer on the substrate layer and a metal electrode part on the top surface of the active layer, and the case consisting of the metal part and the insulator part. It is mainly determined by the wiring part, such as metal wire or metal tape, used for the purpose. FIG. 1 shows a cross-sectional view of a conventional semiconductor device, showing a pellet having an active layer 2 on a substrate layer 1 and a metal electrode part 3 on the top surface of an active part 112, a metal part 4 and an insulator part. 5 (However, the contact surface of the insulator portion 5 with the metal portion 4 and the opposite surface thereof are normal.
金属膜が蒸着等により形成されている)からなるケース
との1気的接触をとるため、金属電極部3と絶縁体部5
上面に、均−太さ金属線または、均−幅金礪テープ6が
融着されている。第2図に、その上面図を示したもので
、金属電極部3と絶縁体部5上面との電気的接触をとる
ためにそれらの部分に融着されるのは、均−太さの金属
線かまえは均一幅の金部テープ6であった。半導体装置
のインダクタンスを低減して高周波特性を上げるために
は、均−太さ1属線かオ九は均−一一属テープ6の太さ
や幅、長さ、厚さをそれぞれ、太く。A metal electrode part 3 and an insulator part 5 are connected to each other in order to make contact with the case (on which a metal film is formed by vapor deposition, etc.).
A metal wire of uniform thickness or a metal tape 6 of uniform width is fused to the upper surface. FIG. 2 shows a top view of the metal electrode part 3 and the top surface of the insulator part 5. In order to make electrical contact between the metal electrode part 3 and the upper surface of the insulator part 5, a metal of uniform thickness is fused to these parts. The wire frame was a metal tape 6 of uniform width. In order to reduce the inductance of the semiconductor device and improve the high frequency characteristics, the thickness, width, length, and thickness of the uniform wire tape 6 must be increased.
広く、短く、厚くする必要がある。しかしながら高い周
波数での使用が要求される半導体素子においては、接合
容量低減の九め金属電極部3の面積が非常に小さく、シ
九がって金属電極部3に融着される均−太さ金属線ある
いは均一幅金属テープ6も、融着時の均−太さ金属線あ
るいは均一幅金属テープ6のつぶれ幅が広くなり、金属
電極部3の外側にはみ出してし壇う、仁のためはみ出し
部とサブストレート層1間の寄生容量の増加や、周辺部
サブストレート層lとの接触を避けるためにどうしても
太さを細くしたり幅を狭くしたりしなければならなかっ
た。第3図は、インダクタンスを低減するために全体に
わたって太さや幅を太くあるいけ広くしたために1金属
電極部3に融着された均−太さ金属線あるいは均一幅金
属テープ6の融着部分が融着時のつぶれKより、金属電
極部3の外側にはみだした様子を示す横断面図で、第4
図はその上面図を示している。It needs to be wide, short, and thick. However, in semiconductor devices that are required to be used at high frequencies, the area of the metal electrode part 3 that reduces junction capacitance is very small, and the area of the metal electrode part 3 that is fused to the metal electrode part 3 is very small. The metal wire or uniform-width metal tape 6 may also be flattened during fusion, causing the width of the uniform-thickness metal wire or uniform-width metal tape 6 to widen and protrude to the outside of the metal electrode portion 3. In order to avoid an increase in the parasitic capacitance between the substrate layer 1 and the substrate layer 1, and to avoid contact with the peripheral substrate layer 1, it was necessary to make the thickness and width narrower. FIG. 3 shows that the fused portion of the uniform-thickness metal wire or uniform-width metal tape 6 is fused to the metal electrode portion 3 because the thickness and width are made thicker and wider over the whole to reduce inductance. This is a cross-sectional view showing how the metal electrode part 3 protrudes from the crushing K during fusion.
The figure shows its top view.
以上のように高い周波数で従来型半導体素子を用いる場
合、接合容量を小さくするため金属電極部30面積が小
さくなり、そこに融着される均−太さ金属線あるいは、
均一幅金属テープ6の融着時のつぶれが、金属電極部3
からはみ出さないようにするため%均−太さ金属線ある
いは、均一幅金属テープ6の太さや幅を細くしたり狭く
し走りしなければならず、インダクタンス低減のため均
−太さ金属線あるいは均一幅金属テープ6の太さや幅を
太くしたり一広くしたりしたいという要求を満足するこ
とができないばかりか%均−太さ金属線あるいは均一幅
金属テープ6の太さや幅を細くしたり狭くしたりすると
とKより、逆にインダクタンスを増加させる結果となり
、半導体素子における高周波特性の著しい劣化を招いて
いた。When using a conventional semiconductor element at a high frequency as described above, the area of the metal electrode part 30 becomes small in order to reduce the junction capacitance, and the area of the metal electrode part 30 becomes small, and the metal wire of uniform thickness or
The flattening of the uniform width metal tape 6 during welding causes the metal electrode portion 3 to
In order to prevent it from protruding from the % uniform thickness metal wire or uniform width metal tape 6, it is necessary to make the thickness and width of the uniform thickness metal wire thinner or narrower. Not only is it not possible to satisfy the demand for thickening or widening the thickness or width of the uniform width metal tape 6, but it is also impossible to make the thickness or width of the uniform width metal wire or the uniform width metal tape 6 thinner or narrower. If this happens, the inductance will be increased more than K, resulting in significant deterioration of the high frequency characteristics of the semiconductor device.
本発明は浮遊容量を増加させることなくインダクタンス
の低減がはかれる半導体装置を提供することを目的とす
る。An object of the present invention is to provide a semiconductor device in which inductance can be reduced without increasing stray capacitance.
−第5図は、説明のた
めケースの絶縁体部5の一部を省略した本発明によるイ
ンダクタンス低減半導体装置の一実施例による概略図を
示したもので、サブストレート層1と動作層および動作
層上面の金属電極部3からなるペレットと金属部4およ
び絶縁体部5からなるケースに、電気的接触をと石ため
金属テープ7が金属電極部3およびケースの絶縁体部5
上面に融着されている。高い周波数で用いられる半導体
素子IIcおいては、金属電極部50面積は非常に小さ
いため、そこに融着される金属テープ70幅も融着時の
金属テープ70つぶれが金属電極部3の外にはみ出し、
このはみ出し部分とサブストレート層1との間の浮遊容
量が増加した9、はみ出し部分とサブストレート層1と
が接融するのを避けるために狭くしなければならないと
いう要求と、インダクタンスを低減させるという要求と
の両方會−挙に満足する構造となっている。すなわち、
金属テープ70幅が全体にわたって均一ではなく、ペレ
ットの金属電極部3周辺では金属テープの幅が狭く、そ
れ以外のところでは幅がテーノ(状に広くなっている。- FIG. 5 is a schematic diagram showing an embodiment of the inductance reducing semiconductor device according to the present invention, with a part of the insulator section 5 of the case omitted for explanation, and shows a substrate layer 1, an operating layer and an operating layer. A metal tape 7 is placed between the pellet consisting of the metal electrode section 3 on the upper surface of the layer and the case consisting of the metal section 4 and the insulator section 5 for electrical contact.
It is fused to the top. In the semiconductor device IIc used at high frequencies, the area of the metal electrode part 50 is very small, so the width of the metal tape 70 fused thereto is such that the crushing of the metal tape 70 at the time of fusion is outside the metal electrode part 3. protruding,
The stray capacitance between this protruding part and the substrate layer 1 has increased9, there is a need to narrow the protruding part and the substrate layer 1 to avoid welding, and there is a need to reduce inductance. It has a structure that satisfies both requirements and events. That is,
The width of the metal tape 70 is not uniform over the entire area; the width of the metal tape is narrow around the metal electrode portion 3 of the pellet, and the width is wide in other areas.
このように、金属テープ70幅を金属電極部3に融着さ
れる部分で狭くすることにより、融着時の金属テープ7
0つぶれ部分が金属電極部3外部へはみ出すことがなく
なV%はみ出し部分とサブストレート層1間による浮遊
容量の増加や、はみ出し部分とサブストレート層1との
接触の問題も解消されるとと4に、金属電極部3補辺以
外の部分の金属テープ70幅が広くなっている丸め、金
属電極部30面積が小さくなっても従来型半導体素子に
おけるようなインダクタンスの増加がなく、逆にインダ
クタンスの大きな低減がはかれることkなる。このよう
力構造の金属テープ7を用いた本発明による半導体素子
の高周波特性は、従来型半導体素子に比べ格段にすぐれ
ており、加えて金属テープ70幅を金属電極部3に融着
される部分は融着時のつぶれ部分が金属電極部3からは
み出さない種度に一定幅にしておき、それ以外の部分の
金属テープ70幅を変えるととkよりインダクタンスの
値を自由に変える事が出来るため、ペレットやケースを
変えることなく金属テープ7の幅を適mK選ぶことによ
って、すたわち、金属テープ7によって決まるインダク
タンス分のみを変化させることにより、半導体素子の高
周波特性(たとえば、共振周波数など)を使用目的によ
り自由に調整することができるという利点を有する。第
6図Fi、ケースの絶縁体部5の一部を省略した第5図
の上面図で、絶縁体部5の一部を省略することなく示し
たものである。In this way, by narrowing the width of the metal tape 70 at the portion to be fused to the metal electrode part 3, the width of the metal tape 70 is reduced during fusion.
Since the collapsed portion does not protrude to the outside of the metal electrode portion 3, the increase in stray capacitance between the V% protruding portion and the substrate layer 1, and the problem of contact between the protruding portion and the substrate layer 1 are eliminated. 4, the width of the metal tape 70 in the part other than the complementary side of the metal electrode part 3 is rounded, and even if the area of the metal electrode part 30 becomes smaller, there is no increase in inductance as in conventional semiconductor devices; This will result in a significant reduction in The high frequency characteristics of the semiconductor device according to the present invention using the metal tape 7 having such a force structure are far superior to those of conventional semiconductor devices. The inductance value can be freely changed by keeping the width constant so that the crushed part during fusion does not protrude from the metal electrode part 3, and changing the width of the metal tape 70 in other parts. Therefore, by selecting an appropriate width of the metal tape 7 (mK) without changing the pellet or case, in other words, by changing only the inductance determined by the metal tape 7, the high frequency characteristics of the semiconductor element (for example, the resonant frequency) can be improved. etc.) can be freely adjusted according to the purpose of use. FIG. 6 Fi is a top view of FIG. 5 with a part of the insulator section 5 of the case omitted, and is shown without omitting a part of the insulator section 5;
第7乃至9図はいづれも、本発明の他の実施例で、第7
および8図においては、サブストレート層1と動作層お
よび金属電極部3からなるペレットの金属電極部3と、
金属部4および絶縁体部5からなるケースの絶縁体部5
上面部分に融着される金属テープあるいは金属線70幅
あるいは太さが、金属電極部3周辺では融着時のつぶれ
Kより金属電極部3からはみ出すのを防ぐために狭くあ
るいけ細くされており、その以外の部分においては、イ
ンダクタンスを低減しなおかつ適当なインダクタンス量
をもたす良め金属テープあるいは金属線7の幅や太さを
段階的に広くしたり、太くしたりした半導体装置の上面
図を示したものである。7 to 9 each show other embodiments of the present invention;
In FIG. 8, a metal electrode part 3 of a pellet consisting of a substrate layer 1, an active layer, and a metal electrode part 3,
Insulator part 5 of the case consisting of metal part 4 and insulator part 5
The width or thickness of the metal tape or metal wire 70 to be fused to the upper surface portion is made narrower around the metal electrode portion 3 in order to prevent it from protruding from the metal electrode portion 3 due to the crushing K during fusion. In other parts, the top view of the semiconductor device is shown in which the width and thickness of the metal tape or metal wire 7 is gradually widened or thickened to reduce the inductance and still have an appropriate amount of inductance. This is what is shown.
第9図はケース容量を低減するためケースの絶縁体部5
を小さくした半導体装置に対して、サブストレート層l
と動作層および金属電極部3とを有するペレットの金属
電極部3周辺では幅が狭く。Figure 9 shows the insulator section 5 of the case to reduce the case capacitance.
For a semiconductor device with a smaller substrate layer l
The width is narrow around the metal electrode part 3 of the pellet having the active layer and the metal electrode part 3.
その他の部分の幅は広い金属テープ7を用いた例の概略
図を示したものである。This is a schematic diagram of an example in which a metal tape 7 having a wider width in other parts is used.
第1図は従来型半導体装置の横断面図、第2図はその上
面図、第3図はペレットの金属電極部に融着され九均−
幅金属テープもしくけ均−太さ金属線が、融着時につぶ
れて、つぶれた部分が金属電極部よりはみ出した従来型
半導体装置の横断面図、第4図はその上面図であゐ、第
5図は本発明の一実施例による半導体装置の概略図で−
便宜上ケースの絶縁体部の一部を省略しである。第6図
は、ケースの絶縁体部を省略すること表〈示した第5図
の半導体装置の上面図である。第7および第8図Fiい
づれ4本発明の他の実施例で夫々半導体装置の上面図を
示し、第9図は本発明の更に他の実施例で半導体装置の
概略図を示しである。
1・・・・・・低抵抗半導体基板(サブストレート層)
2・・・・・・動作層、3・・・・・・金属電極部、4
・・・・・・ケースの金属部、5・・・・・・ケースの
絶縁体部(金属部4と接触する面と反対面は金属膜が形
成されている)、6・・・・・・均一幅金属テープ賜し
くは均−太さ金属線17・・・・・・金属テープもしく
は金属線。Fig. 1 is a cross-sectional view of a conventional semiconductor device, Fig. 2 is a top view thereof, and Fig. 3 is a nine-dimensional structure fused to the metal electrode part of the pellet.
Figure 4 is a cross-sectional view of a conventional semiconductor device in which a width metal tape and a uniform-thickness metal wire are crushed during fusion, and the crushed portion protrudes from the metal electrode part. FIG. 5 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.
For convenience, a part of the insulator part of the case is omitted. FIG. 6 is a top view of the semiconductor device of FIG. 5 in which the insulator portion of the case is omitted. 7 and 8 each show a top view of a semiconductor device according to another embodiment of the present invention, and FIG. 9 shows a schematic diagram of a semiconductor device according to still another embodiment of the present invention. 1...Low resistance semiconductor substrate (substrate layer)
2... Operating layer, 3... Metal electrode part, 4
...Metal part of the case, 5...Insulator part of the case (a metal film is formed on the surface opposite to the surface in contact with the metal part 4), 6... - Uniform width metal tape or uniform thickness metal wire 17...Metal tape or metal wire.
Claims (1)
なる半導体装置において、ペレットの動作層上面の金属
電極部とケースとの電気的接触をとるための金属線ある
いは金属テープの太さ奄しくは幅を前記ケースに近づく
につれて太くもしくは広くしたことを特徴とする半導体
装置。In a semiconductor device consisting of a semiconductor pellet and a case in which a solid pellet is mounted, the thickness or width of the metal wire or metal tape for making electrical contact between the metal electrode part on the upper surface of the active layer of the pellet and the case is determined. A semiconductor device characterized in that the semiconductor device becomes thicker or wider as it approaches the case.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57074868A JPS58191453A (en) | 1982-05-04 | 1982-05-04 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57074868A JPS58191453A (en) | 1982-05-04 | 1982-05-04 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58191453A true JPS58191453A (en) | 1983-11-08 |
Family
ID=13559735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57074868A Pending JPS58191453A (en) | 1982-05-04 | 1982-05-04 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58191453A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6376913B1 (en) * | 1998-08-13 | 2002-04-23 | Siemens Aktiengesellschaft | Integrated semiconductor chip having leads to one or more external terminals |
US6713374B2 (en) | 1999-07-30 | 2004-03-30 | Formfactor, Inc. | Interconnect assemblies and methods |
US6727580B1 (en) | 1993-11-16 | 2004-04-27 | Formfactor, Inc. | Microelectronic spring contact elements |
US6780001B2 (en) | 1999-07-30 | 2004-08-24 | Formfactor, Inc. | Forming tool for forming a contoured microelectronic spring mold |
US6888362B2 (en) | 2000-11-09 | 2005-05-03 | Formfactor, Inc. | Test head assembly for electronic components with plurality of contoured microelectronic spring contacts |
US6939474B2 (en) | 1999-07-30 | 2005-09-06 | Formfactor, Inc. | Method for forming microelectronic spring structures on a substrate |
US7189077B1 (en) | 1999-07-30 | 2007-03-13 | Formfactor, Inc. | Lithographic type microelectronic spring structures with improved contours |
US7435108B1 (en) | 1999-07-30 | 2008-10-14 | Formfactor, Inc. | Variable width resilient conductive contact structures |
US7579269B2 (en) | 1993-11-16 | 2009-08-25 | Formfactor, Inc. | Microelectronic spring contact elements |
-
1982
- 1982-05-04 JP JP57074868A patent/JPS58191453A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6727580B1 (en) | 1993-11-16 | 2004-04-27 | Formfactor, Inc. | Microelectronic spring contact elements |
US7579269B2 (en) | 1993-11-16 | 2009-08-25 | Formfactor, Inc. | Microelectronic spring contact elements |
US6376913B1 (en) * | 1998-08-13 | 2002-04-23 | Siemens Aktiengesellschaft | Integrated semiconductor chip having leads to one or more external terminals |
US6713374B2 (en) | 1999-07-30 | 2004-03-30 | Formfactor, Inc. | Interconnect assemblies and methods |
US6780001B2 (en) | 1999-07-30 | 2004-08-24 | Formfactor, Inc. | Forming tool for forming a contoured microelectronic spring mold |
US6939474B2 (en) | 1999-07-30 | 2005-09-06 | Formfactor, Inc. | Method for forming microelectronic spring structures on a substrate |
US7189077B1 (en) | 1999-07-30 | 2007-03-13 | Formfactor, Inc. | Lithographic type microelectronic spring structures with improved contours |
US7435108B1 (en) | 1999-07-30 | 2008-10-14 | Formfactor, Inc. | Variable width resilient conductive contact structures |
US7524194B2 (en) | 1999-07-30 | 2009-04-28 | Formfactor, Inc. | Lithographic type microelectronic spring structures with improved contours |
US7675301B2 (en) | 1999-07-30 | 2010-03-09 | Formfactor, Inc. | Electronic components with plurality of contoured microelectronic spring contacts |
US6888362B2 (en) | 2000-11-09 | 2005-05-03 | Formfactor, Inc. | Test head assembly for electronic components with plurality of contoured microelectronic spring contacts |
US7245137B2 (en) | 2000-11-09 | 2007-07-17 | Formfactor, Inc. | Test head assembly having paired contact structures |
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