JPS5818947A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS5818947A
JPS5818947A JP56117436A JP11743681A JPS5818947A JP S5818947 A JPS5818947 A JP S5818947A JP 56117436 A JP56117436 A JP 56117436A JP 11743681 A JP11743681 A JP 11743681A JP S5818947 A JPS5818947 A JP S5818947A
Authority
JP
Japan
Prior art keywords
island
lead frame
semiconductor element
plating layer
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56117436A
Other languages
Japanese (ja)
Inventor
Shigeo Sasaki
栄夫 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56117436A priority Critical patent/JPS5818947A/en
Publication of JPS5818947A publication Critical patent/JPS5818947A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive the cost reduction of a lead frame by a method wherein only the surfaces of the tips of inner leads are plated by Au, Ag, or Ni. CONSTITUTION:Only the surfaces of the tips of inner leads 12 are plated 13 by Au, Ag, or Ni and plating is not applied to an island 11. This composition has a semiconductor element 14 is mounted on the island 11 by epoxy resin paste and the pad of the element is connected 15 to a plating layer 13. This composition remarkably reduces a manufacturing cost and the cost is reduced by 68% in the case of the number of connections 15.

Description

【発明の詳細な説明】 本発明は、リードフレームの改良に関する。[Detailed description of the invention] The present invention relates to improvements in lead frames.

従来、例えば第１図に示す如く、半導体素子が装着され
るアイランド１とこのアイランド１０表面して設けられ
た多数本のインナーリード２とからなるリードフレーム
３は、アイランド１０表面の全域とインナーリード２の
先端部の表面領域に金、銀、或はニッケルのメッキ層４
を形成した構造になりている。而して、第２図に示す如
く、アイランド１上に半導体素子５を装着すると共に、
半導体素子５０をンディングパッドとインナーリード２
のメッキ層４との間に一ンティｙグ線６を架設している
。しかしながら、例えば消費電力の小さな相補型の半導
体素子５などのようなエポキシ系樹脂のペーストにより
て半導体素子５をアイランド１上和装着する場合には、
アイランド１上のメッキ層４は全く不要である。このた
め従来のり−ド７レーム３は、製造コストを十分に低減
させることができなかった。Conventionally, as shown in FIG. 1, for example, a lead frame 3 is made up of an island 1 on which a semiconductor element is mounted and a large number of inner leads 2 provided on the surface of the island 10. A gold, silver, or nickel plating layer 4 is applied to the surface area of the tip of 2.
It has a structure that forms. Then, as shown in FIG. 2, the semiconductor element 5 is mounted on the island 1, and
The semiconductor element 50 is connected to the landing pad and the inner lead 2.
A ting line 6 is installed between the plated layer 4 of However, when mounting the semiconductor element 5 on the island 1 using an epoxy resin paste, such as a complementary semiconductor element 5 with low power consumption, for example,
The plating layer 4 on the island 1 is completely unnecessary. For this reason, the conventional adhesive 7 frame 3 has not been able to sufficiently reduce manufacturing costs.

本発明は、かかる点に艦みてなされたもので、製造コス
トの低減を図ったリードフレームを提供するものである
。The present invention has been made in view of this problem, and provides a lead frame with reduced manufacturing costs.

以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

第３図は、本発明の一実施例の平面図である。FIG. 3 is a plan view of one embodiment of the present invention.

このリードフレーム１０は、半導体素子が装着されるア
イランド１１と、このアイランド１１に対向して般社ら
れた多数本のインナーリード１２とで形成されてお）、
インナーリード１２の先端部の表面領域にのみＡｕ、Ａ
ｇｂ或はＮｌなどからなるメッキ層１３が形成されてい
る。This lead frame 10 is formed of an island 11 on which a semiconductor element is mounted, and a large number of inner leads 12 placed opposite to this island 11).
Au and A are applied only to the surface area of the tip of the inner lead 12.
A plating layer 13 made of Gb or Nl is formed.

つｔシ、アイランド１１の表面にはメッキ層１３は形成
されていなく下地の表面が直接露出されている。ここで
、インナーリード１２に形成されるメッキ層１３の大き
さは、半導体素子の仕様に応じて架設されるボンディン
グ線の長さ郷に応じて適宜設定するのが望ましい。However, the plating layer 13 is not formed on the surface of the island 11, and the underlying surface is directly exposed. Here, the size of the plating layer 13 formed on the inner lead 12 is desirably set appropriately according to the length of the bonding wire to be installed according to the specifications of the semiconductor element.

而して、このように構成されたリードフレームＩＯＫよ
れば、第４図に示す如く、例えばエポキシ系の樹脂ペー
ストを介して半導体素子１４をアイランド１ノ上に装着
し、半導体素子１４上のメンディングパッドとインナー
リード１２のメッキ層１３間にボンディング＠１５を架
設することにより、半導体装置１６を製造することがで
きる。According to the lead frame IOK constructed in this way, as shown in FIG. A semiconductor device 16 can be manufactured by providing bonding@15 between the plating layer 13 of the inner lead 12 and the bonding pad.

この半導体装置１６では、アイランド１１上にはメッキ
層１３が全く形成されていないので、例えば半導体素子
１４の大きさくチップサイズ）が４×４鰭で必要なメン
ディング線１５の数が１５本の場合には、従来のアイラ
ンド上にもメッキ層を形成したものに比べて製造コスト
を６８１ｓ低減させることができる。また、半導体素子
１４の大きさが４×４箇でがンノイング線１５の本数が
４０本の場合には、同様に従来のアイランド上にメッキ
層を有するものに比べて製造コストを５７１低減させる
ことができる。In this semiconductor device 16, since no plating layer 13 is formed on the island 11, for example, if the size of the semiconductor element 14 (chip size) is 4×4, the number of mending lines 15 required is 15. In this case, the manufacturing cost can be reduced by 681 seconds compared to the conventional structure in which a plating layer is also formed on the island. Furthermore, in the case where the size of the semiconductor element 14 is 4×4 and the number of coating lines 15 is 40, the manufacturing cost can be similarly reduced by 571 points compared to the conventional one having a plating layer on an island. I can do it.

以上説明した如く、本発明に係るリードフレームによれ
ば、アイランド上にはメッキ層を形成せず罠インナーリ
ードの表面にのみ形成するようにしたので、製造コスト
を著しく低減させることができるものである。As explained above, according to the lead frame according to the present invention, since the plating layer is not formed on the island but only on the surface of the trap inner lead, the manufacturing cost can be significantly reduced. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来のり−ド７レー°ムの平面図、第２図は
、同リードフレームに半導体素子を装着してボンディン
グ線を架設した状態を示す平面図、第３図は、本発明の
一実施例の平面図、第４図は、同実施例のリードフレー
ムに半導体素子を装着してビンディング線を架設した状
態を示す平面図である。 １０・・・リードフレーム、１１・・・アイランド、１
２・・・インナーリード、１３・・・メッキ層、１４・
・・半導体素子、１５・・・ボンディング線、１６・・
・半導体装置。 出願人代理人　　弁理士　鈴　江　武　彦第１図　　　
　第２図 第３図　　　　　第４図 Ｋ　　　　　　　　　坦FIG. 1 is a plan view of the conventional lead frame 7 frame, FIG. 2 is a plan view showing a state in which a semiconductor element is mounted on the same lead frame and bonding wires are installed, and FIG. 3 is a plan view of the present invention. FIG. 4 is a plan view of one embodiment of the present invention, showing a state in which a semiconductor element is mounted on a lead frame of the same embodiment and binding lines are installed therein. 10...Lead frame, 11...Island, 1
2... Inner lead, 13... Plating layer, 14.
...Semiconductor element, 15...Bonding wire, 16...
・Semiconductor equipment. Applicant's agent Patent attorney Takehiko Suzue Figure 1
Figure 2 Figure 3 Figure 4 K Flat

Claims (1)

【特許請求の範囲】[Claims] 半導体素子が装着されるアイランドと、該アイランド九
対向して設けられたインナーリードと、蚊インナーリー
ドの先端部の表面領域に形成された金、銀、或はニッケ
ルからなるメッキ層とを具備することを特徴とするリー
ドフレーム・It comprises an island on which a semiconductor element is mounted, an inner lead provided opposite to the island, and a plating layer made of gold, silver, or nickel formed on the surface area of the tip of the mosquito inner lead. A lead frame characterized by
JP56117436A 1981-07-27 1981-07-27 Lead frame Pending JPS5818947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56117436A JPS5818947A (en) 1981-07-27 1981-07-27 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56117436A JPS5818947A (en) 1981-07-27 1981-07-27 Lead frame

Publications (1)

Publication Number Publication Date
JPS5818947A true JPS5818947A (en) 1983-02-03

Family

ID=14711597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56117436A Pending JPS5818947A (en) 1981-07-27 1981-07-27 Lead frame

Country Status (1)

Country Link
JP (1) JPS5818947A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231322A (en) * 2008-03-19 2009-10-08 Renesas Technology Corp Manufacturing method of semiconductor device
CN105702656A (en) * 2014-12-10 2016-06-22 意法半导体私人公司 Integrated circuit device with plating on lead interconnection point and method of forming the device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51130170A (en) * 1975-05-07 1976-11-12 Nec Corp Ic lead frame process
JPS5373969A (en) * 1976-12-14 1978-06-30 Toshiba Corp Lead frame for semicinductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51130170A (en) * 1975-05-07 1976-11-12 Nec Corp Ic lead frame process
JPS5373969A (en) * 1976-12-14 1978-06-30 Toshiba Corp Lead frame for semicinductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231322A (en) * 2008-03-19 2009-10-08 Renesas Technology Corp Manufacturing method of semiconductor device
CN105702656A (en) * 2014-12-10 2016-06-22 意法半导体私人公司 Integrated circuit device with plating on lead interconnection point and method of forming the device

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