JPS58187089A - Encoding and decoding system between frames - Google Patents

Abstract

PURPOSE:To reduce the deterioration in the picture quality in the encoding and decoding system between frames, by eliminating deframing in response to the increase in the amount of information generation and selecting the deframing system in the order of less deterioration in the picture quality. CONSTITUTION:An input signal is changed in the order of production at a preprocessing device 2 and outputted to a subtractor 6. The subtractor 6 subtracts the output picture element of a selection circuit 7 from the output value of the circuit 2 to obtain a difference between frames. A quantitizer 8 quantitizes the difference between the frames, transmits a represented value to an adder 10 and a code representing the quantitized value to a variable length encoding circuit 9. The circuit 9 assigns a short code to a code having high frequency of generation and a long code to a code having less frequency, and outputs the code to a buffer memory 14.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interframe coding/decoding method for suppressing redundancy contained in television signals and transmitting the signals economically.

In the interframe coding/decoding method, the transmitting side calculates the difference between the previous frame signal stored in the frame memory and the input signal, encodes and transmits the difference signal, and the receiving side decodes it to create an image. It is meant to reproduce.

In this method, variable length coding is introduced with the aim of improving coding efficiency, so data is generated unevenly.In order to match this unevenly generated data to a constant transmission rate, Graffa memory is used for speed smoothing.

For example, the graphics memory has two memories that store data for four fields, writes variable length codes alternately in four fields, and smoothes data from the memory that is not in the writing period. A double-buffer configuration is used that reads at the code transmission rate.

However, when the movement is intense, information may be generated that exceeds the smoothing ability of the buffer memory. This state is called an overflow, and normal images cannot be reproduced. Therefore, the occupied amount of the buffer memory is monitored, and when the occupied amount exceeds a predetermined threshold, an encoding stop signal is sent to the prediction circuit, and the prediction circuit performs quantization. Output generation is stopped to prevent overflow.

In the conventional method of resetting the encoding stop signal every 4 fields and setting the encoding stop signal when the graph memory occupancy exceeds a predetermined threshold, The order of the first cycle is (F
lo, Fle' + F1a, F1a) (however, the numbers represent frame numbers, and 0 and e represent odd and even fields, respectively), so when the encoding stop signal is sent in the fourth field, On the receiving side, F1a whose encoding has been stopped is dropped (Flo
, Fle, F1a, F1a). Also, when encoding is stopped in the third field, F1a and F1a are dropped on the receiving side (Flo,
Fle, Flo '+ Fle), and when the encoding is stopped in the second field, (F 1 o I F
1 o +Flo, Flo), respectively.

Since this method uses frame dropping, it has the disadvantage that the image quality of moving images is extremely degraded.

The present invention is designed to avoid frame drop as the amount of information generated increases, and to select frame drop methods in order of decreasing image quality deterioration. The method is to realize it.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
(a) shows a transmitter, (b) shows a receiver, ■ is a signal input terminal, 2 is a preprocessing circuit, 3 and 4 are field delay circuits, 5 and 7 are selection circuits, 6 is a subtracter, and 8 is a Quantizer, 9
is a variable length encoding circuit, 1o is an adder, 11.12 and 1
3 is a field delay circuit, 14 is a buffer memory, 15
is a code output terminal, which constitutes the transmitter (a) so far.

The following components constitute the receiving section (b): 16 is a code input terminal, 17 is a grapher memory, 18 is a variable modulation decoding circuit, 19 is an adder, 20 and 21 are selection circuits, 22.2
3 and 24 are field delay circuits, 25 is a signal output terminal, and 101 to 117 and 201, 202 are signal lines.

Next, the operation will be explained.

First, a digitized television signal is input from a signal input terminal 1 to a preprocessing circuit 2.

The preprocessing circuit 2 is composed of field delay circuits 3 and 4 and a selection circuit 5, and the input signal is sent to the field delay circuit 3.
and is input to the selection circuit 5. The output of the field delay circuit 3 is input to the field delay circuit 4 and the selection circuit 5, and the output of the field delay circuit 4 is input to the selection circuit 5. The selection circuit 5 switches the signal to be selected for each field and outputs it to the subtracter 6.

FIG. 2 shows an operation time chart of the selection circuit 5, where A, B, and C are signals on signal lines 101, 102, and 103, respectively, in the preprocessing circuit 2, numbers are frame numbers, and 0 and e are Indicates odd and even fields, eg Fl.

O indicates the odd field signal of the first frame. The preprocessing circuit 2 changes the order of occurrence of the input signals by setting four fields in one week. , B').

This preprocessing device 2 generates input signals (Flo, Fle.

The order of occurrence has been changed from (F1a, F1a) to (F1a, F1a)
lo.

F1a + Fle + F2e) is output to the subtracter 6.

A subtracter 6 subtracts the output pixel value of the selection circuit 7 from the output value of the preprocessing circuit 2 to obtain an interframe difference value. Quantizer 8
quantizes the inter-frame difference value and adds the representative value to adder 1
0, and also sends a code representing the quantized value to the variable length encoding circuit 9.

The adder 10 adds the output value of the selection circuit 7 to the quantized representative value and inputs this to the field delay circuit 11.

The output of the field delay circuit 11 is the output of the field delay circuit 1.
The output of the field delay circuit 12 is input to the field delay circuit 13 and simultaneously input to the selection circuit 7, and the output of the field delay circuit 13 is input to the selection circuit 7. be done.

The selection circuit 7 changes the order of occurrence of the fields to enable interframe predictive coding, and its output is sent to the subtracter 6 and adder 10.

On the other hand, the variable length encoding circuit 9, which receives the code representing the quantized value from the quantizer 8, assigns short codes to codes that occur frequently and long codes to codes that occur less frequently, and outputs the obtained codes. The variable length code is input to the graph memory 14.

- The graph memory 14 matches the received code with the transmission speed and outputs it to the transmission line from the code output terminal 15, but if there is a risk of overflow, it outputs an encoding stop signal just before the overflow to stop it. When this is input, the quantizer 8 outputs the quantized output as O.
Next, the operation of the receiving section (b) will be explained.

The code input from the code input terminal 16 is matched with the sampling rate of the image signal in the buffer memory 17 and output as a variable length code. This variable length code is converted by the variable length decoding circuit 18 into a prediction error signal expressed as an equal length code, and is input to the adder 19. The adder 19 adds the prediction error signal input from the variable length decoding circuit 18 to the previous frame image signal input from the selection circuit 20 to obtain a decoded signal.

The decoded signal is input to the selection circuit 21 and simultaneously input to the field delay circuit 22, and the output of the field delay circuit 22 is input to the selection circuits 20 and 21 and the field delay circuit 23.
The output of the field delay circuit 23 is input to the selection circuits 20 and 21 and the field delay circuit 24, and the output of the field delay circuit 24 is input to the selection circuits 20 and 21.

The selection circuit 20 selects one of the output signals of the field delay circuits 22, 23, 24 and outputs it to the adder 19.
3.24 outputs are input, one of the signals is selected and outputted from the signal output terminal 25 as a dinotal television signal.

FIG. 3 is an embodiment diagram showing the details of the configuration of the buffer memory 14 used in the transmitter (a) of FIG. Memory for storing encoded data for hours; 2;
9 is a selection circuit, and 30 is an encoding stop signal setting circuit.

Encoded data from the variable length encoding circuit 9 shown in FIG. are written alternately.

Reading from the memories 27 and 28 is performed when it is not the write period, and the selection circuit 29 selects the output of the memory during the read period and sends it from the output terminal 15.

The code stop signal setting circuit 30 monitors the amount of data being written in the memory 27 or the memory 28 and resets the code stop signal at a change point of the change control signal.

FIG. 4 is an embodiment diagram showing the details of the configuration of the buffer memory 17 used in the receiving section (b) of FIG.
Memory for storing encoded data for one time period, 34
is a selection circuit.

Data input from the code input terminal 16 is written alternately into the memories 32 and 33 by a switching control signal generated by a buffer memory switching control circuit 31. Reading from memory is performed when it is not a write period. The selection circuit 34 selects the output of the memory during the read period and sends code data from the signal line 202.

Next, the operations of the selection circuits 7, 2o and 21 in FIG. 1 will be explained in detail using the time charts shown in FIGS. 5 and 6.

In the figure, 35 indicates the control unit of the buffer memory, and ] indicates that some data in the field has been encoded or decoded, and stock indicates that no encoded data is included, and - indicates data that has been previously encoded and decoded.

(1) First, when the encoding stop signal is not set during the 4-field period, which is the control unit.

On the transmitting side, the selection circuit 7 is operated as shown in FIG. 5(1). As a result, the signal on signal line 104 and the signal on signal line 10
The relationship is one frame time apart from the signal on 9, and the subtracter 6 can calculate the interframe difference and realize interframe coding.

On the receiving side, the selection circuit 20 is operated as shown in FIG. 6(1). As a result, the signal on the signal line 111 and the signal on the signal line 11
Since the signal above 6 has a one-frame time difference, inter-frame decoding can be realized by the adder 19. Furthermore, by operating the selection circuit 21 as shown in FIG. 6(1), the four fields are sent out in the original order of occurrence. This decodes all fields.

(2) Next, when the encoding stop signal is set during encoding of the internal phase 4 fields of 4 fields that are the control unit.

On the transmitting side, the selection circuit 7 is operated as shown in FIG. 5(2).

On the receiving side, as shown in FIG. 6(2), a selection circuit 20',
Operate 21. As a result, in the reproduced image sent from the selection circuit 21, the fourth field is omitted, and the third field is omitted.
The field signal is interpolated and displayed.

(3) When the encoding stop signal is still set while encoding the internal phase 3 fields of 4 fields that are the control unit.

Each selection circuit is operated as shown in FIG. 5 (3) on the transmitting side and as shown in FIG. 6 (3) on the receiving side. As a result, the reproduced image becomes fieldless, and the second. The 4th field is the 1st
．． The signal of the third field is interpolated and displayed.

(4) When the encoding stop signal is set during encoding of two inner cylinder fields of four fields, which are control units.

Each selection circuit is operated as shown in FIG. 5 (4) on the transmitting side and as shown in FIG. 6 (4) on the receiving side. As a result, the second result. Third
．． In the fourth field, frames are omitted and the image of the first field is repeatedly displayed.

(5) Finally, when the encoding stop signal is set while encoding one field of the inner cylinder of four fields, which is a control unit.

Each selection circuit is operated as shown in FIG. 5 (5) on the transmitting side and as shown in FIG. 6 (5) on the receiving side. As a result, the encoded image of the first field becomes the encoded image of the second field. The signals are displayed repeatedly in the third and fourth fields, and for images that have not been encoded, the signals remaining in the frame memory are output and displayed repeatedly.

That is, in this system, the field position of the encoded stop signal is used to indicate the amount of information generated, and as the amount of information generated increases, the frame drop method is sequentially switched to a frame dropping method with a high frame drop rate.

As explained above, this method uses 4
Among the fields, the frame dropping method is sequentially switched to dropping frames for one field, dropping frames for two fields, and dropping frames for three fields. By changing the order in which the fields occur, it is possible to avoid dropping frames and select the frame dropping method in the order of decreasing image quality deterioration depending on the amount of information generated.

Therefore, there is an advantage that the image quality in interframe coding can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an operation time chart of the selection circuit 5 in FIG. 1, and FIG.
The figure shows buffer memory 1 used in the transmitting section (,) in Figure 1.
FIG. 4 is an embodiment diagram showing the details of the configuration of the buffer memory 17 used in the receiving section (b) of FIG. 1, and FIGS. 5) and FIGS. 6(1) to (5) show operation time charts of the selection circuit 7 and selection circuit 20, 21 of FIG. 1, respectively. 1...Signal input terminal, 2...Pre-processing circuit, 3,4°11+12. li, 22, 23.24...Field delay circuit, 5, 7, 20, 21, 29.34...Selection circuit, 6...Subtractor, 8...Quantizer, 9...Variable Long encoding circuit, 10.19... Adder, 14.17.
... Buffer memory, 15... Sign output terminal, 16.
... code input terminal, 18 ... variable length decoding circuit, 25.
・Signal output terminal, 26.31 ・Paper memory switching control circuit, 27.28, 32.33 ・Memory, 3
0...Encoding stop signal setting circuit. -53,1- Figure 3 Figure 4

Claims (1)

[Claims] A frame in which a television signal is encoded on the transmitting side, unevenly generated data is smoothed by a buffer memory and transmitted at a constant speed, and the data is decoded on the receiving side to obtain a television signal. In the intercoding decoding system, four fields (Flo, Fle, F
1a, F2e) (However, the numbers are frame numbers,
o and e are odd fields respectively. Indicates that it is even). ) as one period, a signal (Flo, F1a, Fle, F2e) in which the order of occurrence of the second and third fields of the input signal is changed, and an interframe predicted value of the previous frame in which the order of occurrence of the decoded signal is changed. (FOo + Flor F
inter-frame predictive coding is performed using OE+Fle), and the prediction error signal is matched to the transmission speed of the transmission path using a buffer memory and sent out to the transmission path, and
If the encoding stop signal sent from the buffer memory immediately before the flow does not occur for a period of 4 fields, all fields are encoded and after decoding on the receiving side, (Flo, Fl
e, F1a, F2e) and return the occurrence order to the original and output it. When encoding is stopped in the fourth field of the four-field period, the receiving side outputs (Flo, F2e).
le , F1a , F1a , and when the encoding is stopped in the third field, it is outputted as (Flo , Flo . F1a , F1a ), and when the encoding is stopped in the second field, it is outputted as (Flo , Flo , Fl
An interframe coding/decoding method characterized in that it outputs (o, Flo).